KR20160083370A - Display Device - Google Patents

Abstract

The present invention relates to a display device which includes a display panel, a driving part, a timing control part, and a power supply part. The display panel displays an image. The driving part drives the display panel. The timing control part controls the driving part. The power supply part corresponds to a power control signal outputted from the timing control part and generates and outputs a high potential voltage and a low potential voltage to the display panel. The power supply part includes a protection circuit part which transmits a power control signal supplied from the timing control part to another node when a short is generated in the output terminal of the power supply part. So, damage to a device or the risk of a fire can be prevented.

Description

[0001]

The present invention relates to a display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device and an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form, a driver for driving the display panel, and a timing controller for controlling the driver. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

The display device displays a specific image as the display panel emits or transmits light based on the voltage output from the power supply unit and the scan signal and the data signal output from the scan driver and the data driver.

The display device may be short-circuited between the high-potential voltage and the low-potential voltage output from the power supply unit due to a foreign matter or a mechanical problem occurring in the manufacturing process or assembly. However, in the display device proposed in the related art, if a short circuit occurs after the output terminal of the power supply part, the device is seriously damaged and there is a risk of fire.

The present invention for solving the problems of the background art is to prevent a problem caused by a damage of the apparatus or a fire even if a short circuit occurs due to a foreign matter or a mechanical problem occurring in the manufacturing process or assembly.

The present invention relates to a display device including a display panel, a driving unit, a timing control unit, and a power supply unit. The display panel displays the image. The driving unit drives the display panel. The timing control unit controls the driving unit. The power supply unit generates and outputs a high potential voltage and a low potential voltage to be supplied to the display panel in response to the power supply control signal output from the timing control unit. The power supply unit includes a protection circuit unit for transmitting a power supply control signal supplied from the timing control unit to another node when a short circuit occurs at an output terminal of the power supply unit.

The protection circuit part can deliver the power supply control signal supplied from the timing control part to a node which is applied with a low potential voltage when a short circuit occurs.

The power supply part includes a sequence circuit part including a first transistor and a second transistor and a power generation part for outputting an input power supplied from the outside under the control of the sequence circuit part to a high potential voltage, To the gate electrode of the second transistor, and to transmit the power control signal to the node between the first transistor and the power generation unit in the abnormal operation.

The first transistor has a gate electrode connected to a drain electrode of the second transistor, a source electrode connected to a line through which input power is transmitted, a drain electrode connected to an input terminal of the power generation unit, A source electrode is connected to a gate electrode of the first transistor, a drain electrode is connected to a gate electrode of the first transistor, and a source electrode is connected to a line through which a low potential voltage is transmitted. The first electrode is connected to a line, A second electrode may be connected to a drain electrode of one transistor.

The protection circuitry may comprise a diode.

The protection circuit may be a diode in which an anode electrode is connected to a line through which a power supply control signal is transmitted, and a cathode electrode is connected to a drain electrode of the first transistor.

The present invention is designed to stably stop the operation of the power supply unit in the event of a short circuit due to foreign matter or mechanical problems occurring in the manufacturing process or assembly, thereby preventing the problems caused by the damage of the apparatus or the risk of fire have.

1 is a block diagram schematically showing a display device;
Fig. 2 is a schematic view showing the subpixel shown in Fig. 1. Fig.
Fig. 3 is an example of modularization of the display device of Fig. 1; Fig.
4 is a view showing a part of the apparatus for explaining the operation of the power supply unit;
5 is a diagram illustrating a configuration example of a power supply unit according to an experimental example;
6 is a graph showing a change in node voltage due to the occurrence of a short circuit in an experimental example;
7 is a diagram illustrating a configuration example of a power supply unit according to an embodiment of the present invention;
8 is a diagram showing a change in node voltage due to a short-circuit occurrence of a temporal example of the present invention.
9 is a view for explaining a state before and after a shot of a temporal example of the present invention.
10 is a view showing an example of a protection circuit;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The display device according to the present invention is implemented as a television, a set-top box, a navigation device, a video player, a Blu-ray player, a personal computer (PC), a home theater and a mobile phone. The display panel of the display device may be a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, a plasma display panel, or the like, but is not limited thereto. In the following description, an organic electroluminescent display device will be described as an example for convenience of explanation.

FIG. 1 is a block diagram schematically showing a display device, FIG. 2 is a schematic diagram showing the subpixel shown in FIG. 1, and FIG. 3 is an example of modulating the display device of FIG.

1, the display device includes an image supply unit 110, a timing control unit 120, a scan driving unit 130, a data driving unit 140, a display panel 150, and a power supply unit 180.

The image supply unit 110 processes the data signal and outputs the image signal together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The image supply unit 110 supplies a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and a data signal to the timing controller 120 (LVDS) through an LVDS (Low Voltage Differential Signaling) interface or a TMDS (Transition Minimized Differential Signaling) .

The timing controller 120 receives a data signal DATA from the image supplier 110 and receives a gate timing control signal GDC for controlling the operation timing of the scan driver 130 and an operation timing of the data driver 140 And outputs a data timing control signal (DDC)

The timing controller 120 outputs the data signal DATA together with the gate timing control signal GDC and the data timing control signal DDC through the communication interface and outputs the data signal DATA to the scan driver 130 and the data driver 140 .

The scan driver 130 outputs a scan signal (or a gate signal) while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 includes a level shifter and a shift register.

The scan driver 130 supplies the scan signals to the sub-pixels SP included in the display panel 150 through the scan lines GL1 to GLm. The scan driver 130 is formed in the form of an integrated circuit (IC) or a gate-in-panel type display panel 150. The portion of the scan driver 130 formed in a gate-in-panel manner is a shift register.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 and converts the digital signal into an analog signal corresponding to the gamma reference voltage and outputs the analog signal .

The data driver 140 supplies the data signal DATA to the sub-pixels SP included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 is formed in the form of an integrated circuit (IC).

The power supply unit 180 generates and outputs voltages such as a high-potential voltage (VDD) and a low-potential voltage (GND) based on a voltage output from the outside. The high potential voltage (VDD) and the low potential voltage (GND) output from the power supply unit 180 are supplied to the display panel 150. The power supply unit 180 may generate a voltage to be supplied to the timing controller 120, the scan driver 130, and the data driver 140.

The display panel 150 displays an image corresponding to the scan signal supplied from the scan driver 130 and the data signal DATA supplied from the data driver 140. The display panel 150 includes sub-pixels SP.

As shown in FIG. 2, one subpixel is supplied through a switching thin film transistor SW and a switching thin film transistor SW which are connected (or formed at intersections) to a scan line GL1 and a data line DL1 And a pixel circuit PC that operates in response to the data signal DATA. The subpixels SP consist of a liquid crystal display panel including a liquid crystal element according to the configuration of the pixel circuit PC or an organic light emitting display panel including an organic light emitting element.

When the display panel 150 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 150 is formed of an organic light emitting display panel, the display panel 150 may be implemented as a top emission type, a bottom emission type, or a dual emission type.

3, the display device includes a system board 115, a timing circuit board 125, a cable 111, drive circuit boards 135a, 135b, 145a and 1450b, and a display panel 150 It is made in module form.

The system board 115 includes an image supply unit 110 and a main power supply unit 190. The image supply unit 110 is mounted on the system board 115 in the form of an integrated circuit (IC). The main power supply unit 190 converts the AC power into DC power and outputs the AC power.

The DC power outputted from the main power supply unit 190 is supplied to the image supply unit 110, the power supply unit 160, and the like. The system board 115 may be selected from a printed circuit board (PCB) or a flexible printed circuit board (FPCB), but is not limited thereto.

The cable 111 electrically connects the system board 115 and the timing circuit board 125. The cable 111 may be selected as a flexible flat cable (FFC), but is not limited thereto.

A timing control unit 120 and a power supply unit 180 are disposed on the timing circuit board 125. The timing control unit 120 and the power supply unit 180 are mounted on the timing circuit board 125 in the form of an integrated circuit (IC).

The power supply unit 160 generates and outputs power based on the DC power supplied from the main power supply unit 190. The timing circuit board 125 may be selected as a printed circuit board (PCB) or a flexible circuit board (FPCB), but is not limited thereto.

The scan driver 130a and the scan driver 130b and the data drivers 140a and 140b are located on the driving circuit boards 135a, 135b, 145a, and 1450b. The scan drivers 130a and 130b and the data drivers 140a and 140b are mounted on the driver circuit boards 135a, 135b, 145a, and 1450b in the form of an integrated circuit (IC). The driving circuit boards 135a, 135b, 145a, and 1450b may be selected as a printed circuit board (PCB) or a flexible circuit board (FPCB), but are not limited thereto.

The driver circuit boards 135a, 135b, 145a and 1450b are connected to the first driver circuit boards 135a and 135b on which the scan drivers 130a and 130b are mounted and the second driver circuit board 135b on which the data drivers 140a and 140b are mounted. 145a and 145b.

The first driving circuit boards 135a and 135b are connected to the left side of the display panel 150 and the second driving circuit boards 145a and 145b are connected to the upper side of the display panel 150. [ However, this is only an example, and may be varied corresponding to the resolution and size of the display panel 150. [ When the scan driver 130a or 130b is formed in the bezel region of the display panel 150 in the form of a gate panel, the first driver circuit boards 135a and 135b are omitted.

The display device may be configured such that the display panel 150 emits light or emits light based on the voltage output from the power supply unit 180 and the scan signal and the data signal DATA output from the scan driver 130 and the data driver 140, As a result, a specific image is displayed.

On the other hand, a short circuit between the high-potential voltage and the low-potential voltage output from the power supply unit 180 may occur due to a foreign object or a mechanical problem occurring in the manufacturing process or assembly. However, if a short circuit occurs after the output terminal of the power supply unit 180, the conventional display apparatus may cause a serious damage to the apparatus and possibly cause a fire.

In order to solve the above problems, a method for securing the safety of a device in the event of a short circuit is sought.

4 is a diagram showing a part of the apparatus for explaining the operation of the power supply unit.

4, the power supply unit 180 is configured to supply the input power VIN of the DC voltage supplied from the main power supply unit 190 corresponding to the power supply control signal DPM output from the timing control unit 120, (VDD) and a low potential voltage (GND) are generated and output.

The power supply unit 180 has a sequence circuit unit for matching a sequence with other voltages. The sequence circuit part may differ depending on the characteristics of the voltage required by the device and the configuration of the circuit, but the present invention is embodied on the basis of one experimental example.

FIG. 5 is a diagram illustrating a configuration of a power supply unit according to an experimental example, and FIG. 6 is a diagram illustrating a change in a node voltage due to a short circuit in an experimental example.

[Experimental Example]

As shown in FIGS. 5 and 6, the power supply unit 180 according to the experimental example includes the power generation unit 185 and the sequence circuit units TR1 and TR2. Quot; C1 and C2 "denote first and second capacitors formed at the input terminal of the power supply unit 180, and R1 to R4 denote first and second capacitors connected to the sequence circuit units TR1 and TR2 and the power generation unit 185, respectively. And "RSC" means the reset circuit of the power supply unit 180. The " RSC " In addition to the illustrated passive elements, there is a plurality of elements for protecting, operating, and controlling the circuit, but the power supply 180 is omitted.

The first transistor TR1 is turned on only when the second transistor TR2 is turned on by the power supply control signal DPM output from the timing control unit 120 in the sequence circuit units TR1 and TR2. The explanation is further detailed as follows.

The second transistor TR2 is turned on when the power control signal DPM of the logic high output from the timing controller 120 is supplied to the gate electrode G of the second transistor TR2. When the second transistor TR2 is turned on, a voltage or a current flows between the drain electrode D and the source electrode S of the second transistor TR2.

The first transistor TR1 is turned on as the low potential voltage GND flowing through the drain electrode D and the source electrode S of the second transistor TR2 is supplied to the gate electrode G of the first transistor TR1. When the first transistor TR1 is turned on, a voltage or a current flows between the source electrode S and the drain electrode D of the first transistor TR1.

The first transistor TR1 is turned on after the second transistor TR2 is turned on in the power supply unit 180 according to the experimental example. Therefore, even if the input power supply VIN is supplied to the first node N1 serving as the input terminal, the first transistor TR1 is turned on only after the second transistor TR2 is turned on. There is a time difference DELTA t when the input power supply VIN is supplied to the second node N2.

The voltages V1 and V2 applied to the first node N1 and the second node N2 of the power supply unit 180 are substantially the same before the short circuit occurs. After a short circuit occurs, V1 is applied to the first node N1 of the power supply unit 180, but 0V is applied to the second node N2. 0V is a voltage corresponding to the low potential voltage.

The reason why 0 V is applied to the second node N2 of the power supply unit 180 is that a first output terminal that outputs a high potential voltage VDD due to a short circuit generated after the output terminal of the power supply unit 180, ) Is electrically short-circuited.

The second transistor TR2 is turned on by the power supply control signal DPM of logic high output from the timing controller 120 even if a short circuit occurs after the output terminal of the power supply unit 180. [

In the experimental example, the voltage corresponding to the input power supply voltage VIN and the voltage corresponding to the low potential voltage GND are applied to the first node N1 and the second node N2 of the power supply unit 180, Since one transistor TR1 is turned on, two voltages (VIN and GND collision) collide with each other. When the collision between two voltages VIN and GND collision is continued as described above, not only the first transistor TR1 of the sequence circuit units TR1 and TR2 but also the power generation unit 185 may be damaged (for example, Burnt) The problem of fire caused by the fire can not be avoided.

FIG. 7 is a diagram illustrating a configuration example of a power supply unit according to an embodiment of the present invention. FIG. 8 is a diagram showing a change in a node voltage due to a short circuit of a temporary example of the present invention. Fig. 10 is a diagram showing an example of a protection circuit portion. Fig.

[Example]

7 to 9, a power supply unit 180 according to an embodiment of the present invention includes a power generation unit 185, sequence circuit units TR1 and TR2, and a protection circuit unit 182. [ Quot; C1 and C2 "denote first and second capacitors formed at the input terminal of the power supply unit 180, and R1 to R4 denote first and second capacitors connected to the sequence circuit units TR1 and TR2 and the power generation unit 185, respectively. And "RSC" means the reset circuit of the power supply unit 180. The " RSC " In addition to the illustrated passive elements, there is a plurality of elements for protecting, operating, and controlling the circuit, but the power supply 180 is omitted.

The sequence circuit portions TR1 and TR2 include a first transistor TR1 and a second transistor TR2. The first transistor TR1 has a source electrode S connected to the output terminal of the main power supply unit 190 and a drain electrode D connected to the input terminal of the power generation unit 185, And the gate electrode G is connected.

The second transistor TR2 has a drain electrode D connected to the other end of the first resistor R1 and a source electrode S connected to the low potential voltage line GND, The electrode G is connected. The first and second resistors R1 and R2 are passive elements that are positioned to protect specific electrodes of the first and second transistors TR1 and TR2 from a voltage or a signal or drive them to a specific voltage, Or may be omitted depending on the characteristics of the transistor.

The first transistor TR1 is turned on only when the second transistor TR2 is turned on by the power supply control signal DPM output from the timing control unit 120 in the sequence circuit units TR1 and TR2. The explanation is further detailed as follows.

The second transistor TR2 is turned on when the power control signal DPM of the logic high output from the timing controller 120 is supplied to the gate electrode G of the second transistor TR2. When the second transistor TR2 is turned on, a voltage or a current flows between the drain electrode D and the source electrode S of the second transistor TR2.

The first transistor TR1 is turned on as the low potential voltage GND flowing through the drain electrode D and the source electrode S of the second transistor TR2 is supplied to the gate electrode G of the first transistor TR1. When the first transistor TR1 is turned on, a voltage or a current flows between the source electrode S and the drain electrode D of the first transistor TR1.

The first transistor TR1 is turned on after the second transistor TR2 is turned on in the power supply unit 180 according to an embodiment of the present invention. Therefore, even if the input power source VIN is supplied to the first node N1 as the input terminal, the power supply unit 180 according to the embodiment of the present invention can not supply the first transistor TR1 after the second transistor TR2 is turned on, The input voltage VIN is supplied to the second node N2, so that there is a time difference DELTA t.

The voltages V1 and V2 applied to the first node N1 and the second node N2 of the power supply unit 180 are substantially the same before the short circuit occurs. After a short circuit occurs, V1 is applied to the first node N1 of the power supply unit 180, but 0V is applied to the second node N2. 0V is a voltage corresponding to the low potential voltage.

The reason why 0 V is applied to the second node N2 of the power supply unit 180 is that a first output terminal that outputs a high potential voltage VDD due to a short circuit generated after the output terminal of the power supply unit 180, ) Is electrically short-circuited.

In an embodiment of the present invention, when a short circuit does not occur after the output terminal of the power supply unit 180, it operates as follows. The second transistor TR2 is turned on by the power supply control signal DPM of the logic high output from the timing control unit 120 (1 in Fig. 9 (a)). Since the low potential GND is supplied through the second transistor TR2, the first transistor TR1 is also turned on (2 in FIG. 9A). As the first transistor TR1 is turned on, the input power supply VIN is supplied to the input terminal of the power generator 185 through the first transistor TR1. The power generating unit 185 generates and outputs a high potential voltage VDD to be supplied to the display panel 150 based on the input power VIN.

In an embodiment of the present invention, when a short occurs after the output terminal of the power supply unit 180, the following operation is performed. The power supply control signal DPM of the logic high outputted from the timing control section 120 is supplied to the input terminal of the power generation section 185 through the protection circuit section 182 (1 in FIG. 9 (b)). The second transistor TR2 is turned off because it does not receive the power control signal DPM of logic high. The first transistor TR1 is also turned off because it does not receive the low voltage GND from the second transistor TR1. The power generation unit 185 can not generate and output the high potential voltage VDD to be supplied to the display panel 150 because the input power voltage VIN is not received by the first transistor TR1 turned off.

As described above, according to one embodiment of the present invention, when a short circuit occurs after the output terminal of the power supply unit 180, the power supply control signal DPM of the logic high output from the timing control unit 120 causes the second transistor TR2 ) Is not turned on. In an embodiment of the present invention, the first node N1 and the second node N2 of the power supply unit 180 are connected to the first node N1 through the protection circuit unit 182, And the operation of the second transistors TR1 and TR2 are cut off.

The protection circuit unit 182 outputs the power control signal DPM of the logic high output from the timing control unit 120 when the voltage corresponding to the low potential voltage GND is applied to the second node N2 of the power supply unit 180. [ To the second node N2 located at the drain electrode D of the first transistor TR1. That is, when a short circuit occurs in the output terminal of the power supply unit 180 and the voltage of the second node N2 falls to a voltage corresponding to the low potential voltage GND, the power control signal of logic high output from the timing control unit 120 (DPM) is not supplied to the second transistor TR2 by the protection circuit portion 182 but is pulled to the second node N2.

A voltage corresponding to the input power supply VIN and a voltage corresponding to the low potential voltage GND are applied to the first node N1 and the second node N2 of the power supply unit 180, The operation of the sequence circuit portions TR1 and TR2 is interrupted so that the problem of collision between the two voltages VIN and GND collisions is prevented. As a result, the first transistor TR1 of the sequence circuit units TR1 and TR2 as well as the power generation unit 185 can be prevented from being damaged due to a short circuit (for example, Burnt ) And fire problems caused by this can be avoided.

As shown in Fig. 10, the protection circuit portion 182 may be selected as the diode D1. The protection circuit portion 182 selected by the diode D1 is connected to the power source control signal line through which the power source control signal DPM is transferred and the drain electrode D of the first transistor TR1, (Hereinafter referred to as a cathode electrode) is connected to the second electrode.

The protection circuit portion 182 selected by the diode D1 allows voltage or current to flow in only one direction. When no short circuit occurs after the output terminal of the power supply unit 180, the power supply control signal DPM is transferred to the gate electrode G of the second transistor TR2 because a high voltage is applied to the cathode electrode.

When the diode D1 is formed between the power supply control signal line and the input terminal of the power generation unit, the second transistor TR2 and the first transistor TR1 are sequentially turned on by the power supply control signal DPM during normal operation . Since the voltage applied to the anode electrode of the diode D1 is lower than the voltage applied to the cathode electrode even after the second transistor TR2 and the first transistor TR1 operate, the power supply control signal DPM is supplied to the second transistor TR2, To the gate electrode (G).

On the other hand, when a short circuit occurs after the output terminal of the power supply unit 180, a low voltage is applied to the cathode electrode. Therefore, the power supply control signal DPM is supplied to the first transistor TR1 To the drain electrode (D). The drain electrode D of the first transistor TR1 corresponds to a node to which the low potential voltage GND is applied.

When the diode D1 is formed between the power supply control signal line and the input terminal of the power generation unit 185, the power supply control signal DPM is transferred to the other node in the abnormal operation 1 transistor TR1 will not operate. At this time, since the voltage applied to the anode electrode of the diode D1 is higher than the voltage applied to the cathode electrode, the power supply control signal DPM is transmitted to the node between the drain electrode D of the first transistor TR1 and the input terminal of the power generation unit do.

As a result, since the power supply unit 180 stops the operation of the circuits related to itself under abnormal conditions, it is possible to prevent (damage or fire) problems that may occur throughout the apparatus as well as circuits related thereto.

As described above, the present invention is designed to prevent the problem caused by the damage of the apparatus or the fire by designing the operation of the power supply unit to stop stably in the event of a short circuit due to foreign matter or mechanical problems occurring in the manufacturing process or assembly .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: image supply unit 120: timing control unit
130: scan driver 140:
150: Display panel 180: Power supply unit
185: power generation section TR1, TR2: sequence circuit section
TR1: first transistor TR2: second transistor
182: Protection circuit

Claims (6)

Display panel;
A driving unit for driving the display panel;
A timing controller for controlling the driving unit; And
And a power supply unit for generating and outputting a high potential voltage and a low potential voltage to be supplied to the display panel in response to the power supply control signal output from the timing control unit,
And the power supply unit includes a protection circuit unit for transmitting the power control signal supplied from the timing control unit to another node when a short circuit occurs in an output terminal of the power supply unit. The method according to claim 1,
The protection circuit part
And supplies the power supply control signal supplied from the timing control unit to a node that receives the low potential voltage when the short occurs. The method according to claim 1,
The power supply unit
A sequence circuit section including a first transistor and a second transistor;
And a power generator for outputting the input power supplied from the outside under the control of the sequence circuit part to the high potential voltage,
Wherein the protection circuit part transfers the power supply control signal to the gate electrode of the second transistor during normal operation and transmits the power supply control signal to the node between the first transistor and the power generation part in abnormal operation Display device. The method of claim 3,
A gate electrode is connected to a drain electrode of the second transistor, a source electrode is connected to a line through which the input power is transmitted, a drain electrode is connected to an input terminal of the power generation unit,
A gate electrode of the second transistor is connected to a line through which the power supply control signal is transmitted, a drain electrode is connected to a gate electrode of the first transistor, a source electrode is connected to a line through which the low potential voltage is transmitted,
Wherein a first electrode is connected to a line through which the power control signal is transmitted, and a second electrode is connected to a drain electrode of the first transistor. The method according to claim 1,
Wherein the protection circuit portion includes a diode. 5. The method of claim 4,
The protection circuit part
Wherein the anode is connected to the line through which the power supply control signal is transmitted, and the cathode is connected to the drain electrode of the first transistor.

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