KR102457405B1 - Organic light emitting display panel and organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device, wherein a plurality of sub driving voltage common lines are disposed on one side of an organic light emitting display panel, and a plurality of driving voltage lines spaced apart from each other in each sub driving voltage common line By configuring this to be connected, the flow of overcurrent caused by panel cracks is distributed and distributed not only during normal display operation, but also at the time of power-off sequence driving and power-on sequence driving, without a separate overcurrent prevention circuit or algorithm. By limiting, it is possible to suppress the panel ignition (POL-melting) phenomenon due to overcurrent.

Description

An organic light emitting display panel and an organic light emitting display device including the same

The present embodiments relate to an organic light emitting display device, and more particularly, to a structure for preventing panel damage due to overcurrent in an organic light emitting display panel.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Various display devices such as an organic light emitting diode display device (OLED) are being used.

Among them, the organic light emitting display device, which has recently been spotlighted as a display device, uses an organic light emitting diode (OLED) that emits light by itself, and thus has a fast response speed and a large luminous efficiency, luminance, and viewing angle.

In such an organic light emitting display device, sub-pixels including organic light emitting diodes are arranged in a matrix form, and the brightness of the sub-pixels selected by a scan signal is controlled according to a gray level of data.

A plurality of gate lines GL or scan lines extending in a first direction and a plurality of data lines DL extending in a second direction are formed in the organic light emitting display panel constituting the organic light emitting display device, and the gate lines and An area defined by a data line constitutes one sub-pixel.

An equivalent circuit including an organic light emitting diode, a driving transistor, a plurality of transistors such as a sensing transistor and a switching transistor, and one or more capacitors is implemented in a subpixel included in the organic light emitting display panel, and a driving transistor (DRT) The driving voltage EVDD is input to the source input of the switching transistor SWT, the gate driving voltages V _GH and V _GL are input to the gate input of the switching transistor SWT, and the reference voltage Vref is input to the sensing transistor. have.

As described above, in the organic light emitting display panel, a plurality of power supply voltage lines are formed to supply a plurality of power supply voltage signals EVDD, V _GH , V _GL , and Vref to the sub-pixels, and these voltage lines intersect ( are arranged in a cross) manner.

In this structure, when an external force greater than or equal to a certain level is applied to the panel to cause panel damage such as a panel crack, a voltage greater than a reference value is applied to the data line, and an overcurrent may flow in the driving transistor.

At this time, there is a risk that the heat generation of the panel element continuously increases due to the flowing overcurrent, and the polarization film formed on the upper and lower parts of the panel melts at a certain temperature or higher, leading to Pol-melting of the entire display panel.

In order to solve this problem, an overcurrent detection circuit is added to the display panel in hardware to cut off the input of the power voltage when an overcurrent is detected, or by software to sense the lines at the blanking time to generate abnormal data. In this case, an overcurrent prevention method of cutting off the power input has been proposed.

However, such a hardware or software overcurrent prevention method has disadvantages such as a complicated circuit structure or additional time required to detect abnormal data.

Therefore, there is a need for a method that can replace the existing hardware overcurrent protection circuit or software overcurrent protection algorithm.

Against this background, it is an object of the present invention to provide an organic light emitting display device capable of preventing heating or ignition of a display panel by preventing overcurrent caused by damage to the panel.

Another object of the present invention is to provide an organic light emitting display device capable of preventing overcurrent due to panel damage by changing the structure of the driving voltage common line (EVDD common line) of the organic light emitting display panel.

Another object of the present invention is to arrange a plurality of sub driving voltage common lines (Sub EVDD Common Lines) on one side of an organic light emitting display panel, and to connect a plurality of driving voltage lines spaced apart from each other to each sub driving voltage common line. To provide an organic light emitting display device capable of preventing heating or ignition of a display panel by dispersing a flow path of an overcurrent generated by damage to the panel.

In order to achieve the above object, an embodiment of the present invention provides a plurality of sub-pixels defined by data lines, gate lines, an intersection region of the gate line and the data line, and a driving voltage ( a display area including a plurality of driving voltage lines (EVDD Lines) disposed to apply EVDD; a non-display area disposed perpendicular to the driving voltage line outside the display area and including two or more sub driving voltage common lines electrically connected to one end of at least two driving voltage lines selected from among the plurality of driving voltage lines; It provides an organic light emitting display panel comprising a.

According to another embodiment of the present invention, data lines, gate lines, a plurality of sub-pixels defined by an intersection region of the gate line and the data line, are arranged to apply a driving voltage EVDD to the sub-pixels a display area including a plurality of driving voltage lines (EVDD Lines); a non-display area disposed perpendicular to the driving voltage line outside the display area and including two or more sub driving voltage common lines electrically connected to one end of at least two driving voltage lines selected from among the plurality of driving voltage lines; A display panel comprising: a connection film connected to the display panel at the opposite side of the non-display area where the sub driving voltage common line is disposed, and having a source driver integrated circuit (S-DIC) mounted therein; It provides an organic light emitting display device comprising: a source printed circuit board (S-PCB) connected to a film.

According to an embodiment of the present invention to be described below, by changing the structure of the driving voltage common line (EVDD Common Line) of the organic light emitting display panel, the flow path of the overcurrent generated by the panel damage is dispersed to prevent damage to the panel. It has the effect of preventing overcurrent caused by

More specifically, a plurality of sub driving voltage common lines are disposed on one side of the organic light emitting display panel, and a plurality of driving voltage lines spaced apart from each other are connected to each sub driving voltage common line. By dispersing the flow path of the overcurrent generated by the damage, heating or ignition of the display panel can be prevented.

1 is a system configuration diagram of an organic light emitting display device 100 to which the present invention can be applied.
FIG. 2 shows an example of arrangement of an equivalent circuit and signal lines of each subpixel of an organic light emitting diode display to which the present embodiment can be applied.
FIG. 3 shows several examples of a structure for preventing overcurrent damage. FIG. 3 (a) is a hardware overcurrent protection structure, and FIG. 3(b) shows a software overcurrent protection structure.
FIG. 4 is a diagram illustrating only some components of a general organic light emitting diode display to which the present invention can be applied.
5 is a plan view of an organic light emitting display device according to an exemplary embodiment of the present invention.
6 is an enlarged view illustrating the connection relationship between the sub driving voltage common line and the driving voltage lines according to an embodiment of the present invention and effects thereof.
7 shows a contrast configuration for contrast with an embodiment of the present invention.
8 illustrates an overcurrent flow phenomenon in an organic light emitting diode display according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It should be understood that each component may be “interposed” or “connected,” “coupled,” or “connected” through another component.

1 is a system configuration diagram of an organic light emitting display device 100 to which the present invention can be applied.

Referring to FIG. 1 , in an organic light emitting diode display 100 to which the present invention can be applied, a plurality of data lines DL and a plurality of gate lines GL are disposed, and a plurality of sub-pixels (SP) are provided. The arranged organic light emitting display panel 110 , the data driver 120 driving the plurality of data lines DL, the gate driver 130 driving the plurality of gate lines GL, and the data driver 120 . ) and a controller 140 for controlling the gate driver 130 , and the like.

The controller 140 supplies various control signals to the data driver 120 and the gate driver 130 to control the data driver 120 and the gate driver 130 .

The controller 140 starts scanning according to the timing implemented in each frame, converts the input image data input from the outside to match the data signal format used by the data driver 120, and outputs the converted image data. , control the data drive at an appropriate time according to the scan.

The controller 140 may be a timing controller used in a typical display technology or a control device that further performs other control functions including a timing controller.

The data driver 120 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL. Here, the data driver 120 is also referred to as a 'source driver'.

The data driver 120 may include at least one source driver integrated circuit (S-DIC) to drive a plurality of data lines.

The gate driver 130 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driver 130 is also referred to as a 'scan driver'.

The gate driver 130 may include at least one gate driver integrated circuit (G-DIC).

The gate driver 130 sequentially supplies a scan signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller 140 .

When a specific gate line is opened by the gate driver 130 , the data driver 120 converts the image data received from the controller 140 into an analog data voltage and supplies it to the plurality of data lines DL.

Although the data driver 120 is located only on one side (eg, upper or lower side) of the organic light emitting display panel 110 in FIG. 1 , both sides (eg, the organic light emitting display panel 110 ) according to a driving method and a panel design method. : It may be located both above and below).

Although the gate driver 130 is located only on one side (eg, left or right) of the organic light emitting display panel 110 in FIG. 1 , the gate driver 130 is located on both sides of the organic light emitting display panel 110 according to a driving method, a panel design method, etc. For example, it can be located on both the left and right side).

The above-described controller 140, along with the input image data, a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input data enable (DE: Data Enable) signal, various types including a clock signal (CLK), etc. Timing signals are received from the outside (eg host system).

The controller 140 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), an input DE signal, and a clock signal to control the data driver 120 and the gate driver 130, Various control signals are generated and output to the data driver 120 and the gate driver 130 .

For example, in order to control the gate driver 130 , the controller 140 may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). Various gate control signals (GCS: Gate Control Signal) including Gate Output Enable) are output.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 130 . The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits and controls shift timing of a scan signal (gate pulse). The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140 controls the data driver 120 , a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE: Source Output). Enable) and output various data control signals (DCS: Data Control Signal).

Here, the source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits constituting the data driver 120 . The source sampling clock SSC is a clock signal that controls sampling timing of data in each of the source driver integrated circuits. The source output enable signal SOE controls the output timing of the data driver 120 .

The data driver 120 may drive a plurality of data lines including at least one source driver integrated circuit (SDIC).

Each source driver integrated circuit (S-DIC) is a bonding pad of the organic light emitting display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method. ) or may be directly disposed on the organic light emitting display panel 110 , or may be integrated and disposed on the organic light emitting display panel 110 in some cases. In addition, each source driver integrated circuit SDIC may be implemented in a Chip On Film (COF) method mounted on a film connected to the organic light emitting display panel 110 .

Each source driver integrated circuit (S-DIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, and the like. .

Each source driver integrated circuit (S-DIC) may further include an analog-to-digital converter (ADC) in some cases.

The gate driver 130 may include at least one gate driver integrated circuit (GDIC).

Each gate driver integrated circuit (G-DIC) is connected to a bonding pad of the organic light emitting display panel 110 by a tape automatic bonding (TAB) method or a chip-on-glass (COG) method, or a gate (GIP) method. In Panel) type and may be directly disposed on the organic light emitting display panel 110 , or may be integrated and disposed on the organic light emitting display panel 110 in some cases. In addition, each gate driver integrated circuit (G-DIC) may be implemented in a chip-on-film (COF) method mounted on a film connected to the organic light emitting display panel 110 .

In addition, the organic light emitting display device 100 to which this embodiment can be applied has at least one source printed circuit board (S-PCB) necessary for circuit connection to at least one source driver integrated circuit (S-DIC). Circuit Board) and a control printed circuit board (C-PCB) for mounting control components and various electric devices may be included.

At least one source printed circuit board (S-PCB), at least one source driver integrated circuit (S-DIC) is mounted, or at least one source driver integrated circuit (S-DIC) is mounted on the film may be connected .

The control printed circuit board (C-PCB) includes a controller 140 for controlling operations of the data driver 120 and the gate driver 130 , the organic light emitting display panel 110 , the data driver 120 , and the gate driver. A power management IC (PMIC) that supplies various voltages or currents to 130 or the like or controls various voltages or currents to be supplied may be mounted.

As the power supplied to the organic light emitting display panel 110 by the power controller PMIC, the driving voltage EVDD is provided as a source input of the driving transistor to drive the organic light emitting diode, and the driving voltage EVDD is supplied to switch the switching transistor. There are gate high/low voltages (VGH, VGL) and a reference voltage (Vref).

On the other hand, a plurality of power lines for supplying such power are formed in the organic light emitting display panel 110 , and these power lines are disposed in such a way that they intersect the data lines.

Each subpixel SP disposed on the organic light emitting display panel 110 may include circuit elements such as a plurality of transistors. Specifically, each subpixel SP includes an organic light emitting diode (OLED). diode) and circuit elements such as a driving transistor for driving the diode.

FIG. 2 shows an example of arrangement of an equivalent circuit and signal lines of each subpixel of an organic light emitting diode display to which the present embodiment can be applied.

Referring to FIG. 2 , in the organic light emitting diode display 100 according to the present exemplary embodiments, each sub-pixel basically drives an organic light emitting diode (OLED) and an organic light emitting diode (OLED). A driving transistor (DRT) for transmitting a data voltage to the second node N2 corresponding to the gate node of the driving transistor (DRT) It may be configured to include a storage capacitor (Cstg: Storage Capacitor) that maintains a data voltage or a voltage corresponding thereto for one frame time.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode), an organic layer, and a second electrode (eg, a cathode electrode).

The driving transistor DRT drives the organic light emitting diode OLED by supplying a driving current to the organic light emitting diode OLED.

The first node N1 of the driving transistor DRT may be electrically connected to the first electrode of the organic light emitting diode OLED, and may be a source node or a drain node. The second node N2 of the driving transistor DRT may be electrically connected to a source node or a drain node of the switching transistor SWT, and may be a gate node. The third node N3 of the driving transistor DRT may be electrically connected to a driving voltage line (DVL) supplying the driving voltage EVDD, and may be a drain node or a source node.

In this specification, a wiring extended and formed in the display area of the display panel to supply the driving voltage EVDD to the driving transistor DRT is defined as a driving voltage line, and is abbreviated as an EVDD line or a Driving Voltage Line (DVL).

The driving transistor DRT and the switching transistor SWT may be implemented as an n-type or a p-type as illustrated in FIG. 2 .

The switching transistor SWT is electrically connected between the data line DL and the second node N2 of the driving transistor DRT, and is controlled by receiving the scan signal SCAN through the gate line GL as a gate node. can be

The switching transistor SWT is turned on by the scan signal SCAN to transfer the data voltage Vdata supplied from the data line DL to the second node N2 of the driving transistor DRT.

The storage capacitor Cstg may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

This storage capacitor Cstg is not a parasitic capacitor (eg, Cgs, Cgd) which is an internal capacitor that exists between the first node N1 and the second node N2 of the driving transistor DRT, It is an external capacitor intentionally designed outside the driving transistor (DRT).

Meanwhile, in the case of the organic light emitting diode display 100 according to the present exemplary embodiments, as the driving time of each sub-pixel SP increases, the circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT) are reduced. Degradation may proceed.

Accordingly, unique characteristic values (eg, threshold voltage, mobility, etc.) of circuit elements such as organic light emitting diodes (OLEDs) and driving transistors (DRTs) may change.

Meanwhile, each subpixel disposed in the organic light emitting display panel 110 according to the present exemplary embodiments includes, for example, an organic light emitting diode (OLED), a driving transistor (DRT), a switching transistor (SWT), and a storage capacitor (Cstg). In addition, it may further include a sensing transistor (SENT: Sensing Transistor) used for compensation according to the deterioration of the circuit element.

The sensing transistor SENT is electrically connected between the first node N1 of the driving transistor DRT and a reference voltage line RVL supplying a reference voltage Vref, and a gate node It may be controlled by receiving a sensing signal SENSE, which is a kind of raw scan signal.

The sensing transistor SENT is turned on by the sensing signal SENSE to apply the reference voltage Vref supplied through the reference voltage line RVL to the first node N1 of the driving transistor DRT.

Also, the sensing transistor SENT may be used as one of the voltage sensing paths for the first node N1 of the driving transistor DRT.

Meanwhile, the scan signal SCAN and the sensing signal SENSE may be separate gate signals. In this case, the scan signal SCAN and the sensing signal SENSE may be respectively applied to the gate node of the switching transistor SWT and the gate node of the sensing transistor SENT through other gate lines.

In some cases, the scan signal SCAN and the sensing signal SENSE may be the same gate signal. In this case, the scan signal SCAN and the sensing signal SENSE may be commonly applied to the gate node of the switching transistor SWT and the gate node of the sensing transistor SENT through the same gate line.

Meanwhile, as shown in FIG. 2 , the driving voltage line DVL 210 extends across the display panel in parallel to the data line DL, and each driving voltage line DVL is connected to the driving voltage link pattern 212 . is connected to the driving transistor (DRT) through

In this case, one driving voltage line 210 is disposed for each of the four sub-pixels of R, G, B, and W, and is electrically connected to non-adjacent sub-pixels through the driving voltage link pattern 212 .

In this structure, when an external force is applied to the display panel, the panel is damaged. At the same time, the data line DL and the voltage lines are internally disconnected, so that a voltage higher than the reference value is applied to the data line, and as a result, an overcurrent flows in the driving transistor DRT. .

More specifically, in FIG. 2 , a disconnection occurs in the region 220 where the data line DL and the driving voltage link pattern 212 intersect, and the driving voltage EVDD is applied to the data line DL. An overcurrent will flow in the driving transistor connected to the line.

At this time, the number of disconnected lines is determined according to the range of the external force, and the overcurrent flowing by rising is also proportionally increased. As a result, there is a risk of melting the polarizing film (POL) of the panel and causing the entire panel Pol Melting phenomenon.

In order to prevent damage to the panel element due to such overcurrent, an overcurrent detection circuit is added to the display panel in hardware to cut off the input of the power voltage when overcurrent is detected, or to sense the lines in software at blanking time. Therefore, when abnormal data is generated, an overcurrent prevention method of cutting off the power input has been proposed.

3 shows several examples of a structure for preventing overcurrent damage. FIG. 3 (a) is a hardware overcurrent protection structure, and FIG. 3(b) shows a software overcurrent protection structure.

First, the hardware structure considered as a method for preventing damage to the panel element due to overcurrent will be described as follows.

As shown in (a) of FIG. 3 , in the hardware overcurrent prevention structure, an overcurrent detection circuit (Over-Current Detection Circuit; 310) is additionally formed inside or outside the display panel 110, and the overcurrent detection circuit is used through the overcurrent detection circuit. A method of cutting off the power supply voltage is possible when is detected.

In this case, the overcurrent detection circuit 310 may be configured as a circuit for sensing the current flowing through the panel driving gate driving voltage (gate high/low voltage; VGH, VGL).

To describe this hardware overcurrent protection structure in more detail, first, the timing controller (T-con) 320 included in the source printed circuit board (S-PCB) transmits the gate driving voltage enable signal (VGH/VGL Enable) signal. The power controller (PMIC) 330 applies the gate driving voltage, that is, the gate high/low voltages VGH and VGL, to the display panel 110 .

In this process, the overcurrent detection circuit 310 detects the current flowing when the panel driving gate driving voltage (VGL, VGH) is applied, and when the current is an overcurrent exceeding a certain standard, burnt detection and protection (Burnt Detection and Protection) ; BDP) signal VGH/VGL_BDP is generated and transmitted to the timing controller 320 .

When the timing controller 320 receives an abnormal signal (VGH/VGL_BDP Signal), the timing controller 320 transmits a BDP signal to a power supply unit of a set device such as a TV to cut off power supplied to the set device.

Meanwhile, as a software method, as shown in FIG. 3B , it may be considered to include and use a constant overcurrent detection algorithm 342 in the source driver integrated circuit (S-DIC) 340 .

This overcurrent detection algorithm 342 detects the sensing data applied to the sensing line (or reference voltage line), etc. during the blanking time between the active time period in the normal display mode (Normal Display Mode), and is abnormal. When data is detected, a burnt detection and protection signal (BDP signal) is generated and transmitted to the timing controller 320 .

When receiving the BDP signal, the timing controller 320 transmits the BDP signal to the power supply unit of the set device, such as a TV, to cut off the power supplied to the set device.

However, the hardware overcurrent protection structure not only complicates the circuit configuration because an additional overcurrent protection circuit must be added, but also operates only when an overcurrent occurs in the gate driving voltage block. There is a problem that there is no

That is, there is a disadvantage in that it cannot cover all of the various types of overcurrent phenomena that may occur due to panel cracks.

In addition, in the software overcurrent prevention structure, the time interval required for the overcurrent detection operation is long because it is determined whether there is an overcurrent by the data sensed in the blanking time between the active time sections. have.

In addition, since the software method operates only in the normal display state in which an image is displayed on the display panel, states other than the normal display mode, more specifically, ON-RF after power-on ) or when an overcurrent is generated due to panel damage in the off sequence (Off-RS) after power off, there is a problem in that it cannot be dealt with.

In addition, in the above two methods, there is a problem that the entire power supply of the set device must be shut down when an overcurrent occurs.

Accordingly, in the embodiment of the present invention, two or more sub driving voltage common lines are formed on one side of the display panel, and a plurality of driving voltage lines (DVL or EVDD Lines) are connected to each sub driving voltage common line. We propose a method of preventing panel damage due to overcurrent by connecting and distributing the overcurrent generated when the panel cracks to a plurality of sub-driving voltage common lines having high resistance.

FIG. 4 is a diagram illustrating only some components of a general organic light emitting diode display to which the present invention can be applied.

In FIG. 4 , a connection film (Chip-On-Film; 430), the driving voltage line DVL 210, and the driving voltage common line EVDD Common Line 440 are shown.

As shown in FIG. 4 , a source printed circuit board (S-PCB) 420 is disposed on one side of the display panel 110 , and a connection film (Chip-On-Film) on which a source driver integrated circuit (S-DIC) 432 is mounted. 430 is connected to the display panel and the S-PCB 420 .

In addition, a plurality of driving voltage lines 210 are formed inside the display panel 110 in a direction parallel to the data line, and each driving voltage line 210 is connected to the S-DIC 432 of the connecting film (COF) 430 . ) is connected to a power controller (PMIC; not shown) in the S-PCB 420 .

Meanwhile, a driving voltage common line (EVDD Common Line) 440 electrically connected to all driving voltage lines 210 is formed in a portion of the non-display area on the other side of the display panel, that is, on the opposite side to which the S-PCB is connected.

The driving voltage common line 440 is formed in a direction parallel to the gate line in the lower non-display area of the display panel and is connected to all the driving voltage lines 210 to stably apply the driving voltage EVDD to the driving voltage line. At the same time, it is responsible for the authorization function.

In this structure, as described above, when an overcurrent of the driving transistor (DRT) is generated due to damage such as a crack of the display panel, the overcurrent is transmitted through one driving voltage common line 440 connected to an external power source in the region where the crack occurs. It flows along the data line.

Accordingly, it is difficult for the overcurrent generated by the panel crack or the like to escape from the panel, and thus the above-described Pol-melting phenomenon may still occur in a part of the panel.

5 is a plan view of an organic light emitting display device according to an exemplary embodiment of the present invention.

5 shows a connection film (Chip-On_Film; 530) on which a source printed circuit board (S-PCB; 520) and a source driver integrated circuit (S-DIC; 532) related to the present invention are mounted among the components of the organic light emitting display device. , a driving voltage line DVL 550 and a plurality of sub driving voltage common lines EVDD Common Lines 540, 540', 540” are shown.

As shown in FIG. 5 , the organic light emitting display panel 510 according to the embodiment of the present invention includes a display area 512 in which a plurality of subpixels including organic light emitting diodes are formed, and two or more driving areas formed outside the display area. and a non-display area 614 including voltage common lines 540 , 540 ′ and 540 ″.

In the display area 512 , a plurality of data lines DL extending in a first direction (vertical direction) of the display panel, a plurality of gate lines GL extending in a second direction (horizontal direction), and a gate It includes a plurality of sub-pixels SP defined as an intersection region of a line and a data line, and a plurality of driving voltage lines EVDD Line 550 disposed to apply a driving voltage EVDD to the sub-pixels.

The driving voltage line EVDD Line 550 extends throughout the display panel in a first direction (vertical direction) parallel to the data line DL, and a driving voltage extension line 550 formed on the connection film COF 530 . It is connected to a power controller (not shown) of the source PCB 520 through 552 .

In addition, in the non-display area 514 (NA) disposed outside the display area of the display panel 510, a line on glass (LOG) area in which various power lines and signal lines are formed is formed. In particular, in the LOG area, the source PCB ( In the non-display area opposite to the 520 , two or more sub-driving voltage common lines (ECLs; 540, 540', 540”) extending long in the second direction (horizontal direction) of the display panel are formed.

For convenience, it is described that three sub-driving voltage common lines (ECL) are formed in FIG. 5, but the present invention is not limited thereto. If the number of sub-driving voltage common lines (ECL) is two or more, All should be construed as being included in the scope of the present invention.

The sub EVDD common line (ECL; 540, 540', 540") may be formed of the same material and layer as the gate metal layer, but is not limited thereto.

Each of the sub driving voltage common lines (ECL) is electrically connected to one end of two or more driving voltage lines selected from among the plurality of driving voltage lines 550 .

Each of the sub driving voltage common lines (ECL) should be formed to be smaller than the width of a single driving voltage common line (EVDD Common Line) 440 as shown in FIG. 4 .

In general, since the LOG area formed in the non-display area has a certain limit in size, in order to form a plurality of Sub EVDD Common Lines (ECL), a single driving voltage common line (Sub EVDD Common Line) is required. Line; 440) has no choice but to be narrower than the line width.

When the line width of the sub driving voltage common line (ECL) is reduced, the electrical resistance of the sub driving voltage common line (ECL) increases. When the overcurrent flows along the driving voltage line, the concentration phenomenon of the overcurrent can be alleviated.

Also, in the present embodiment, it is preferable that the driving voltage lines connected to one sub driving voltage common line are not adjacent to each other but are spaced apart from each other.

More specifically, when the number of driving voltage lines is N and the number of sub driving voltage common lines is k (k≥2), the i-th driving voltage line (i=1,2, ..., N-1) and The (i+nk)-th driving voltage lines (n=1,2, ..., N/k-1) are connected to the same sub driving voltage common line.

6 is an enlarged view illustrating the connection relationship between the sub driving voltage common line and the driving voltage lines according to an embodiment of the present invention and effects thereof.

5 and 6 as an example, when the total number of driving voltage lines is 120 (N=120) and the number of sub-driving voltage common lines is 3 (k=3), the first driving voltage line EL#1 550) and the fourth driving voltage line EL#4; 550 are connected to the first driving voltage common lines ECL#1 and 540.

Similarly, the second driving voltage line EL#2; 550' and the fifth driving voltage line EL#5; 550' are connected to the second driving voltage common lines ECL#2 and 540', and the third driving voltage line ECL#2 and 540'. The driving voltage line EL#3; 550” and the sixth driving voltage line EL#6; 550” are connected to the third driving voltage common lines ECL#3 and 540”.

That is, according to the present embodiment, the electrical resistance component is increased by setting the line width of the sub EVDD common lines 540, 540', 540” to a predetermined size or less, and as described above, one sub driving voltage The driving voltage lines connected to the common line (Sub EVDD Common Line; ECL) are spaced apart as much as possible from each other.

According to this configuration, as shown in FIG. 6 , even if an overcurrent flows along the driving voltage line in the burnt region 570 generated in a certain portion of the display panel, a plurality of sub driving voltage common lines Sub having a resistance component greater than or equal to a certain level Since the overcurrent is evenly distributed along the EVDD Common Line (ECL), it is possible to prevent damage to the panel due to the distribution of the overcurrent. That is, when the burnt region 570 is generated due to a panel crack or the like, even if an overcurrent (I1+I2+I3) is introduced from the external driving voltage source EVDD Source, the resistance component is equal to or greater than a certain level along the common line of the plurality of sub driving voltages. By being dispersed and flowing into I1, I2, and I3, it is possible to suppress the panel fire caused by overcurrent.

7 shows a contrast configuration for contrast with an embodiment of the present invention.

In the structure of FIG. 7 , successive driving voltage lines 650 are connected to one driving voltage common line. In this case, all of the first to third overcurrents I1 to I3 generated in the burnt region 670 are one. Since the sub driving voltage flows along the common line ECL#1, the overcurrent dispersion effect of the present invention cannot be achieved.

On the other hand, as shown in FIG. 6, using the embodiment of the present invention, among the overcurrents generated in the burnt region 570, the first overcurrent I1 flows along the third sub driving voltage common line ECL#3, The second overcurrent I2 flows along the first sub driving voltage common line ECL#1, and the third overcurrent I3 flows along the second sub driving voltage common line ECL#3, so that the overcurrent is evenly distributed. it can be

Accordingly, even if overcurrent occurs due to damage to the panel in a certain area of the display panel, the overcurrent is evenly distributed across the plurality of sub driving voltage common lines and flows, thereby suppressing panel damage or POL melting due to overcurrent. .

In particular, the electrical resistance of each of the sub driving voltage common lines is increased as much as desired by adjusting the number and line width of the sub driving voltage common lines without changing the space occupied by the single driving voltage common line 440 as shown in FIG. 4 . Therefore, it is possible to prevent overcurrent and panel ignition (POL Melting) caused by panel cracks.

For convenience, only some components of the glass light emitting display device are illustrated in FIG. 5 , but the organic light emitting display device according to the present invention may include all of the various components described with reference to FIGS. 1 to 3 .

That is, the sub-pixels included in the organic light emitting diode display according to the present embodiment basically include an organic light emitting diode (OLED) and a driving transistor (DRT) for driving the organic light emitting diode (OLED). ), a switching transistor (SWT) for transferring a data voltage to the second node N2 corresponding to the gate node of the driving transistor DRT, and a data voltage corresponding to the image signal voltage or a voltage corresponding thereto It may be configured by including a storage capacitor (Cstg: Storage Capacitor) that holds the .

In addition, in some cases, in order to compensate for circuit element deterioration, between the first node N1 of the driving transistor DRT and a reference voltage line (RVL) supplying a reference voltage (Vref) It may further include a sensing transistor (SENT: Sensing Transistor) electrically connected to the gate node and controlled by receiving a sensing signal SENSE, which is a type of scan signal, as a gate node.

In addition, in the organic light emitting display device according to the embodiment of the present invention, in addition to the display panel 510 having the above-described structure, the display panel and the display panel are disposed on the opposite side of the non-display area where the sub driving voltage common lines 540 , 540 ′, 540 ″ are disposed. It may further include a connection film (COF; 530) connected to, and a source printed circuit board (S-PCB; 520) connected to the connection film.

The connection film 530 is an electrical component in the form of a chip-on film, in which a source driver integrated circuit (S-DIC) for applying image data to a data line is mounted therein, and includes a plurality of electrical wiring structures. In particular, a driving voltage extension line 552 electrically connected to the driving voltage line 550 is further formed on the connecting film 530 .

Such a connection film (COF; 530) is illustrated and described as a chip-on-film (Chip-On-Film) type circuit, but is not limited to such an expression, and a Chip-On-Flexible (COF) It may be replaced by other terms or expressions such as circuit, COF printed circuit, COFPC, flexible printed circuit (FPC), and TCP (Tape Carrier Package).

The connection film 530 is formed by forming a wiring or a circuit that can be electrically connected to other circuit wirings on a flexible insulating film that can be bent.

8 illustrates an overcurrent flow phenomenon in an organic light emitting diode display according to an embodiment of the present invention.

As described above, when the embodiment of the present invention is used, the overcurrent generated by cracks in the display panel is dispersed and flows to the sub driving voltage common line, thereby preventing panel damage.

However, when the line widths of the sub driving voltage common lines 540 , 540 ′ and 540 ″ are reduced to a certain level or more, the electrical resistance of the sub driving voltage common lines increases accordingly.

In this case, some of the overcurrent I4 flowing into the display panel flows into the data line inside the panel, but some of the current I5 may flow toward the connection film 530 .

In this case, the signal line of the connection film, which is relatively weak compared to the display panel, in particular, the driving voltage extension line 552 inside the connection film 530 is disconnected, and only the connection film may be damaged.

As described above, by adjusting the number and line width of the sub driving voltage common lines to increase the electrical resistance of each sub driving voltage common line to a certain range or more, and disposing the connection film 530 on the opposite side of the sub driving voltage common line, Even if overcurrent occurs due to panel cracks, only the connection film is damaged or ignited, and as a result, it is possible to prevent POL melting of the entire display panel.

By using the embodiment of the present invention as described above, without a separate overcurrent prevention circuit or algorithm, the panel crack can be caused not only in the normal display operation but also at the time of driving the power-off sequence and the power-on sequence. By dispersing and limiting the flow of the overcurrent, it is possible to suppress the panel ignition (POL-melting) phenomenon caused by the overcurrent.

In addition, by adjusting the number and line width of the sub driving voltage common lines to increase the electrical resistance of each sub driving voltage common line to a certain range or more, and arranging the connection film on the opposite side of the sub driving voltage common line, Even if overcurrent occurs, only the connecting film is damaged or ignited, and as a result, there is an effect of preventing the entire display panel from burning (POL melting).

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine configurations within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

510: display panel 520: source printed circuit board (S-PCB)
530: connection film (COF) 532: source driver integrated circuit (S-DIC)
550: driving voltage line (EVDD Line; EL)
540, 540', 540": Sub drive voltage common line (ECL)

Claims (7)

Data lines, gate lines, a plurality of subpixels defined by an intersection region of the gate line and the data line, and a plurality of driving voltage lines EVDD disposed to apply a driving voltage EVDD to the subpixels Line) including a display area;
a non-display area disposed perpendicular to the driving voltage line outside the display area and including two or more sub driving voltage common lines electrically connected to one end of at least two driving voltage lines selected from among the plurality of driving voltage lines; includes,
The two or more sub driving voltage common lines apply the driving voltage to the driving voltage line,
the sub driving voltage common line includes a first sub driving voltage common line and a second sub driving voltage common line extending in the same direction as the first sub driving voltage common line;
At least one driving voltage line electrically connected to the second sub driving voltage common line is positioned between the two driving voltage lines electrically connected to the first sub driving voltage common line. According to claim 1,
The driving voltage lines connected to the one sub driving voltage common line are not adjacent to each other but are spaced apart from each other. 3. The method of claim 2,
The plurality of driving voltage lines is N, and the number of the sub driving voltage common lines is k (k≥2), and the i-th driving voltage lines (i=1,2,..., N-1) and (i+nk) are The th driving voltage lines (n=1,2, ..., N/k-1) are connected to the same sub driving voltage common line. Data lines, gate lines, a plurality of subpixels defined by an intersection region of the gate line and the data line, and a plurality of driving voltage lines EVDD disposed to apply a driving voltage EVDD to the subpixels Line) including a display area; a non-display area disposed perpendicular to the driving voltage line outside the display area and including two or more sub driving voltage common lines electrically connected to one end of at least two driving voltage lines selected from among the plurality of driving voltage lines; A display panel comprising:
A connection film connected to the display panel on the opposite side of the non-display area in which the sub driving voltage common line is disposed and having a source driver integrated circuit (S-DIC) mounted therein;
A source printed circuit board (S-PCB) connected to the connection film:
includes,
The two or more sub driving voltage common lines apply the driving voltage to the driving voltage line,
the sub driving voltage common line includes a first sub driving voltage common line and a second sub driving voltage common line extending in the same direction as the first sub driving voltage common line;
At least one driving voltage line electrically connected to the second sub driving voltage common line is positioned between the two driving voltage lines electrically connected to the first sub driving voltage common line. 5. The method of claim 4,
and the connecting film includes a driving voltage extension line electrically connected to the driving voltage line. 6. The method of claim 5,
The driving voltage lines connected to the one sub driving voltage common line are not adjacent to each other but are spaced apart from each other. 7. The method of claim 6,
The plurality of driving voltage lines is N, and the number of the sub driving voltage common lines is k (k≥2), and the i-th driving voltage lines (i=1,2,..., N-1) and (i+nk) are The second driving voltage lines (n=1,2, ..., N/k-1) are connected to the same sub driving voltage common line.

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