KR102587494B1 - Display device - Google Patents

Abstract

A display device according to the present invention includes a display panel including a plurality of pixels connected to a plurality of scan lines and a data line; A gate driving circuit for driving the scan line; a data driving circuit for driving a data line; A timing controller for transmitting image data received from the host through a differential signal line to a data driving circuit and generating a control signal for controlling the gate driving circuit and the data driving circuit from the signal of the differential signal line; and a power management unit for generating a plurality of driving voltages required to drive the display panel, gate driving circuit, data driving circuit, and timing controller using input power supplied from the host, wherein the power management unit levels the voltage of the differential signal line. Alternatively, a power-off sequence may be started that turns off a plurality of driving voltages based on the voltage level of a backlight control signal supplied from the host.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly, to a method of controlling the power-off sequence of a display device and a display device to which the same is applied.

As the information society progresses, the demand for display devices for displaying images is becoming more diverse, and in recent years, large-scale displays such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs: Organic Light Emitting Diodes) have become more diverse. Flat panel display devices are widely used.

A flat panel display device is composed of several components such as a display panel, data driving circuit, gate driving circuit, timing controller, and power management unit. The power management unit uses input power to generate various operating voltages required for the operation of these components. supply.

The power management unit sequentially generates several operating voltages based on the input power according to the designated power on sequence when the power is turned on, but the input power is turned off in the power off sequence. Because several operating voltages are turned off, the power-off sequence required by the data driving circuit or gate driving circuit is not satisfied.

If the power-off sequence required by the data driving circuit or gate driving circuit is not satisfied when the power is turned off, potential reversal may occur, resulting in leakage current and damage to the circuit, as well as data stored in the pixels that make up the screen. If the voltage is not sufficiently discharged, the image displayed before turning off the power may appear as an afterimage.

The present invention takes this situation into consideration, and the purpose of the present invention is to provide a method of controlling the power-off sequence so that the circuit is not damaged or an afterimage is left during the power-off process.

Another object of the present invention is to provide a method for quickly and accurately detecting the power-off timing so as to perform the power-off sequence in a timely manner.

A display device according to an embodiment of the present invention includes a display panel including a plurality of pixels connected to a plurality of scan lines and a data line; A gate driving circuit for driving the scan line; a data driving circuit for driving a data line; A timing controller for transmitting image data received from the host through a differential signal line to a data driving circuit and generating a control signal for controlling the gate driving circuit and the data driving circuit from the signal of the differential signal line; and a power management unit for generating a plurality of driving voltages required to drive the display panel, gate driving circuit, data driving circuit, and timing controller using input power supplied from the host, wherein the power management unit levels the voltage of the differential signal line. Alternatively, a power-off sequence may be started to turn off a plurality of driving voltages based on the voltage level of a backlight control signal supplied from the host.

In one embodiment, the power management unit may perform a power-off sequence starting when the voltage level of the differential signal line becomes lower than the first reference voltage or when the voltage level of the backlight control signal becomes lower than the second reference voltage.

In one embodiment, the display device further includes a logic circuit consisting of a comparator where one of the differential signal lines is connected to an inverting terminal and a first reference voltage is connected to a non-inverting terminal, and the power management unit is configured to connect the differential signal line to the non-inverting terminal. When the voltage level becomes lower than the first reference voltage, the power-off sequence can be started according to the power-off control signal output by the comparator.

In one embodiment, the display device includes a first comparator in which a first line of the differential signal lines is connected to an inverting terminal and a first reference voltage is connected to a non-inverting terminal, and a second line of the differential signal lines is connected to an inverting terminal. 1 The reference voltage further includes a logic circuit including a second comparator connected to the non-inverting terminal and an AND gate that takes the output of the first comparator and the second comparator as input, and the power management unit is configured to connect the first line and the second line. When the voltage level becomes lower than the first reference voltage, the power-off sequence can be started according to the power-off control signal output from the AND gate.

In one embodiment, the logic circuitry may be embedded in a timing controller or in a power management unit.

In one embodiment, the display device further includes a logic circuit comprised of a comparator in which a signal line supplying a backlight control signal is connected to an inverting terminal and a second reference voltage is connected to a non-inverting terminal, and the power management unit provides a backlight control signal. When the voltage level of becomes lower than the second reference voltage, the power-off sequence can be started according to the power-off control signal output by the comparator.

In one embodiment, when performing a power-off sequence, the power management unit may turn off a plurality of driving voltages according to the power sequence required by the data driving circuit and the gate driving circuit.

In one embodiment, the power management unit may turn off the common voltage, low-potential power voltage, gate high voltage, gate low voltage, and high-potential power voltage in the following order.

In one embodiment, the power management unit may turn off the gate high voltage after a predetermined time has elapsed after the voltage level of the differential signal line becomes lower than the first reference voltage or after the voltage level of the backlight control signal becomes lower than the second reference voltage. there is.

A method of driving a display device according to another embodiment of the present invention includes comparing the voltage level of one or more differential signal lines that receive image data and control data from a host with a reference voltage; and starting a power-off sequence that turns off a plurality of driving voltages necessary for driving the display device when the voltage level becomes lower than the reference voltage.

By quickly detecting the power-off point and performing the power-off sequence in time, the reliability and durability of the display device are improved by preventing damage to the driving circuit due to voltage reversal during the power-off process, and the screen is displayed during the power-off process. Display quality can be improved by preventing afterimages from being displayed.

1 shows an ideal power on/off sequence for a source drive IC;
Figure 2 shows an ideal power on/off sequence for a gate drive IC;
Figure 3 shows the power sequence of an actual power management unit that sequentially generates various voltages during the power-on sequence and simultaneously stops output of all voltages during the power-off sequence;
Figure 4 is a graph showing changes in various voltages during the actual power on/off sequence,
Figures 5a and 5b show situations in which leakage current occurs in the electrostatic protection circuit and the electrostatic protection circuit during the power-off sequence;
Figure 6 shows a situation in which the discharge signal is not properly applied to the panel during the power-off sequence.
Figure 7 illustrates controlling the power-off sequence using a differential signal transmitted from the host according to an embodiment of the present invention;
Figure 8 shows a display device according to the present invention as a block,
9 shows a logic circuit for generating a power-off control signal from a differential signal according to an embodiment of the present invention;
Figures 10A and 10B illustrate controlling the power-off sequence using a backlight enable signal transmitted from the host according to another embodiment of the present invention;
Figure 11 is a graph showing changes in various voltages during the power on/off sequence according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Figure 1 shows an ideal power on/off sequence of a source drive IC, and Figure 2 shows an ideal power on/off sequence of a gate drive IC.

The data driving circuit may be composed of a plurality of source drive ICs, to which a high-potential power supply voltage and a low-potential power supply voltage (VDD and VSS or PVDD and NVDD) are applied to generate data voltage and set gamma compensation voltage. .

The ideal power management unit first generates a high-potential supply voltage (VDD) based on the input power (Vin) supplied in the power-on sequence, and then generates a low-potential supply voltage (VSS) according to the requirements of the source drive IC. And, in the power-off sequence, the output or generation of the low-potential supply voltage (VSS) must be turned off and then the output of the high-potential supply voltage (VDD) must be turned off.

The gate driving circuit includes a plurality of gate drive ICs in the non-display areas on both sides of the display panel. The gate drive IC includes a gate high voltage (VGH) indicating the high logic and low logic levels of the scan signal or emission signal, and a gate voltage (VGH) that indicates the high logic and low logic levels of the scan signal or emission signal. Low voltage (VGL) is applied.

The ideal power management unit first generates the gate low voltage (VGL) and then the gate high voltage (VGH) based on the input power (Vin) supplied in the power-on sequence, according to the requirements of the gate drive IC. , in the power-off sequence, the output or generation of the gate high voltage (VGH) must be turned off, followed by the output of the gate low voltage (VGL).

Figure 3 shows the power sequence of the actual power management unit, which sequentially generates various voltages during the power-on sequence and simultaneously stops outputting all voltages during the power-off sequence, and Figure 4 shows the changes in various voltages during the actual power-on/off sequence. This is a graph showing.

In the power-on sequence, when the input power (Vin) is applied and exceeds a predetermined level, the actual power management unit controls the high-potential power supply voltage (PVDD), gate low voltage (VGL), gate high voltage (VGH), and low-potential power supply voltage. Voltages are generated and output in the order of (NVDD) and common voltage (VCOM).

However, in the power-off sequence, the common voltage (VCOM), low-potential power supply voltage (NVDD), gate high voltage (VGH), gate low voltage (VGL), and high-potential power supply voltage (PVDD) are not turned off sequentially, but are input It is turned off at the same time when the voltage (Vin) falls below a predetermined level, for example, Under Voltage Lock Out (UVLO).

That is, as shown in FIG. 4, once the voltage of the input power supply (Vin) drops below a predetermined level, the output levels of the high potential power supply voltage (PVDD) and the gate high voltage (VGH) also drop immediately, so that the source drive IC and gate drive IC The power-off sequence conditions required by are not satisfied.

In the case of some drive ICs, if the operating voltages are turned off at the same time, the potential between the operating voltages is reversed, resulting in leakage current, which may damage the circuit.

FIGS. 5A and 5B illustrate a situation in which leakage current occurs in the static electricity protection circuit and the static electricity protection circuit during a power-off sequence.

As shown in FIG. 5A, a diode is placed in the reverse direction between the first voltage source (NVDD) and the second voltage source (VGL) with a relatively lower potential level to electrostatically discharge the circuit connected to the first voltage source (NVDD). can be protected from Normally, when the first voltage source (NVDD) has a higher potential level than the second voltage source (VGL), no current flows through the diode and no leakage current (I_leak) occurs. However, in an abnormal case where the first voltage source (NVDD) has a lower potential level than the second voltage source (VGL), leakage current (I_leak) flows through the diode and is applied to the circuit, which may cause damage to the circuit.

In the power-on sequence, the power management unit that receives the input power sequentially generates and outputs the voltage necessary for the operation of the driving drive. As shown in FIGS. 3 and 5B, for example, the gate low voltage of -14V ( VGL) is first generated, and then a low-potential power supply voltage (NVDD) of -7V, which has a higher potential level, is generated, and a voltage is applied in the reverse direction to the diode in the static electricity protection circuit of Figure 5a, causing the diode to be turned off and leakage current to occur. I never do that.

However, in the power-off sequence, if the power management unit arbitrarily turns off the generation/output of the operating voltage and the gate low voltage (VGL) changes to the ground level before the low-potential power supply voltage (NVDD), the gate low voltage (VGL) changes to ground level before the low-potential power supply voltage (NVDD). ) may occur during a period in which the potential level is higher than the low-potential power supply voltage (NVDD), and at this time, a forward voltage is applied to the diode in the static electricity protection circuit of Figure 5a, causing the diode to turn on, generating leakage current and flowing into the circuit. It may damage the circuit.

Figure 6 shows a situation in which a discharge signal is not properly applied to the panel during the power-off sequence.

In the power-off sequence, when the voltage of the input power supply (Vin) falls below a predetermined level, the gate all-high signal (ALL_H) changes to low level, and accordingly, the discharge unit included in the gate driving circuit operates with the gate high voltage (VGH). Thus, a discharge voltage (Discharging), that is, a gate signal at the gate high voltage (VGH) level is output to all gate lines of the panel to discharge the pixels of the panel.

However, when the voltage of the input power supply (Vin) falls below a predetermined level, the gate high voltage (VGH) also decreases, and the discharge voltage (Discharging) applied to the gate line is also discharged like the gate high voltage (VGH). (as shown in the dotted box in Figure 6), the panel is not properly discharged.

As shown in Figures 5 and 6, problems that occur in the power-off sequence occur because the power management unit does not know in advance when the input voltage is turned off, that is, when the input voltage falls below a predetermined level.

The present invention recognizes in advance when the input voltage is turned off by using a signal input from the host system to the display panel, for example, a low voltage differential signal (LVDS), which is an interface for high-speed data transmission, By adjusting the turn-off order and turn-off time interval of various driving voltages from the point of recognition, the power-off sequence can be controlled to meet the specifications required by the source drive IC and gate drive IC.

Figure 7 illustrates controlling the power-off sequence using a differential signal transmitted from the host according to an embodiment of the present invention.

As can be seen in Figure 4, the host that delivers the input power (Vin) to the panel turns off the output of the differential signal (LVDS) for data transmission before turning off the input power (Vin), and the voltage of the LVDS line operates. becomes lower than the voltage.

The host transmits data signals and control signals to be displayed on the pixel to the timing controller (T-CON) through the low-voltage differential signal (LVDS) interface, and the timing controller (T-CON) adjusts the level of the differential signal to a predetermined reference voltage and When the voltage falls below the reference voltage, a power-off control signal (POS) is generated and transmitted to the power management unit (PMU).

The power management unit (PMU) that receives the power-off signal sequentially turns off the driving voltage in the reverse order of the power-on sequence until the input power (Vin) is turned off.

Figure 8 shows a display device according to the present invention as a block.

The display device according to the present invention may include a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a power management unit 16.

In the display panel 10, a plurality of data lines 14 arranged in a column direction and a plurality of scan lines or gate lines 15 arranged in a row direction intersect, and pixels ( PXL) are arranged in a matrix form to form a pixel array. A scan signal for controlling data voltage application is supplied to the scan lines 15.

In the pixel array, a pixel (PXL) arranged on the same horizontal line is connected to one of the data lines 14 and one of the scan lines 15 to form a pixel line. The pixel is electrically connected to the data line 14 in response to a scan signal input through the scan line 14 and receives a data voltage. Pixels arranged on the same pixel line operate simultaneously according to scan signals applied from the same scan line 15.

The display panel 10 displays an image in response to the scan signal supplied from the gate driving circuit 12 and the data signal supplied from the data driving circuit 12, and pixels (PXL) included in the display panel 10 emits its own light or controls external light.

One pixel includes a switching transistor connected to the scan line 15 and the data line 14, and a pixel circuit that operates in response to a data signal supplied through the switching transistor. Depending on the configuration of the pixel circuit, the display panel may be configured as a liquid crystal display panel if it includes a liquid crystal element, and may be configured as an organic light emitting display panel if it includes an organic light emitting device.

If the display panel 10 is configured as a liquid crystal display panel, the display panel 10 may be configured to operate in Twisted Nematic (TN) mode, Vertical Alignment (VA) mode, In Plane Switching (IPS) mode, Fringe Field Switching (FFS) mode, or Electrically Controlled Birefringence (ECB) mode. ) mode, etc. When the display panel 10 is composed of an organic light emitting display panel, it may be implemented as a top-emission method, a bottom-emission method, or a dual-emission method.

The timing controller 11 supplies image data (RGB) transmitted from an external host system (not shown) through a differential signal interface such as LVDS to the data driving circuit 12 through a communication interface such as EPI.

In addition, the timing controller 11 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK) from the host system through LVDS. It receives input and generates control signals to control the operation timing of the data driving circuit 12 and the gate driving circuit 13. The control signals include a gate timing control signal (GCS) for controlling the operation timing of the gate driving circuit 13 and a data timing control signal (DCS) for controlling the operation timing of the data driving circuit 12.

The timing controller 11 compares the level of one or more signal lines of a low-power differential signal (LVDS), which is a signal interface connected to the host system, with a predetermined reference voltage, and applies the level to the power management unit 16 as soon as it becomes lower than the reference voltage. It is determined that the input power is turned off, and a power-off control signal (POS) is generated and supplied to the power management unit 16.

The data driving circuit 12 samples and latches the digital video data (RGB) input from the timing controller 11 under the control of the timing controller 11, converts it into parallel data, and converts it to an analog data voltage according to the gamma reference voltage. It is converted to and output to the data lines 14 through the output channel. The data driving circuit 12 may be composed of a plurality of source drive ICs.

The gate driving circuit 13 generates scan signals in a row-sequential manner while shifting the level of the gate driving voltage based on the gate control signal (GDC) and sequentially provides the scan signals to the scan lines 15 connected to each pixel line.

The gate driving circuit 13 may be composed of a plurality of gate drive integrated circuits, each including a shift register, a level shifter, and an output buffer for converting the output signal of the shift register into a swing width suitable for driving the TFT of the pixel. there is. Additionally, the gate driving circuit 13 may be formed directly on the lower substrate of the display panel 10 using a Gate Drive IC in Panel (GIP) method. In the case of the GIP method, the level shifter may be mounted on a printed circuit board (PCB), and the shift register may be formed on the lower substrate of the display panel 10.

The power management unit 16 uses the input power (Vin) delivered from the host system to generate various driving voltages necessary for the operation of the display device to operate the display panel 10, timing controller 11, and data driving circuit 12. , can be separately supplied to the gate driving circuit 13. The driving voltage includes a first power supply voltage or a high-potential power supply voltage (PVDD), a second power supply voltage or a low-potential power supply voltage (NVDD), a common voltage (VCOM), a gate high voltage (VGH), and a gate low voltage (VGL). It can be included.

When the input power 16 is above a predetermined level, the power management unit 16 determines that power is applied and sets the high potential power supply voltage (PVDD), gate low voltage (VGL), and gate high according to the power-on sequence. The driving voltage is generated in the following order: voltage (VGH), low-potential power supply voltage (NVDD), and common voltage (VCOM).

In addition, when the power management unit 16 receives the power-off control signal (POS) from the timing controller 11, the common voltage (VCOM) and the low-potential power supply voltage (NVDD) are generated in the reverse order of the power-on sequence according to the power-off sequence. , the output of the gate high voltage (VGH), gate low voltage (VGL), and high potential power supply voltage (PVDD) can be turned off.

Since there is a certain time interval between when the power-off control signal (POS) is applied and the input power (Vin) is actually turned off, that is, falls below a predetermined voltage level, the power management unit 16 controls the power supply between the time intervals. Off sequence can be performed.

Figure 9 shows a logic circuit for generating a power-off control signal from a differential signal according to an embodiment of the present invention.

LVDS, a low-power roadway signal interface, is a data transmission standard that enables high-speed data transmission. Two different voltages are transmitted from a transmitter, and encoded information can be obtained from the voltage difference between the two lines received by the receiver. The average operating voltage of the two lines of LVDS is about 1.25V.

Serial communication that is more resistant to noise than the existing single-ended signal method, has easier signal termination than the pECL (pseudo-emitter coupled logic) signal method, and allows ultra-high-speed transmission and reception of Gbps or more. (Serial Communication) method.

The LVDS method has the advantage of reducing electromagnetic interference and reducing power consumption because it uses low voltage. Due to these advantages, the LVDS method is applied to various fields such as data transmission between chips as well as data transmission between boards.

Since the voltage of the LVDS line is about 1.25V, if the voltage of the LVDS line is lower than a predetermined reference voltage, for example, 0.5V, it can be determined that data transmission through the LVDS interface has stopped.

Among the LVDS data line pairs, at least one of the (+) line and the (-) line can be compared with the reference voltage, and if it is higher than the reference voltage, it can be determined that the LVDS interface is operating. Otherwise, it can be determined that the LVDS interface has stopped operating. .

In Figure 9, the power-off control signal generation circuit may be composed of two comparators and one AND gate, where the (+) line of the LVDS is connected to the inverting terminal (-) of the first comparator and the (+) line of the LVDS is connected to the non-inverting terminal (+). Connect the reference voltage (Vref), connect the (-) line of LVDS to the inverting terminal (-) of the second comparator, and connect the reference voltage (Vref) to the non-inverting terminal (+), and connect the first comparator and the second comparator. A power-off control signal (POS) can be generated by AND logic processing the output of the comparator.

The power-off control signal generation circuit may generate a power-off control signal (POS) only with the output of the first comparator or only with the output of the second comparator.

In FIGS. 7 and 8, the power-off control signal generation circuit of FIG. 9 is shown to be included in the timing controller (T-CON, 11), but the present invention is not limited to this, and the power management unit 16 receives the LVDS signal and By embedding the circuit of FIG. 9, a power-off control signal (POS) can be generated on its own to perform a power-off sequence.

FIGS. 10A and 10B illustrate controlling a power-off sequence using a backlight enable signal transmitted from the host according to another embodiment of the present invention, and FIG. 11 shows various control functions during the power on/off sequence according to the present invention. This is a graph showing the change in voltage.

The backlight control unit (BLU-CON) of the host of the liquid crystal display device supplies the backlight control signal (EN) and operating voltage (Vin2), which control the operation of the backlight unit (BLU), to the backlight unit (BLU). ) implements local dimming, global dimming, etc. according to the backlight control signal (EN).

When turning off the system, the host turns off the backlight control signal (EN) output from the backlight control unit (BLU-CON) before turning off the output of the input voltage (Vin).

The power management unit 16 (PMU) compares the backlight control signal EN transmitted from the host with a predetermined reference voltage, determines that it is a power-off process when it becomes lower than the reference voltage, and performs a power-off sequence.

As shown in Figure 10b, a signal line supplying the backlight control signal (EN) is connected to the inverting terminal (-) of the comparator, a reference voltage (Vref) is connected to the non-inverting terminal (+), and the backlight control signal (EN) When the level falls below the reference voltage (Vref), the output of the comparator can generate a power-off control signal (POS) that will trigger the power-off sequence. The reference voltage in FIG. 10B may be the same as or different from the reference voltage in FIG. 9.

The power management unit 16 (PMU) may perform the power-off sequence as shown in FIG. 11 from the time the power-off control signal (POS) is generated until the input power (Vin) falls below a predetermined level.

The system turns on the backlight control signal (EN) while supplying power (Vin). During the power-off process, the backlight control signal (EN) can be used as the gate all-high signal (ALL_H) to control the discharge of the panel 10. there is.

When the input power (Vin) is above a predetermined level, the power management unit 16 controls the high-potential power supply voltage (PVDD), gate low voltage (VGL), gate high voltage (VGH), and low-potential power supply voltage (PVDD) according to the power-on sequence. Generate and output voltages in the order of NVDD) and common voltage (VCOM).

When the gate low voltage (VGH) is generated, it is applied to the discharge part of the gate driving circuit 13 as a discharge voltage (Discharging).

Meanwhile, when the system receives a power-off command from the user, it turns off the LVDS signal or turns off the backlight control signal (EN) before turning off the power supplied to the panel.

When the backlight control signal (EN) is turned off, the gate all-high signal (ALL_H) is also turned off, and the gate high voltage (VGH) is applied to the discharge portion of the gate driving circuit 13 in synchronization with the turn-off of the gate all-high signal (ALL_H). It is supplied as a discharge voltage (Discharging).

The power management unit 16 generates a power-off control signal (POS) according to the off-level backlight control signal (EN) and performs a power-off sequence based on this.

When performing a power-off sequence, the power management unit 16 controls the common voltage (VCOM), low-potential power supply voltage (NVDD), gate high voltage (VGH), gate low voltage (VGL), and high-potential power supply voltage (PVDD). are turned off sequentially, but in order to sufficiently discharge the panel 10, the gate high voltage (VGH) may be turned off a predetermined time or more after the power-off control signal (POS) is generated. It is advantageous for the power-off sequence to turn off several voltages after generating the power-off control signal (POS) until the input voltage (Vin) is turned off.

In this way, by detecting the power-off time in advance and performing a power-off sequence before power-off based on the differential signal applied from the host, the panel's discharge characteristics can be improved and the power supply can be adjusted to the specifications required by the drive IC. By performing an off sequence, the durability and reliability of the drive IC can be improved.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
14: data line 15: scan line
16: Power management unit

Claims (10)

A display panel including a plurality of pixels connected to a plurality of scan lines and a data line;
a gate driving circuit for driving the scan line;
a data driving circuit for driving the data line;
a timing controller for transmitting image data received from a host to the data driving circuit through a differential signal line and generating a control signal for controlling the gate driving circuit and the data driving circuit from signals of the differential signal line; and
A power management unit configured to sequentially generate a plurality of driving voltages required to drive the display panel, the gate driving circuit, the data driving circuit, and the timing controller using input power supplied from the host,
The power management unit turns off the plurality of driving voltages in an order opposite to the order in which the plurality of driving voltages were sequentially generated based on the voltage level of the differential signal line or the voltage level of the backlight control signal supplied from the host. An indication device characterized in that it starts an off sequence. According to claim 1,
The power management unit performs the power-off sequence from when the voltage level of the differential signal line becomes lower than the first reference voltage or when the voltage level of the backlight control signal becomes lower than the second reference voltage. Device. According to clause 2,
Further comprising a logic circuit consisting of a comparator wherein one of the differential signal lines is connected to an inverting terminal and the first reference voltage is connected to a non-inverting terminal,
The power management unit starts the power-off sequence according to a power-off control signal output from the comparator when the voltage level of the differential signal line becomes lower than the first reference voltage. According to clause 2,
A first comparator in which a first line of the differential signal lines is connected to an inverting terminal and the first reference voltage is connected to a non-inverting terminal, and a second line of the differential signal lines is connected to an inverting terminal and the first reference voltage is It further includes a logic circuit including a second comparator connected to a non-inverting terminal and an AND gate that receives outputs of the first comparator and the second comparator as input,
The power management unit starts the power-off sequence according to a power-off control signal output from the AND gate when the voltage level of the first line and the second line becomes lower than the first reference voltage. . According to claim 3 or 4,
The display device, wherein the logic circuit is built into the timing controller or the power management unit. According to clause 2,
It further comprises a logic circuit consisting of a comparator in which a signal line supplying the backlight control signal is connected to an inverting terminal and the second reference voltage is connected to a non-inverting terminal,
The power management unit starts the power-off sequence according to the power-off control signal output by the comparator when the voltage level of the backlight control signal becomes lower than the second reference voltage. According to claim 1,
When performing the power-off sequence, the power management unit turns off the plurality of driving voltages in a reverse order of the order in which the driving voltages of the data driving circuit and the gate driving circuit are generated. According to clause 7,
The power management unit turns off a common voltage, a low-potential power supply voltage, a gate high voltage, a gate low voltage, and a high-potential power supply voltage in that order. According to clause 8,
The power management unit turns off the gate high voltage after a predetermined time has elapsed after the voltage level of the differential signal line becomes lower than the first reference voltage or after the voltage level of the backlight control signal becomes lower than the second reference voltage. Characterized display device. Comparing the voltage level of one or more of the differential signal lines that receive video data and control data from the host with a reference voltage; and
When the voltage level becomes lower than the reference voltage, starting a power-off sequence to turn off a plurality of driving voltages required to drive the display device,
The step of starting the power-off sequence is,
A method of driving a display device by turning off the plurality of driving voltages in an order opposite to the order in which the plurality of driving voltages were sequentially generated.

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