KR20160048911A - 멀티-칩 패키지 상의 혼성 메모리를 위한 단일화된 메모리 제어기 - Google Patents

멀티-칩 패키지 상의 혼성 메모리를 위한 단일화된 메모리 제어기 Download PDF

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Publication number
KR20160048911A
KR20160048911A KR1020167008120A KR20167008120A KR20160048911A KR 20160048911 A KR20160048911 A KR 20160048911A KR 1020167008120 A KR1020167008120 A KR 1020167008120A KR 20167008120 A KR20167008120 A KR 20167008120A KR 20160048911 A KR20160048911 A KR 20160048911A
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KR
South Korea
Prior art keywords
memory
interface
chip package
host
umc
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Withdrawn
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KR1020167008120A
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English (en)
Korean (ko)
Inventor
현석 신
정필 김
덱스터 타미오 춘
정원 수
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퀄컴 인코포레이티드
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Publication of KR20160048911A publication Critical patent/KR20160048911A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
KR1020167008120A 2013-09-03 2014-07-09 멀티-칩 패키지 상의 혼성 메모리를 위한 단일화된 메모리 제어기 Withdrawn KR20160048911A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/016,717 2013-09-03
US14/016,717 US10185515B2 (en) 2013-09-03 2013-09-03 Unified memory controller for heterogeneous memory on a multi-chip package
PCT/US2014/045983 WO2015034580A1 (en) 2013-09-03 2014-07-09 Unified memory controller for heterogeneous memory on a multi-chip package

Publications (1)

Publication Number Publication Date
KR20160048911A true KR20160048911A (ko) 2016-05-04

Family

ID=51293140

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167008120A Withdrawn KR20160048911A (ko) 2013-09-03 2014-07-09 멀티-칩 패키지 상의 혼성 메모리를 위한 단일화된 메모리 제어기

Country Status (6)

Country Link
US (1) US10185515B2 (enExample)
EP (1) EP3042295A1 (enExample)
JP (1) JP2016532974A (enExample)
KR (1) KR20160048911A (enExample)
CN (1) CN105493061B (enExample)
WO (1) WO2015034580A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102408613B1 (ko) 2015-08-27 2022-06-15 삼성전자주식회사 메모리 모듈의 동작 방법, 및 메모리 모듈을 제어하는 프로세서의 동작 방법, 및 사용자 시스템
US10268541B2 (en) 2016-08-15 2019-04-23 Samsung Electronics Co., Ltd. DRAM assist error correction mechanism for DDR SDRAM interface
KR102482896B1 (ko) 2017-12-28 2022-12-30 삼성전자주식회사 이종 휘발성 메모리 칩들을 포함하는 메모리 장치 및 이를 포함하는 전자 장치
US20210233585A1 (en) * 2020-01-29 2021-07-29 Micron Technology, Inc. Multichip memory package with internal channel
US12475068B2 (en) * 2022-09-15 2025-11-18 Micron Technology, Inc. Multi-interface memory

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100383774B1 (ko) 2000-01-26 2003-05-12 삼성전자주식회사 공통 인터페이스 방식의 메모리 장치들을 구비한 시스템
JP4049297B2 (ja) 2001-06-11 2008-02-20 株式会社ルネサステクノロジ 半導体記憶装置
JP4059002B2 (ja) 2001-06-13 2008-03-12 株式会社日立製作所 メモリ装置
KR101085406B1 (ko) 2004-02-16 2011-11-21 삼성전자주식회사 불 휘발성 메모리를 제어하기 위한 컨트롤러
EP1849162A4 (en) 2005-01-25 2009-02-11 Northern Lights Semiconductor SINGLE CHIP WITH A MAGNETORESISTIVE MEMORY
JP4693843B2 (ja) 2005-06-09 2011-06-01 パナソニック株式会社 メモリ制御装置及びメモリ制御方法
US20060294295A1 (en) 2005-06-24 2006-12-28 Yukio Fukuzo DRAM chip device well-communicated with flash memory chip and multi-chip package comprising such a device
US8291295B2 (en) 2005-09-26 2012-10-16 Sandisk Il Ltd. NAND flash memory controller exporting a NAND interface
US7519754B2 (en) 2005-12-28 2009-04-14 Silicon Storage Technology, Inc. Hard disk drive cache memory and playback device
US20070147115A1 (en) 2005-12-28 2007-06-28 Fong-Long Lin Unified memory and controller
US7716411B2 (en) 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
EP2122473B1 (en) 2007-01-10 2012-12-05 Mobile Semiconductor Corporation Adaptive memory system for enhancing the performance of an external computing device
US8700830B2 (en) * 2007-11-20 2014-04-15 Spansion Llc Memory buffering system that improves read/write performance and provides low latency for mobile systems
CN101303885A (zh) 2008-07-01 2008-11-12 普天信息技术研究院有限公司 多芯片封装存储模块
US7778101B2 (en) 2008-09-05 2010-08-17 Genesys Logic, Inc. Memory module and method of performing the same
JP2011070470A (ja) 2009-09-28 2011-04-07 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
US20150067234A1 (en) 2015-03-05
CN105493061A (zh) 2016-04-13
CN105493061B (zh) 2020-11-03
US10185515B2 (en) 2019-01-22
WO2015034580A1 (en) 2015-03-12
EP3042295A1 (en) 2016-07-13
JP2016532974A (ja) 2016-10-20

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PA0105 International application

Patent event date: 20160328

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid