KR20160015022A - Light emitting device and lighting system - Google Patents

Abstract

The embodiment of the present invention relates to a light emitting device, a manufacturing method of the light emitting device, a light emitting device package, and a lighting system. According to an embodiment, the light emitting device may comprise: a first-conductivity-type semiconductor layer having a recess including an inclined portion and a planar bottom portion; an active layer arranged on the inclined portion of the recess; and a second-conductivity-type semiconductor layer arranged on the active layer.

Description

[0001] LIGHT EMITTING DEVICE AND LIGHTING SYSTEM [0002]

Embodiments relate to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system.

A light emitting device can be produced by combining p-n junction diodes having the characteristic that electric energy is converted into light energy by elements of Group III and Group V on the periodic table. LEDs can be implemented in various colors by controlling the composition ratio of compound semiconductors.

When a forward voltage is applied to a light emitting device, the electrons in the n-layer and the holes in the p-layer are coupled to emit energy corresponding to the energy gap between the conduction band and the valance band. It emits mainly in the form of heat or light, and emits in the form of light.

For example, nitride semiconductors have received great interest in the development of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. Particularly, blue light emitting devices, green light emitting devices, ultraviolet (UV) light emitting devices, and the like using nitride semiconductors have been commercialized and widely used.

In recent years, there has been a demand for a light emitting device having a high luminous efficiency in accordance with the demand for a high output light emitting device.

Embodiments provide a light emitting device capable of achieving high light emitting efficiency, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system.

Also, embodiments are directed to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system capable of improving reliability and light efficiency.

The light emitting device according to the embodiment includes a first conductive semiconductor layer 112 having a recess A including an inclined portion A1 and a lower planar portion A2; An active layer 114 disposed on the inclined portion A1 of the recess; And a second conductive semiconductor layer 116 disposed on the active layer 114.

An illumination system according to an embodiment may include a light emitting module having the light emitting element.

Embodiments can provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system capable of maximizing a region of a light emitting active layer and achieving high light emitting efficiency.

Also, the embodiment can provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and a lighting system capable of achieving a high light emitting efficiency by securing a high quality active layer region.

In addition, in the embodiment, current diffusion can be performed between the active layers, thereby improving the reliability and the light efficiency.

1 is a sectional view of a light emitting device according to a first embodiment;
2 is a cross-sectional view of a light emitting device according to a second embodiment;
3A to 7 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment.
8 is a sectional view of a light emitting device package according to an embodiment.
9 is a perspective view of a lighting apparatus according to an embodiment.

In the description of the embodiments, each layer (film), region, pattern or structure is referred to as being "on" or "under" the substrate, each layer (film) Quot; on "and" under "are intended to include both" directly "or" indirectly " do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

(Example)

1 is a cross-sectional view of a light emitting device 100 according to a first embodiment.

The light emitting device 100 according to the embodiment includes the first conductivity type semiconductor layer 112 having the recess A (see FIG. 3A) including the inclined portion A1 and the lower plane portion A2, An active layer 114 disposed on the inclined portion A1 of the scep and a second conductive semiconductor layer 116 disposed on the active layer 114. [

The exemplary embodiment may include a first electrode 115 electrically connected to the first conductive semiconductor layer 112 and a second electrode layer 140 electrically connected to the second conductive semiconductor layer 116 have. The second electrode layer 140 may include an ohmic layer 142 and a reflective layer 144, but the present invention is not limited thereto.

1, the light extracting pattern 119 may be provided on the surface of the first conductivity type semiconductor layer 112 to improve external light extraction efficiency.

1 is an explanatory view of a vertical light emitting device, but the present invention is not limited thereto. The present invention is also applicable to the horizontal light emitting device 102 as shown in FIG.

The light emitting device according to the second embodiment employs the technical features of the first embodiment and may include an internal light extracting pattern P, for example, PSS, on the substrate 105, A light-transmitting ohmic layer 146 and a second electrode 148 may be provided on the first electrode 116.

Hereinafter, technical features of the light emitting device according to the embodiment will be described with reference to FIGS. 1 and 3A to 5.

The embodiment includes a recess A disposed in the first conductive type semiconductor layer 112 and the recess A may include an inclined portion A1 and a lower planar portion A2.

The embodiment may include a first insulating layer 130a disposed on the lower plane portion A2 of the recess.

In an embodiment, the length of any one of the slopes A1 may be greater than the length of any one of the first insulating layers 130a. For example, in the embodiment, the minimum length of the inclined portion A1 may be greater than the maximum length of the first insulating layer 130a.

Accordingly, according to the embodiment, the length of any one of the active layers 114 disposed in the sloped portion A1 may be greater than the length of any one of the first insulating layers 130a. For example, the minimum length of the active layer 114 disposed in the inclined portion A1 may be greater than a maximum length of the first insulating layer 130a.

Accordingly, the area of the active layer is increased as compared with the active layer of the conventional light emitting device arranged horizontally, so that the overall luminous efficiency can be remarkably increased.

The first conductive semiconductor layer 112 may include an upper planar portion B disposed between the plurality of recesses A, and may include a plurality of recesses A, can do.

The light emitting device according to the embodiment may include a second insulating layer 130b disposed on the upper plane portion B.

In an embodiment, the length of any one of the slopes A1 may be greater than the length of any one of the second insulating layers 130b. For example, in the embodiment, the minimum length of the inclined portion A1 may be greater than the maximum length of the second insulating layer 130b.

Accordingly, according to the embodiment, the length of any one of the active layers 114 disposed in the sloped portion A1 may be greater than the length of any one of the second insulating layers 130b. For example, the minimum length of the active layer 114 disposed in the inclined portion A1 may be greater than the maximum length of the second insulating layer 130b.

Thus, according to the embodiment, the area of the active layer is increased as compared with the active layer of the conventional light emitting device, and the overall luminous efficiency can be remarkably increased.

In an embodiment, the active layer 114 may not be disposed on the lower planar portion A2 of the recess A. In addition, the upper plane portion B of the recess A and the active layer 114 may not overlap with each other.

In an embodiment, the active layer 114 may be disposed at an inclined portion A1 of the recess, and the inclined portion A1 of the recess may be a {11-20} plane. Accordingly, the inclined portion A1 of the recess may be a semi-polar surface.

In the light emitting device according to the embodiment, since the active layer 114 grown on the semi-polar plane has a small difference in lattice constant, it is less influenced by the piezoelectric and spontaneous electric fields, and the quality of the thin film can be increased.

Thus, according to the embodiment, by maximizing the quality of the active layer compared to the conventional one, the chip Po and the efficiency droop of the light emitting device chip can be remarkably improved.

In addition, according to the embodiment, the length of any one of the slopes A1 is greater than the sum of the length of any one of the first insulating layers 130a and the length of any one of the second insulating layers 130b . For example, the minimum length of the inclined portion A1 may be greater than the sum of the maximum length of the first insulating layer 130a and the maximum length of the second insulating layer 130b.

Thus, according to the embodiment, the length of one of the active layers 114 disposed in the sloped portion A1 is set to be equal to the length of any one of the first insulating layers 130a and the second insulating layer 130b May be greater than the combined length of one length.

For example, according to an embodiment, the minimum length of the active layer 114 disposed in the sloped portion A1 is a length of the maximum length of the first insulating layer 130a and the maximum length of the second insulating layer 130b .

Thus, according to the embodiment, it is possible to maximize the area of the active layer of high quality and significantly improve the luminous intensity Po of the light emitting device chip.

The first insulating layer 130a and the second insulating layer 130b may be referred to as an insulating layer 130. The insulating layer 130 may be a light-transmitting insulating layer.

For example, the first insulating layer 130a or the second insulating layer 130b may be formed of a light-transmitting insulating layer such as an oxide, thereby enhancing the external extraction efficiency of light emitted.

The first insulating layer 130a or the second insulating layer 130b that isolates the first conductivity type semiconductor layer 112 from the second conductivity type semiconductor layer 116 may function as a current diffusion layer The reliability of the chip can be improved and the light intensity can be improved by current diffusion.

Hereinafter, a method of manufacturing the light emitting device according to the embodiment will be described with reference to FIGS. 3A to 7, and the technical features of the embodiments will be described in detail.

First, the substrate 105 is prepared as shown in FIG. 3A. The substrate 105 may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate. For example, the substrate 105 may include at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ . A concavo-convex structure may be formed on the substrate 105, but the present invention is not limited thereto.

A buffer layer (not shown) may be formed on the substrate 105. The buffer layer may mitigate the lattice mismatch between the material of the light emitting structure 110 to be formed and the substrate 105. The material of the buffer layer may be a group III-V compound semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN.

Next, a first conductive semiconductor layer 112 may be formed on the first substrate 105.

The first conductive semiconductor layer 112 may be formed of a semiconductor compound. Group 3-Group 5, Group 2-Group 6, and the like, and the first conductive type dopant may be doped. When the first conductive semiconductor layer 112 is an n-type semiconductor layer, the first conductive dopant may include Si, Ge, Sn, Se, and Te as an n-type dopant.

The first conductive semiconductor layer 112 includes a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) .

The first conductive semiconductor layer 112 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP and InP.

Embodiments can form a recess A including the inclined portion A1 and the lower planar portion A2 in the first conductivity type semiconductor layer 112 after the first conductive type semiconductor layer 112 is formed.

For example, after forming the first conductive semiconductor layer 112, the recesses A may be formed by texturing by dry etching to form the recesses A as shown in FIG. 3A.

In an embodiment, the recesses A may be provided in plurality and the first conductive semiconductor layer 112 may include an upper flat portion B disposed between the plurality of recesses A have.

Next, as shown in FIG. 3B, a first insulating layer 130a may be formed on the lower plane portion A2 of the recess, and a second insulating layer 130b may be formed on the upper plane portion B.

The first insulating layer 130a and the second insulating layer 130b may be referred to as an insulating layer 130. The insulating layer 130 may be a light-transmitting insulating layer.

For example, the first insulating layer (130a) or the second insulating layer (130b) is to increase external extraction efficiency of the light emitted by being formed of a light-transmitting insulating layer of nitride, such as oxide, SiN, etc., such as SiO ₂ have.

The first insulating layer 130a or the second insulating layer 130b that isolates the first conductivity type semiconductor layer 112 from the second conductivity type semiconductor layer 116 may function as a current diffusion layer The reliability of the chip can be improved and the light intensity can be improved by current diffusion.

In an embodiment, the length of any one of the slopes A1 may be greater than the length of any one of the first insulating layers 130a. For example, in the embodiment, the minimum length of the inclined portion A1 may be greater than the maximum length of the first insulating layer 130a.

In addition, in the embodiment, the length of any one of the slopes A1 may be greater than the length of any one of the second insulating layers 130b. For example, in the embodiment, the minimum length of the inclined portion A1 may be greater than the maximum length of the second insulating layer 130b.

Next, as shown in FIG. 4, the active layer 114 may be formed on the inclined portion A1.

The active layer 114 may emit light from the UV-A region to the blue region and the green region.

The active layer 114 may be formed of at least one of a single quantum well structure, a multi quantum well (MQW) structure, a quantum-wire structure, or a quantum dot structure.

For example, the active layer 114 may be formed with a multiple quantum well structure by injecting trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) But is not limited thereto.

The active layer 114 may include a quantum well and a quantum wall. For example, the active layer 114 may be formed of one or more pairs of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs) / AlGaAs, GaP But is not limited thereto.

In an embodiment, the active layer 114 may be disposed at an inclined portion A1 of the recess, and the inclined portion A1 of the recess may be a {11-20} plane. Accordingly, the inclined portion A1 of the recess may be a semi-polar surface.

In an embodiment, the active layer 114 may not be disposed on the lower planar portion A2 of the recess A. In addition, the upper plane portion B of the recess A and the active layer 114 may not overlap with each other.

In the light emitting device according to the embodiment, since the active layer 114 grown on the semi-polar plane has a small difference in lattice constant, it is less influenced by the piezoelectric and spontaneous electric fields, and the quality of the thin film can be increased.

Thus, according to the embodiment, by maximizing the quality of the active layer compared to the conventional one, the chip Po and the efficiency droop of the light emitting device chip can be remarkably improved.

According to the embodiment, the length of one of the active layers 114 disposed in the sloped portion A1 may be greater than the length of any one of the first insulating layers 130a. For example, the minimum length of the active layer 114 disposed in the inclined portion A1 may be greater than a maximum length of the first insulating layer 130a.

Accordingly, the area of the active layer is increased as compared with the active layer of the conventional light emitting device arranged horizontally, so that the overall luminous efficiency can be remarkably increased.

In addition, according to the embodiment, the length of any one of the active layers 114 disposed in the sloped portion A1 may be greater than the length of any one of the second insulating layers 130b. For example, the minimum length of the active layer 114 disposed in the inclined portion A1 may be greater than the maximum length of the second insulating layer 130b.

Thus, according to the embodiment, the area of the active layer is increased as compared with the active layer of the conventional light emitting device, and the overall luminous efficiency can be remarkably increased.

In addition, according to the embodiment, the length of any one of the slopes A1 is greater than the sum of the length of any one of the first insulating layers 130a and the length of any one of the second insulating layers 130b . For example, the minimum length of the inclined portion A1 may be greater than the sum of the maximum length of the first insulating layer 130a and the maximum length of the second insulating layer 130b.

Thus, according to the embodiment, the length of one of the active layers 114 disposed in the sloped portion A1 is set to be equal to the length of any one of the first insulating layers 130a and the second insulating layer 130b May be greater than the combined length of one length.

For example, according to an embodiment, the minimum length of the active layer 114 disposed in the sloped portion A1 is a length of the maximum length of the first insulating layer 130a and the maximum length of the second insulating layer 130b .

Thus, according to the embodiment, it is possible to maximize the area of the active layer of high quality and significantly improve the luminous intensity Po of the light emitting device chip.

According to the embodiment, the active layer 114 may be formed after forming a super lattice layer (not shown) on the sloped portion A1 to improve disconnection and quality of the crystal. The superlattice layer may be an Al _x Ga _(1-x) N (0 _{? X?} 1) / GaN super lattice structure, but is not limited thereto.

Thereafter, an electron blocking layer (not shown) is formed on the active layer 114 to serve as electron blocking and cladding of the active layer, thereby improving the luminous efficiency. For example, the electron blocking layer may be formed of an Al _x In _y Ga _(1-xy) N (0? _{X ? 1, 0? Y ? 1} ) semiconductor, Lt; RTI ID = 0.0 > bandgap < / RTI >

Next, as shown in FIG. 5, the second conductive semiconductor layer 116 may be formed of a semiconductor compound. 3-group-5, group-2-group-6, and the like, and the second conductivity type dopant may be doped.

For example, the second conductivity type semiconductor layer 116 may be a semiconductor having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + ≪ / RTI > When the second conductive semiconductor layer 116 is a p-type semiconductor layer, the second conductive dopant may include Mg, Zn, Ca, Sr, and Ba as p-type dopants.

In an embodiment, the first conductive semiconductor layer 112 may be an n-type semiconductor layer, and the second conductive semiconductor layer 116 may be a p-type semiconductor layer.

Also, on the second conductive semiconductor layer 116, a semiconductor (e.g., an n-type semiconductor) (not shown) having a polarity opposite to that of the second conductive type may be formed. Accordingly, the light emitting structure 110 may have any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

Next, as shown in FIG. 6, a second electrode layer 140 may be formed on the second conductive semiconductor layer 116. The second electrode layer 140 may include an ohmic layer 142 and a reflective layer 144, but the present invention is not limited thereto.

The ohmic layer 142 may be formed by laminating a single metal, a metal alloy, a metal oxide, or the like so as to efficiently perform carrier injection. For example, the ohmic layer 142 may be formed of a superior material that is in electrical contact with a semiconductor. For example, the ohmic layer 142 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (ZnO), indium gallium tin oxide (AZO), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZON nitride, AGZO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Ni, IrOx / Au, and Ni / IrOx / , Au, and Hf, and is not limited to such a material.

The reflective layer 144 may be formed of a material having excellent reflectivity and excellent electrical contact. For example, it may be formed of a metal or an alloy containing at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf. The reflection layer 144 may be formed of a multilayer structure using a metal or an alloy and a light-transmitting conductive material such as IZO, IZTO, IAZO, IGZO, IGTO, AZO, or ATO. For example, IZO / Ni, AZO / Ag, IZO / Ag / Ni, AZO / Ag / Ni, or the like.

The second electrode layer 140 may include a supporting substrate (not shown). The support substrate may be made of a metal, a metal alloy, or a conductive semiconductor material having excellent electrical conductivity so that the carrier can be efficiently injected. For example, the support substrate may be made of a material selected from the group consisting of copper (Cu), gold (Au), copper alloy, nickel-nickel, Ge, GaAs, ZnO, SiGe, SiC, etc.).

The supporting substrate may be formed by an electrochemical metal deposition method, a bonding method using a yttetic metal, or the like.

Next, the substrate 105 may be removed from the light emitting structure 110 as shown in FIG. For example, the substrate 105 may be removed by using a high-power laser to separate the substrate or use a chemical etching method. In addition, the substrate 105 may be removed by physically grinding.

For example, in the laser lift-off method, energy is absorbed at the interface between the substrate 105 and the light emitting structure when a predetermined energy is applied at room temperature, and the bonding surface of the light emitting structure is thermally decomposed to separate the substrate 105 from the light emitting structure can do.

In this case, when the second electrode layer 140 does not have a supporting substrate, the thickness of the second electrode layer 140 may be sufficient to support the light emitting structure 110 when the substrate 105 is removed .

Next, a portion of the exposed surface of the first conductive semiconductor layer 112 may be partially removed to form an external light extracting pattern 119, and the first electrode 115 may be formed. The external light extraction pattern 119 may be a regular pattern or an irregular pattern, but is not limited thereto.

Embodiments can provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and an illumination system capable of maximizing a region of a light emitting active layer and achieving high light emitting efficiency.

Also, the embodiment can provide a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and a lighting system capable of achieving a high light emitting efficiency by securing a high quality active layer region.

In addition, in the embodiment, current diffusion can be performed between the active layers, thereby improving the reliability and the light efficiency.

8 is a view illustrating a light emitting device package having the light emitting device according to the embodiments.

The light emitting device package according to the embodiment includes a package body 205, a third electrode layer 213 and a fourth electrode layer 214 provided on the package body 205, A light emitting device 100 electrically connected to the third electrode layer 213 and the fourth electrode layer 214 and a molding member 230 surrounding the light emitting device 100 are included.

The third electrode layer 213 and the fourth electrode layer 214 are electrically isolated from each other and provide power to the light emitting device 100. The third electrode layer 213 and the fourth electrode layer 214 may function to increase light efficiency by reflecting the light generated from the light emitting device 100, And may serve to discharge heat to the outside.

The light emitting device 100 may be electrically connected to the third electrode layer 213 and / or the fourth electrode layer 214 by a wire, flip chip, or die bonding method.

9 is an exploded perspective view of an illumination system according to an embodiment.

The lighting apparatus according to the embodiment may include a cover 2100, a light source module 2200, a heat discharger 2400, a power supply unit 2600, an inner case 2700, and a socket 2800. Further, the illumination device according to the embodiment may further include at least one of the member 2300 and the holder 2500. The light source module 2200 may include a light emitting device or a light emitting device package according to the embodiment.

The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250. The member 2300 is disposed on the upper surface of the heat discharging body 2400 and has guide grooves 2310 through which the plurality of light source portions 2210 and the connector 2250 are inserted.

The holder 2500 blocks the receiving groove 2719 of the insulating portion 2710 of the inner case 2700. Therefore, the power supply unit 2600 housed in the insulating portion 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510.

The power supply unit 2600 may include a protrusion 2610, a guide 2630, a base 2650, and an extension 2670. The inner case 2700 may include a molding part together with the power supply part 2600. The molding part is a hardened portion of the molding liquid so that the power supply unit 2600 can be fixed inside the inner case 2700.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects and the like illustrated in the embodiments can be combined and modified by other persons skilled in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

The inclined portion A1, the lower plane portion A2, the recesses A,
The first conductive semiconductor layer 112, the active layer 114,
The second conductive type semiconductor layer 116, the first insulating layer 130a,
The upper plane portion B, the second insulating layer 130b,

Claims (16)

A first conductive semiconductor layer having a recess including an inclined lower plane portion;
An active layer disposed at an inclined portion of the recess; And
And a second conductive semiconductor layer disposed on the active layer. The method according to claim 1,
And a first insulating layer disposed on a lower plane portion of the recess. 3. The method of claim 2,
The length of any one of the slopes
Wherein the length of one of the first insulating layers is larger than the length of any one of the first insulating layers. 3. The method of claim 2,
The plurality of recesses are provided,
The first conductivity type semiconductor layer
And a top plane portion disposed between the plurality of recesses. 5. The method of claim 4,
And a second insulating layer disposed on the upper plane portion. 6. The method of claim 5,
The length of any one of the slopes
And the second insulating layer is larger than the length of any one of the second insulating layers. 6. The method of claim 5,
The length of any one of the slopes
Wherein a length of any one of the first insulating layers and a length of any one of the second insulating layers is greater than a sum of lengths of any one of the first insulating layers and the second insulating layer. 6. The method of claim 5,
And the length of any one of the active layers disposed in the inclined portion is
Wherein the length of one of the first insulating layers is larger than the length of any one of the first insulating layers. 6. The method of claim 5,
And the length of any one of the active layers disposed in the inclined portion is
And the second insulating layer is larger than the length of any one of the second insulating layers. 6. The method of claim 5,
And the length of any one of the active layers disposed in the inclined portion is
Wherein a length of any one of the first insulating layers and a length of any one of the second insulating layers is greater than a sum of lengths of any one of the first insulating layers and the second insulating layer. 6. The method of claim 5,
And the active layer is not disposed on a lower plane portion of the recess. 6. The method of claim 5,
Wherein the upper plane portion of the recess and the active layer are not overlapped with each other. 13. The method according to any one of claims 1 to 12,
The inclined portion of the recess
{11-20} plane. 13. The method according to any one of claims 1 to 12,
The inclined portion of the recess
The light-emitting device is a semi-polar surface. 6. The method according to claim 2 or 5,
Wherein the first insulating layer or the second insulating layer is a light-transmitting insulating layer. A lighting system comprising a light emitting module comprising the light emitting element according to any one of claims 1 to 12.

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