KR102250512B1 - Light emitting device and lighting system - Google Patents

Abstract

The embodiment relates to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package and a lighting system.
The light emitting device according to the embodiment includes a first conductivity type semiconductor layer; An active layer on the first conductivity type semiconductor layer; A second conductivity type semiconductor layer on the active layer; A light-transmitting electrode layer having a first refractive index on the second conductivity-type semiconductor layer; And a light extraction pattern having a second refractive index greater than the first refractive index on the translucent electrode layer.

Description

Light emitting device and lighting system {LIGHT EMITTING DEVICE AND LIGHTING SYSTEM}

The embodiment relates to a light emitting device, a method of manufacturing a light emitting device, a light emitting device package, and a lighting system.

Light Emitting Device (LED) is a pn junction diode that converts electrical energy into light energy. It can be produced by combining elements of Group III and Group V on the periodic table. Color can be implemented.

When the forward voltage is applied, the electrons in the n-layer and the holes in the p-layer are combined to emit energy equivalent to the band gap energy of the conduction band and the balance band. , This energy is mainly emitted in the form of heat or light, and when it is radiated in the form of light, it becomes a light-emitting device.

For example, nitride semiconductors are attracting great interest in the development of optical devices and high-power electronic devices due to their high thermal stability and wide bandgap energy. In particular, a blue light emitting device, a green light emitting device, and an ultraviolet (UV) light emitting device using a nitride semiconductor have been commercialized and widely used.

According to the prior art, there is a problem in that light emitted from the active layer travels from the active layer to the outside of the light emitting device chip, and the ratio of light extracted to the outside of the chip is limited according to the difference in refractive index, and thus the luminous flux is lowered.

The embodiment is to provide a light emitting device capable of improving light flux by increasing light extraction efficiency, a method of manufacturing the same, a light emitting device package, and a lighting system.

The light emitting device according to the embodiment includes a first conductivity type semiconductor layer 112; An active layer 114 on the first conductivity type semiconductor layer 112; A second conductivity type semiconductor layer 116 on the active layer 114; A light-transmitting electrode layer 130 having a first refractive index on the second conductivity-type semiconductor layer 116; And a light extraction pattern 160 having a second refractive index smaller than the first refractive index on the translucent electrode layer 130.

In addition, the lighting system according to the embodiment may include a light emitting module including the light emitting device.

According to the light emitting device, the manufacturing method of the light emitting device, the light emitting device package, and the lighting system according to the embodiment, it is possible to improve the light flux by increasing the light extraction efficiency.

1 is a cross-sectional view of a light emitting device according to a first embodiment.
2 is a photograph of a first light extraction pattern of a light emitting device according to the first embodiment.
3A is a schematic diagram of a first light extraction pattern of a light emitting device according to the first embodiment.
3B is another exemplary view of a first light extraction pattern of a light emitting device according to the first embodiment.
3C is another exemplary view of a first light extraction pattern of a light emitting device according to the first embodiment.
4 is an exemplary diagram illustrating a light extraction threshold angle in a light emitting device according to the first embodiment.
5 is an exemplary diagram illustrating a light extraction threshold angle in the prior art.
6 and 7 are effect data of the light emitting device according to the embodiment.
8 to 10 are manufacturing process diagrams of the light emitting device according to the first embodiment.
11 is a cross-sectional view of a light emitting device according to a second embodiment.
12 is an exemplary view of a second light extraction lens pattern of a light emitting device according to the second embodiment.
13 is a plan view of a second light extraction lens pattern of a light emitting device according to the second embodiment.
14 is an exemplary view of a third light extraction lens pattern of a light emitting device according to the third embodiment.
15A to 15C are exemplary views of a fourth light extraction pattern of a light emitting device according to the fourth embodiment.
16 is a cross-sectional view of a light emitting device package according to an embodiment.
17 is an exploded perspective view of a lighting device according to the embodiment.

In the description of the embodiment, each layer (film), region, pattern, or structure is "on/over" or "under" of the substrate, each layer (film), region, pad, or patterns. In the case of being described as being formed in, "on/over" and "under" include both "directly" or "indirectly" formed. do. In addition, the criteria for the top/top or bottom of each layer will be described based on the drawings.

(Example)

1 is a cross-sectional view of a light emitting device 101 according to a first embodiment.

The light emitting device 101 according to the first embodiment includes a first conductivity type semiconductor layer 112, an active layer 114 on the first conductivity type semiconductor layer 112, and a second conductivity type semiconductor layer 114 on the active layer 114. A second refractive index smaller than the first refractive index on the conductive semiconductor layer 116 and the translucent electrode layer 130 having a first refractive index on the second conductive semiconductor layer 116 and the translucent electrode layer 130 It may include a first light extraction pattern 160 having.

2 is a photograph of the first light extraction pattern 160 of the light emitting device according to the first embodiment, and FIG. 3A is a schematic diagram of the first light extraction pattern 160 of the light emitting device according to the first embodiment, It will be described below with reference to FIG. 3A.

In the light emitting device according to the embodiment, the first light extraction pattern 160 includes a lower region 160b including a first inclined surface S1 and a second inclined surface S2 to be disposed on the lower region 160b. It may include an upper region 160a. In the first light extraction pattern 160, the lower region 160b may be a result of dry etching, and the upper region 160a may be a result of wet etching, but the present invention is not limited thereto.

For example, the first light extraction pattern 160 includes a lower region 160b including a first inclined surface S1 having a first angle θ1 with respect to a vertical line V on the translucent electrode layer 130 And an upper region 160a disposed on the lower region 160b with a second inclined surface S2 having a second angle θ2 with respect to the vertical line V.

The second angle θ2 may be greater than the first angle θ1. For example, the second angle θ2 may be 30° or more. The first angle θ1 may be about 10° or more.

The second angle θ2 and the first angle θ1 can be controlled according to a method of forming the first light extraction pattern 160, and the lower region 160b is a first angle θ1 by dry etching. May be provided, and the upper region 160a may have a second angle θ2 by wet etching.

For example, when the upper region 160a is performed by wet etching, an angle of about 30° or more to 45° may be provided by isotropic wet etching.

According to the embodiment, the second angle θ2 of the upper region 160a of the first light extraction pattern 160 is larger than the first angle θ1 of the lower region 160b, so that the boundary surface from which light is extracted is hemispherical. It is possible to increase the light extraction efficiency by minimizing the total reflection area by controlling close to

The lower region 160b of the first light extraction pattern 160 may include a polygonal column with a cut end or a cylindrical shape with a cut end.

The upper region 160a of the first light extraction pattern 160 may have a polygonal pyramid or cone shape.

According to the embodiment, the upper region 160a of the first light extraction pattern 160 may be the last path through which light emitted from the active layer escapes to the outside of the light emitting device chip, so that the pattern of the upper region 160a has a hemispherical shape and The light extraction efficiency can be improved by implementing a similar shape of a polygonal pyramid or cone shape.

The height b of the lower region 160b of the first light extraction pattern 160 may be greater than or equal to the height a of the upper region 160a. For example, the height b of the lower region 160b may be 1 to 10 times less than the height a of the upper region 160a.

In addition to controlling the angle of the lower region 160b and the upper region 160a, the shape of the first light extraction pattern 160 is controlled to be close to a hemispherical shape through height control, thereby increasing light extraction efficiency.

For example, when the total height of the first light extraction pattern 160 is about 10 μm, and the height b of the lower area 160b is about 5 μm, the height of the upper area 160a (a ) May be about 5 μm, but is not limited thereto.

On the other hand, when the total height of the first light extraction pattern 160 is about 11 μm, if the height b of the lower area 160b is about 1 μm, the height a of the upper area 160a is It may be about 10㎛ but is not limited thereto.

In an embodiment, the horizontal width c of the lowermost end of the lower region 160b of the first light extraction pattern 160 may be less than or equal to the total height of the first light extraction pattern 160.

For example, when the lowermost horizontal width (c) of the lower region 160b of the first light extraction pattern 160 is about 0.4 μm to 10 μm, the total height of the first light extraction pattern 160 is about 0.4 It may be ㎛ to 10㎛, but is not limited thereto.

3B is another exemplary view of a first light extraction pattern of a light emitting device according to the first embodiment.

According to the embodiment, as shown in FIG. 3B, since the upper region 160c of the first light extraction pattern is formed in a hemispherical shape, the total reflection region can be minimized to maximize the light extraction efficiency.

The upper region 160c of the first light extraction pattern as shown in FIG. 3B may form a hemispherical upper region 160c by forming the photoresist layer PR pattern itself in a wet etching process, but is not limited thereto.

3C is another exemplary view of a first light extraction pattern of a light emitting device according to the first embodiment.

According to the embodiment, as shown in FIG. 3C, the first light extraction pattern 160 has a lower region 160b, an intermediate region 160d, and an upper region 160a, and is formed to be close to a hemispherical shape to minimize the total reflection region. Light extraction efficiency can be maximized.

The intermediate region 160d may be formed through dry etching or wet etching, but is not limited thereto.

4 is an exemplary diagram illustrating a light extraction threshold angle in a light emitting device according to an exemplary embodiment, and FIG. 5 is an exemplary diagram illustrating a light extraction threshold angle in the prior art.

As shown in FIG. 5, according to the prior art, light emitted from the active layer proceeds from the active layer to the outside of the light emitting device chip, and the ratio of the light extracted to the outside of the chip is limited according to the difference in refractive index.

For example, in the case of light exiting from the active layer 14 to the air through the p-GaN 16 through the translucent electrode 130, the light between p-GaN having a refractive index of about 2.5 and a translucent electrode having a refractive index of about 2.0 The critical angle of the escape cone (area that is not totally reflected) that can be extracted is about 53°, and the critical angle of the escape cone at the interface where the light passing through the translucent electrode contacts air with a refractive index of 1 is limited to about 30°. The ratio of light that can be finally extracted to the outside is very limited.

On the other hand, according to the light emitting device according to the embodiment, in the case of light exiting from the active layer 114 to the air through the second conductive semiconductor layer 116, the translucent electrode layer 130, and the first light extraction pattern 160, The critical angle of total reflection is increased from about 30 ° to about 43 ° by the inclined surface of the first light extraction pattern 160 and the first light extraction pattern 160 having a refractive index between the refractive index of the electrode layer 130 and the air. By remarkably increasing, light extraction efficiency can be greatly improved by increasing the escape cone and by various inclined surfaces according to the shape of the first light extraction pattern.

The first light extraction pattern 160 may be an oxide, a nitride, or a fluorine compound, but is not limited thereto. For example, the first light extraction pattern 160 is SiO ₂ , It may be an oxide such as _{Al 2} O ₃ , a nitride such as _{SiN x , or a fluorine compound such as MgF 2} or CaF ₂ , but is not limited thereto. In addition, the first light extraction pattern 160 according to the embodiment may increase light extraction efficiency by minimizing light absorption or reflection in the light extraction pattern by employing a material having a low light absorption.

For example, the angle of incidence of the first light extraction pattern 160 is escape cone between cases containing SiO _2, the refractive index is about 2.0 and the light transmitting electrode layer 130 and a refractive index of about 1.46 SiO ₂ is about 43 ° It becomes very large, and the ratio of light escaped to the outside by various inclined surfaces of the first light extraction pattern 160 can be greatly improved.

6 and 7 are effect data of a light emitting device chip according to the embodiment.

6 is half to half wafer map data for Example (E) and Comparative Example (R). Compared to Comparative Example (R), in the case of Example (E), it can be seen that there are a number of regions in the wafer Wafer that exhibit a high luminous intensity (Po) of about 144mW (@ 95mA).

7 is a half to half wafer probe data (Probe data) for Example (E) and Comparative Example (R). Compared to Comparative Example (R), in the case of Example (E), it can be seen that there are a number of chips exhibiting a high luminous intensity (Po) of about 142mW (@ 95mA) or more.

Table 1 is a comparison table of chip data of Examples and Comparative Examples. VF3 @95mA WD @95mA Po @95mA Example 2.95 453.9 142.8 Comparative example 2.95 453.4 138.1

When the embodiment is applied, there is no significant difference in the characteristics of the operating voltage (VF3), and the luminous intensity (Po) is improved by about 3%.

Table 2 is a comparison table of package data of Examples and Comparative Examples. VF3 lm lm/W lm(%) Example 2.873 32.71 175.16 101.21 Comparative example 2.875 32.32 172.95 100.00

When the embodiment is applied, there is no significant difference in the characteristics of the operating voltage (VF3) and there is an effect that the luminous flux is improved by about 1%.

Hereinafter, a method of manufacturing a light emitting device according to an embodiment will be described with reference to FIGS. 8 to 10.

First, a substrate 102 is prepared as shown in FIG. 8. The substrate 102 may be formed of a material having excellent thermal conductivity, and may be a conductive substrate or an insulating substrate. For example, the substrate 102 may be formed of at least one _{of sapphire (Al 2} O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ 0 _3. An uneven structure P may be formed on the substrate 102, but the embodiment is not limited thereto. The substrate 102 may be wet cleaned to remove impurities from the surface.

A buffer layer (not shown) may be formed on the substrate 102. The buffer layer can alleviate lattice mismatch between the material of the light emitting structure 110 and the substrate 102, and the material of the buffer layer is a group 3-5 compound semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN , AlInN may be formed of at least one.

An undoped semiconductor layer (not shown) may be formed on the buffer layer, but the embodiment is not limited thereto.

Thereafter, a light emitting structure 110 including a first conductivity type semiconductor layer 112, an active layer 114, and a second conductivity type semiconductor layer 116 may be formed on the substrate 102 or the buffer layer.

The first conductivity type semiconductor layer 112 may be formed of a semiconductor compound. It may be implemented with a compound semiconductor such as Group 3-5 and Group 2-6, and may be doped with a first conductivity type dopant. When the first conductivity-type semiconductor layer 112 is an n-type semiconductor layer, the first conductivity-type dopant is an n-type dopant, and may include Si, Ge, Sn, Se, and Te, but is not limited thereto.

The first conductivity type semiconductor layer 112 may include _{a semiconductor material having a composition formula of In x} Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). I can.

The first conductivity type semiconductor layer 112 may be formed of one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP.

The first conductivity-type semiconductor layer 112 may form an N-type GaN layer using a method such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), sputtering, or hydroxide vapor phase epitaxy (HVPE). . In addition, the first conductivity-type semiconductor layer 112 is a silane containing n-type impurities such as _{trimethyl gallium gas (TMGa), ammonia gas (NH 3} ), nitrogen gas (N _{2 ), and silicon (Si) in the chamber.} It may be formed by injecting gas (SiH _{4 ).}

In an embodiment, a current diffusion layer (not shown) may be formed on the first conductivity type semiconductor layer 112. The current diffusion layer may be an undoped GaN layer, but is not limited thereto.

In addition, an electron injection layer (not shown) may be formed on the current diffusion layer. The electron injection layer may be a first conductivity type gallium nitride layer.

In addition, a strain control layer (not shown) may be formed on the electron injection layer. _{For example, a strain control layer formed of In y} Al _x Ga _(1-xy) N(0≤x≤1, 0≤y≤1)/GaN, etc. may be formed on the electron injection layer.

The strain control layer can effectively alleviate an odd stress due to lattice mismatch between the first conductivity type semiconductor layer 112 and the active layer 114.

Thereafter, an active layer 114 may be formed on the first conductivity type semiconductor layer 112 or the strain control layer.

In the active layer 114, electrons injected through the first conductivity-type semiconductor layer 112 and holes injected through the second conductivity-type semiconductor layer 116 formed thereafter meet each other to form an energy band specific to the active layer (light emitting layer) material. It is a layer that emits light with energy determined by.

The active layer 114 may be formed of at least one of a single quantum well structure, a multi quantum well (MQW) structure, a quantum-wire structure, or a quantum dot structure. For example, in the active layer 114, trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) may be injected to form a multiple quantum well structure. It is not limited thereto.

The active layer 114 may include a well layer/barrier layer structure. For example, the well layer/barrier layer structure may be formed in one or more pair structures among InGaN/GaN, InGaN/InGaN, GaN/AlGaN, InAlGaN/GaN, GaAs(InGaAs)/AlGaAs, GaP(InGaP)/AlGaP. However, it is not limited thereto. The well layer may be formed of a material having a band gap lower than that of the barrier layer.

In an embodiment, an electron blocking layer (not shown) is formed on the active layer 114 to serve as electron blocking and MQW cladding of the active layer, thereby improving luminous efficiency.

For example, the electron blocking layer may be formed of an Al _x In _y Ga _(1-xy) N (0≦x≦1,0≦y≦1) based semiconductor, and the energy band gap of the active layer 114 It may have a higher energy band gap, and may be formed to a thickness of about 100 Å to about 600 Å, but is not limited thereto.

In addition, the electron blocking layer may be formed of an Al _z Ga _(1-z) N/GaN (0≦z≦1) superlattice, but is not limited thereto. The electron blocking layer may be ion implanted in a p-type to effectively block overflowing electrons and increase hole injection efficiency.

Next, the second conductivity type semiconductor layer 116 may be implemented with a semiconductor compound, for example, a compound semiconductor such as group 3-5, group 2-6, etc., and may be doped with a second conductivity type dopant. have

For example, the second conductivity type semiconductor layer 116 is _{a semiconductor having a composition formula of In x} Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) It may contain substances. When the second conductivity-type semiconductor layer 116 is a p-type semiconductor layer, the second conductivity-type dopant is a p-type dopant and may include Mg, Zn, Ca, Sr, Ba, or the like.

The second conductivity-type semiconductor layer 116 is a vicetyl cyclo containing p-type impurities such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N _{2 ), and magnesium (Mg) in the chamber.} Pentadienyl magnesium (EtCp ₂ Mg) {Mg(C ₂ H ₅ C ₅ H ₄ ) ₂ } may be implanted to form a p-type GaN layer, but is not limited thereto.

In an embodiment, the first conductivity-type semiconductor layer 112 may be implemented as an n-type semiconductor layer, and the second conductivity-type semiconductor layer 116 may be implemented as a p-type semiconductor layer, but is not limited thereto. In addition, a semiconductor, for example, an n-type semiconductor layer (not shown) having a polarity opposite to that of the second conductivity type may be formed on the second conductivity type semiconductor layer 116. Accordingly, the light emitting structure 110 may be implemented in any one of an n-p junction structure, a p-n junction structure, an n-p-n junction structure, and a p-n-p junction structure.

Next, a portion of the second conductivity type semiconductor layer 116 and the active layer 114 may be partially removed so that a portion of the upper surface of the first conductivity type semiconductor layer 112 is exposed. A first electrode 151 may be formed on the exposed first conductivity type semiconductor layer 112 in a subsequent process.

Meanwhile, after the light-transmitting electrode layer 130 to be described later is formed, a process of exposing the first conductivity type semiconductor layer 112 may be performed.

Next, as shown in FIG. 9, a current blocking layer 120 may be formed at a location where the second electrode 152 is to be formed. The current blocking layer 120 may include a non-conductive region, a first conductivity type ion implantation layer, a first conductivity type diffusion layer, an insulating material, an amorphous region, and the like.

Next, the translucent electrode layer 130 may be formed on the second conductivity type semiconductor layer 116 on which the current blocking layer 120 is formed. After the light-transmitting electrode layer 130 is formed, as shown in FIG. 8, a process of exposing the first conductivity type semiconductor layer 112 may be performed.

The translucent electrode layer 130 may include an ohmic layer, and may be formed by stacking a single metal, a metal alloy, or a metal oxide in multiple layers so that hole injection can be efficiently performed.

For example, the light-transmitting electrode layer 130 may be formed of an excellent material that is in electrical contact with a semiconductor. For example, the light-transmitting electrode layer 130 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), and IGTO. (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), GZO (gallium zinc oxide), IZON (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx, RuOx, NiO, RuOx/ITO, Ni/IrOx/Au, and Ni/IrOx/Au/ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt , Au, and may be formed including at least one of Hf, but is not limited to these materials.

Thereafter, the passivation layer 140 may be formed as an insulating layer or the like on the side of the light emitting structure 110 and on a part of the light-transmitting electrode layer 130. The passivation layer 140 may expose a region where the first electrode 151 is to be formed.

Next, as shown in FIG. 10, a first light extraction pattern 160 may be formed on the translucent electrode layer 130.

For example, after forming a light extraction pattern layer (not shown) on the translucent electrode layer 130, the first light extraction pattern as shown in FIG. 2 or 3A, 3B, or 3C through wet etching and dry etching. 160 can be formed.

The lower region 160b of the first light extraction pattern 160 may be a result of dry etching, and the upper region 160a may be a result of wet etching, but is not limited thereto.

Meanwhile, it may be somewhat difficult to implement the first light extraction pattern 160 by either dry etching or wet etching. For example, when etching is performed only by dry etching, plasma damage may be applied to the surface of the last light-transmitting electrode layer 130.

On the other hand, when etching proceeds to the surface of the light-transmitting electrode layer 130 only by wet etching, there may be limitations in implementing the first light extraction pattern 160 in terms of uniformity and the phenomenon in which the photosensitive layer PR is blown away.

In the light emitting device according to the embodiment, the first light extraction pattern 160 includes a lower region 160b including a first inclined surface S1 and a second inclined surface S2 to be disposed on the lower region 160b. It may include an upper region 160a.

For example, the first light extraction pattern 160 includes a lower region 160b including a first inclined surface S1 having a first angle θ1 with respect to a vertical line V on the translucent electrode layer 130 And an upper region 160a disposed on the lower region 160b with a second inclined surface S2 having a second angle θ2 with respect to the vertical line V.

The second angle θ2 may be greater than the first angle θ1. For example, the second angle θ2 may be 30° or more. The first angle θ1 may be about 10° or more.

The second angle θ2 and the first angle θ1 can be controlled according to a method of forming the first light extraction pattern 160, and the lower region 160b is a first angle θ1 by dry etching. May be provided, and the upper region 160a may have a second angle θ2 by wet etching.

For example, when the upper region 160a is performed by wet etching, an angle of about 30° or more to 45° may be provided by isotropic wet etching.

The lower region 160b of the first light extraction pattern 160 may include a polygonal column with a cut end or a cylindrical shape with a cut end.

The upper region 160a of the first light extraction pattern 160 may have a polygonal pyramid or cone shape.

According to the embodiment, the upper region 160a of the first light extraction pattern 160 may be the last path through which light emitted from the active layer escapes to the outside of the light emitting device chip, so that the pattern of the upper region 160a has a hemispherical shape and The light extraction efficiency can be improved by implementing a similar shape of a polygonal pyramid or cone shape.

The height b of the lower region 160b of the first light extraction pattern 160 may be greater than or equal to the height a of the upper region 160a. For example, the height b of the lower region 160b may be 1 to 10 times less than the height a of the upper region 160a.

In an embodiment, the horizontal width c of the lowermost end of the lower region 160b of the first light extraction pattern 160 may be less than or equal to the total height of the first light extraction pattern 160.

Next, a first electrode 151 is formed on the exposed first conductivity type semiconductor layer 112 and a second electrode 152 is formed on the translucent electrode layer 130 in an area overlapping the current blocking layer 120. Can be.

11 is a cross-sectional view of the light emitting device 102 according to the second embodiment.

The second embodiment can adopt the technical features of the first embodiment.

12 is an exemplary view of the second light extraction pattern 170 of the light emitting device according to the second embodiment, and FIG. 13 is a perspective view of the second light extraction pattern 170 of the light emitting device according to the second embodiment.

In the second embodiment, the second light extraction pattern 170 is formed on the first light extraction lens pattern 171 on the translucent electrode layer 130 and the second light extraction pattern on the first light extraction lens pattern 171. It may include a light extraction lens pattern 172.

At least two of the plurality of first light extraction lens patterns 171 may be spaced apart from each other by a first distance D1.

On the other hand, the plurality of second light extraction lens patterns 172 may contact each other.

According to the second embodiment, the gap between the second light extraction lens patterns 172 on the first light extraction lens pattern 171 is formed to be at a level of almost zero, so that the light-transmitting electrode layer 130 is exposed to air. Can be minimized.

Accordingly, when the light emitted from the active layer 114 is directed upward, it is extracted from the translucent electrode layer 130 through the second light extraction pattern 170, thereby significantly reducing the amount of total reflected light, thereby significantly increasing the light extraction efficiency. I can.

In addition, according to the second embodiment, since the outer shape of the second light extraction pattern 170 is formed in a continuous embossed dome shape, it has a similar focal length in almost all directions, so that almost no total reflection occurs, thus remarkably increasing the light extraction efficiency. I can.

As a method of forming the second light extraction pattern 170 in the second embodiment, the first light extraction lens pattern 171 may be formed as a seed pattern by an etching mask and an etching process. Thereafter, a second light extraction lens pattern 172 having a zero gap level may be formed on the seed first light extraction lens pattern 171 by a deposition process. The second light extraction lens pattern 172 may be the same material as the material of the first light extraction lens pattern 171 or a material having a lower refractive index.

14 is an exemplary view of a third light extraction lens pattern 173 of a light emitting device according to the third embodiment.

The third embodiment can adopt the technical features of the first embodiment or the second embodiment.

In the third embodiment, the translucent electrode layer 130 patterned with a plurality of third light extracting lens patterns 173 and a plurality of fourth light extracting lens patterns 174 formed on the third light extracting lens pattern 173 ) Can be included.

At least two of the plurality of third light extraction lens patterns 173 may be spaced apart from each other by a second distance D2.

On the other hand, the plurality of fourth light extraction lens patterns 174 may contact each other.

According to the third embodiment, the gap between the fourth light extraction lens patterns 174 on the third light extraction lens pattern 173 is formed to be at a substantially zero level, so that the light-transmitting electrode layer 130 is exposed to air. Can be minimized.

Accordingly, when the light emitted from the active layer 114 is directed upward, it is extracted from the translucent electrode layer 130 through the fourth light extraction lens pattern 174, thereby significantly reducing the amount of total reflected light, thereby remarkably increasing the light extraction efficiency. I can make it.

15A to 15C are exemplary views of a fourth light extraction pattern of a light emitting device according to the fourth embodiment.

The fourth light extraction pattern of the fourth embodiment includes a hemispherical light extraction pattern 181 as shown in FIG. 15A, a conical light extraction pattern 182 having a curvature in the upper region as shown in FIG. 15B, or a pyramidal light extraction pattern as shown in FIG. 15C. 183). Through this, the ratio of total reflection occurring at the interface between the fourth light extraction pattern and the outside may be reduced, thereby increasing light extraction efficiency.

16 is a cross-sectional view of a light emitting device package according to an embodiment.

The light emitting device package according to the embodiment includes a package body part 205, a third electrode layer 213 and a fourth electrode layer 214 installed on the package body part 205, and the package body part 205. A light-emitting element 100 electrically connected to the third and fourth electrode layers 213 and 214, and a molding member 230 including a phosphor 232 and surrounding the light-emitting element 100 are included. .

The third electrode layer 213 and the fourth electrode layer 214 are electrically separated from each other and serve to provide power to the light emitting device 100. In addition, the third electrode layer 213 and the fourth electrode layer 214 may serve to increase light efficiency by reflecting light generated from the light emitting device 100, and It can also play a role in discharging heat to the outside.

The light emitting device 100 may be electrically connected to the third electrode layer 213 and/or the fourth electrode layer 214 by any one of a wire method, a flip chip method, or a die bonding method.

17 is an exploded perspective view of a lighting system according to an embodiment.

The lighting device according to the embodiment may include a cover 2100, a light source module 2200, a radiator 2400, a power supply unit 2600, an inner case 2700, and a socket 2800. In addition, the lighting device according to the embodiment may further include at least one of the member 2300 and the holder 2500. The light source module 2200 may include a light emitting device or a light emitting device package according to the embodiment.

The light source module 2200 may include a light source unit 2210, a connection plate 2230, and a connector 2250. The member 2300 is disposed on the upper surface of the radiator 2400 and has guide grooves 2310 into which a plurality of light source units 2210 and a connector 2250 are inserted.

The holder 2500 blocks the receiving groove 2719 of the insulating part 2710 of the inner case 2700. Accordingly, the power supply unit 2600 accommodated in the insulating unit 2710 of the inner case 2700 is sealed. The holder 2500 has a guide protrusion 2510.

The power supply unit 2600 may include a protrusion 2610, a guide portion 2630, a base 2650, and an extension 2670. The inner case 2700 may include a molding unit together with the power supply unit 2600 therein. The molding portion is a portion in which the molding liquid is solidified, and allows the power supply unit 2600 to be fixed inside the inner case 2700.

Features, structures, effects, and the like described in the embodiments above are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the embodiments.

Although the embodiments have been described above, these are only examples and are not intended to limit the embodiments, and those of ordinary skill in the field to which the embodiments belong are not departing from the essential characteristics of the present embodiment. It will be seen that branch transformation and application are possible. For example, each component specifically shown in the embodiment can be modified and implemented. And differences related to these modifications and applications should be construed as being included in the scope of the embodiments set in the appended claims.

The first conductivity type semiconductor layer 112, the active layer 114, the second conductivity type semiconductor layer 116,
The translucent electrode layer 130, the light extraction pattern 160, the first inclined surface S1, the lower region 160b,
Second inclined surface S2, upper region 160a

Claims (13)

A first conductivity type semiconductor layer;
An active layer on the first conductivity type semiconductor layer;
A second conductivity type semiconductor layer on the active layer;
A light-transmitting electrode layer having a first refractive index on the second conductivity-type semiconductor layer; And
Including; a light extraction pattern having a second refractive index smaller than the first refractive index on the translucent electrode layer,
The light extraction pattern includes a lower area including a first inclined surface having a first angle with respect to a vertical line on the light-transmitting electrode layer, and a second inclined surface having a second angle with respect to the vertical line. Includes an upper region disposed in,
The second angle is greater than the first angle,
The height of the lower region is at least 1 to 10 times the height of the upper region,
The horizontal width of the lowermost end of the lower region is greater than the horizontal width of the lowermost end of the upper region,
The light emitting device having a horizontal width of the lowermost end of the lower region is less than or equal to the total height of the light extraction pattern. delete delete delete delete delete delete delete delete delete delete delete delete

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