KR20150120268A - Nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a nitride semiconductor element and a manufacturing method thereof. The nitride semiconductor element according to an embodiment of the present invention comprises: an n-type nitride semiconductor layer; a low temperature growth layer disposed on an upper portion of the n-type nitride semiconductor layer, and grown at a lower temperature than the n-type nitride semiconductor layer; an activation layer disposed on an upper portion of the low temperature growth layer, and provided with a V-pit formed thereon; a high resistance filling layer which is disposed on an upper portion of the activation layer, and fills the V-pit; and a p-type nitride semiconductor layer disposed on an upper portion of the high resistance filling layer. An undoped layer and a doping layer can be layered in the high resistance filling layer one or more times to inject a hole to the activation layer through internal four sides of the V-pit. According to the present invention, the V-pit is filled using the high resistance filling layer, not the p-type nitride semiconductor layer to eliminate a problem such as an increase in leakage current according to a Mg doping condition or the like.

Description

[0001] NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [0002]

The present invention relates to a nitride semiconductor device and a manufacturing method thereof, and more particularly, to a nitride semiconductor device for improving electrostatic discharge characteristics and a manufacturing method thereof.

The nitride semiconductor is used as a light source for a display device, a traffic light, a lighting or an optical communication device, and can be used for a light emitting diode or a laser diode emitting blue or green light. It can also be used for a heterojunction bipolar transistor (HBT) and a high electron mobility transistor (HEMT).

The nitride semiconductor is difficult to obtain a lattice-matched substrate, and can be grown on a substrate such as sapphire, silicon carbide, or silicon where lattice mismatch occurs. Accordingly, the nitride semiconductor grown on such a substrate has a significantly higher threading dislocation density (TDD) of about 1E9 / cm2 or more.

This potential provides electron trap sites to induce non-luminescent recombination or provide a current leakage path. When an overvoltage such as static electricity is applied to a semiconductor device under such a condition, the current is concentrated through the actual potential and damage due to electrostatic discharge (ESD) occurs.

Several methods for compensating for poor electrostatic discharge characteristics of a nitride semiconductor device have been proposed. Generally, a zener diode is used together with a nitride semiconductor device. A zener diode is connected in parallel with the nitride semiconductor device to bypass the unexpected static discharge to the zener diode to protect the nitride semiconductor device. However, the zener diode is relatively expensive, and a process for using a zener diode is added to increase the cost and process time.

Alternatively, a substrate which is lattice-matched with a nitride semiconductor such as a GaN substrate can be used. However, since the GaN substrate has a very high manufacturing cost, it is difficult to apply it to a specific device other than a laser such as a laser.

In another method, a nitride semiconductor layer having V-pits is grown in the active layer by adjusting the growth temperature to improve the electrostatic discharge characteristics of the nitride semiconductor device, and then the p-type semiconductor layer is grown at a high temperature to fill the V- (Refer to Korean Patent No. 10-1026031). This technique can improve the electrostatic discharge characteristics by forming a potential barrier for the injection carrier by the V-pits formed in the active layer. However, there is a problem that the leakage current may increase depending on the Mg doping condition because the p-type semiconductor layer for filling the V-pit is not grown in a small growth margin.

Korean Patent No. 10-1026031 (Registered on March 23, 2011)

SUMMARY OF THE INVENTION The present invention provides a nitride semiconductor device having improved electrostatic discharge characteristics and a manufacturing method thereof.

A nitride semiconductor device according to an embodiment of the present invention includes: an n-type nitride semiconductor layer; A low-temperature growth layer located above the n-type nitride semiconductor layer and grown at a lower temperature than the n-type nitride semiconductor layer; An active layer located on the low-temperature growth layer and having a V-pit formed therein; A high-resistance buried layer located on the active layer and filling the V-pit; And a p-type nitride semiconductor layer located on top of the high-resistance buried layer, wherein the fixed-buried layer is formed on the undoped layer and the doped layer such that holes are injected into the active layer through the V- Or more.

In this case, the undoped layer may be a uAlGaN layer, the doping layer may be a p-type nitride semiconductor layer, the undoped layer may be a uGaN layer, and the doping layer may be a p-type nitride semiconductor layer. And the undoped layer and the doped layer may be stacked three times at an intersection.

At this time, the low temperature growth layer may contain In. The low-temperature growth layer may have a structure in which an AlInGaN-based nitride-based semiconductor layer and a GaN-based nitride-based semiconductor layer are stacked alternately.

In addition, the device may further include a super lattice layer positioned between the low temperature growth layer and the active layer and for growing the active layer. At this time, the V-pits may be formed over the active layer and the super lattice layer.

Further, the device may further include an electronic block layer located between the active layer and the high-resistance buried layer and filling a part of the V-pit. The high resistance buried layer may fill the remaining portion of the V-pit.

The high concentration barrier layer may further include a high concentration barrier layer doped with Si between the low temperature growth layer and the active layer. The concentration of doped Si in the high concentration barrier layer may be 1E19 / cm2 or more and 5E19 / cm2 or less.

A low-concentration doping layer may be interposed between the high-concentration barrier layer and the n-type nitride semiconductor layer.

In addition, a capacitor may be formed according to an embodiment of the present invention to improve electrostatic discharge characteristics when a reverse voltage is applied.

The superlattice layer may be doped at a low concentration and the doping concentration of the low concentration superlattice layer may be equal to or lower than the doping concentration of the low concentration doping layer. And a superlattice layer doped at a high concentration between the lightly doped layer and the lightly doped superlattice layer. By forming the capacitors in series in two rows according to this embodiment, it is possible to improve the electrostatic discharge characteristics when applying the reverse voltage.

Also, the V-pits can be formed across the high-concentration barrier layers, so that the high-concentration barrier layers can be formed in a three-dimensional shape in a conventional two-dimensional shape. Therefore, as the area of the V-pit increases, the horizontal area of the V-pit high-concentration barrier layers becomes wider and the capacitance can be increased.

According to another aspect of the present invention, there is provided a method of fabricating a nitride semiconductor device, including: forming an n-type nitride semiconductor layer on a substrate; Forming a low-temperature growth layer on the n-type nitride semiconductor layer at a temperature lower than that of the n-type nitride semiconductor layer; Forming an active layer having a top surface surrounding the V-pit and the V-pit on the low-temperature grown layer; Forming a high-resistance buried layer filling the V-pits on the active layer; And forming a p-type nitride semiconductor layer on the high-resistance buried layer. The step of forming the high-resistance buried layer may be performed by alternately laminating the undoped layer and the doped layer at least once.

Here, the n-type nitride semiconductor device may be formed at a temperature of 1000 ° C to 1200 ° C, and the low temperature growth layer may be formed at a temperature of 900 ° C or lower.

At this time, the undoped layer may be a uAlGaN layer, the doping layer may be a p-type nitride semiconductor layer, and the uAlGaN layer and the p-type nitride semiconductor layer as a doping layer may be repeatedly stacked for three cycles.

In addition, the undoped layer may be a uGaN layer, the doping layer may be a p-type nitride semiconductor layer, and the uGaN layer and the p-type nitride semiconductor layer as a doping layer may be repeatedly laminated for three cycles.

By adopting the low-temperature grown layer, the size of the V-pit can be increased, and the efficiency of injecting electrons into the active layer through the high concentration barrier layer is improved. Therefore, the electrostatic discharge characteristic is improved without deteriorating the luminance or electrical characteristics of the nitride semiconductor device can do.

Further, since the V-pit is filled with the high-resistance buried layer instead of the p-type nitride semiconductor layer, there is no problem such that the leak current increases according to the Mg doping condition. Moreover, since the V-pits are filled with the high-resistance buried layer, the actual potential can be prevented from acting as a path of the leakage current, and the nitride semiconductor device can be prevented from being broken due to external high voltage.

Also, since a high concentration barrier layer doped with high concentration Si is disposed at a position where the active layer starts and a low concentration doping layer is interposed between the n-type nitride semiconductor layer and the high concentration barrier layer, the capacitance of the nitride semiconductor device increases, The characteristics are improved. At this time, the internal capacitance is proportional to the area of the high-concentration barrier layer. Since the high-concentration barrier layer is formed in a three-dimensional shape and the area is increased by the area of the V-pit, the internal capacitance becomes larger, and the electrostatic discharge characteristic can be improved more effectively.

The V-pit formed in the nitride semiconductor device is filled with a high-resistance filling layer, thereby preventing the V-pit from acting as a leakage path.

Further, when the high-resistance buried layer is grown, since the region of the p-type nitride semiconductor layer is changed to the AlGaN layer, the nitride semiconductor device having the stronger resistance can be grown. Furthermore, since the uAlGaN layer, the p-type nitride semiconductor layer, the uGaN layer and the p-type nitride semiconductor layer are periodically grown, holes are injected into each well layer in the active layer through the inner slope of the V-pit, . Also, holes can be effectively injected into the well layer nearest to the n-type nitride semiconductor layer, which is difficult to implant because the V-pits extend over the entire active layer.

1 is a cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention.
2 is a partial cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention.
3 is a partial cross-sectional view illustrating a nitride semiconductor device according to another embodiment of the present invention.
4 is a TEM photograph of a nitride semiconductor device according to an embodiment of the present invention.
5 is a TEM photograph of a conventional nitride semiconductor device.
6 is a partial cross-sectional view illustrating a nitride semiconductor device according to another embodiment of the present invention.
7 is a flowchart illustrating a process for forming a high-resistance buried layer in a V-pit of a nitride semiconductor device according to another embodiment of the present invention.
8 is a partial cross-sectional view showing a high-resistance buried layer in the V-pit of the nitride semiconductor device according to another embodiment of the present invention.
9 is a graph showing electrostatic discharge characteristics of a nitride semiconductor device according to another embodiment of the present invention.

Embodiments of the present invention will be described more specifically with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a nitride semiconductor device according to one embodiment of the present invention, and FIG. 2 is a partial cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention. In the present invention, a nitride light emitting diode will be described as an example of a nitride semiconductor device.

1, the nitride light emitting diode includes a substrate 21, an n-type nitride semiconductor layer 25, a low temperature growth layer 27, a superlattice layer 29, an active layer 33, an electronic block layer 35, A high-resistance buried layer 37 and a p-type nitride semiconductor layer 39.

The substrate 21 is for growing a gallium nitride-based semiconductor layer, and sapphire, SiC, Si, spinel, or the like can be used. In addition, the buffer layer 23 can be grown to improve the crystal quality of the nitride semiconductor single crystal grown on the substrate 21. [

The buffer layer 23 usually comprises a low-temperature buffer layer and a high-temperature buffer layer. The low-temperature buffer layer may be formed of (Al, Ga) N on the substrate 21 at a low temperature of 400 DEG C to 600 DEG C, and may be formed of GaN or AlN, for example. The low temperature buffer layer may be formed, for example, to a thickness of about 25 nm. The high temperature buffer layer can be grown at a relatively high temperature to mitigate the occurrence of defects such as dislocation between the substrate 21 and the n-type nitride semiconductor layer 25. [ The high-temperature buffer layer may be formed of undoped GaN or GaN doped with an n-type impurity. During the formation of the buffer layer 23, a real electric potential D is generated between the substrate 21 and the buffer layer 23 by lattice mismatching.

The n-type nitride semiconductor layer 25 may be a nitride semiconductor layer doped with an n-type impurity, for example, a nitride semiconductor layer doped with Si. The Si doping concentration to be doped in the n-type nitride semiconductor layer 25 may be 5E17 / cm2 to 5E19 / cm2. The n-type nitride semiconductor layer 25 may be grown under a growth pressure of 150 Torr to 200 Torr at 1000 ° C to 1200 ° C (for example, 1050 ° C to 1100 ° C) by supplying a metal source gas into the chamber using MOCVD technology. At this time, the n-type nitride semiconductor layer 25 may be continuously formed on the buffer layer 23, and the actual potential D formed in the buffer layer 23 may be transferred to the n-type nitride semiconductor layer 25.

The low temperature growth layer 27 is located on top of the n-type nitride semiconductor layer 25. In one embodiment of the present invention, the low-temperature growth layer 27 may be formed with a structure in which at least one AlInGaN layer 27a and at least one AlGaN layer 27b are alternately stacked. At this time, it is better that the number of stacked layers is increased as much as possible, but the stacked layers are preferably stacked so that the luminance intensity of the nitride light emitting diode is not lowered.

And the low temperature growth layer 27 can be grown at a relatively lower temperature than the n-type nitride semiconductor layer 25. [ In one embodiment of the present invention, the low temperature grown layer 27 can be grown at a temperature of about 900 < 0 > C. The low-temperature growth layer 27 is grown at a relatively lower temperature than the n-type nitride semiconductor layer 25, thereby artificially lowering the crystal quality and promoting the three-dimensional growth so as to form a seed of V- As a result, the size of the V-pit V generated in the active layer 33 can be increased artificially.

In addition, in order to increase the size of the V-pit V more effectively, the lattice constant can be made larger than that of the n-type nitride semiconductor layer 25. For example, the low temperature growth layer 27 containing In can be formed. That is, as described above, the reason why the AlInGaN layer 27a is included in the low-temperature growth layer 27 is the reason. When In is contained in this manner, a difference in lattice constant occurs between the low-temperature growth layer 27 and the n-type nitride semiconductor layer 25, and a phenomenon that the irregular defect of the actual potential D radiates in the form of V-pits (V) The interface of the V-pit V becomes more certain and the size of the V-pit V becomes larger. In addition to AlInGaN, InGaN or InAlN may be used.

The active layer 33 is located on top of the low temperature growth layer 27 and superlattice layers 29 may be formed between the low temperature growth layer 27 and the active layer 33 in one embodiment of the present invention. have. The superlattice layer 29 may be implemented with InGaN / InGaN. Also, the diffusion of V-pits (V) is accelerated due to the difference between the mean lattice constant of the superlattice layer 29 and the lattice constant of the n-type nitride semiconductor layer 25 and the lower low temperature growth layer 27.

For example, the lattice constant of the low-temperature grown layer 27 is the smallest, the mean lattice constant of the superlattice layer 29 is the medium value, and the lattice constant of the active layer 33 is the largest. Accordingly, the V-pit (V) can be enlarged by applying a compressive strain continuously to the V-pit (V). As another example, the storage constant of the low temperature growth layer 27 is the smallest, the average lattice constant of the superlattice layer 29 is the largest, and the lattice constant of the active layer 33 can have the intermediate value. The magnitude of the V-pit V is proportional to the difference in mean lattice constant between the superlattice layer 29 and the low temperature grown layer 27 and the thickness of the superlattice layer 29, However, if the lattice constant difference between the superlattice layer 29 and the active layer 33 is large, a piezoelectric field will increase inside the inner quantum well layer of the active layer 33, resulting in a quantum confined stark effect The inner quantum efficiency of the active layer 33 may be lowered, so that the superlattice layer 29 is required to have a proper thickness and composition ratio. In one embodiment of the present invention, the superlattice layer 29 may be InGaN having an average thickness of about 70 nm to 100 nm and a composition ratio of In of 5% to 10%. The composition ratio of the well layer in the active layer 33 may be an InGaN layer having In of 10% to 20%. The In composition ratio of the low temperature grown layer 27 may be 5% or less. The higher the composition ratio of In than the lower layer, the more compressive strain is applied to the upper layer, so that the V-pit can be gradually diffused.

The active layer 33 emits light having a predetermined energy by recombination of electrons and holes. The active layer 33 may have a single quantum well structure or a multiple quantum well (MQW) structure in which a quantum barrier layer and a quantum well layer are alternately stacked. The quantum barrier layer may be formed of a nitride semiconductor layer such as GaN, InGaN, AlGaN, or AlInGaN having a band gap wider than that of the quantum well layer. In one embodiment, the quantum barrier layer may be formed of AlInGaN to improve the recombination efficiency of the carriers.

The quantum well layer is formed of a nitride semiconductor layer having a narrower bandgap relative to the quantum barrier layer. For example, the quantum well layer may be formed of a gallium nitride semiconductor layer such as InGaN, and a composition ratio for bandgap adjustment may be determined by a desired wavelength . The active layer 33 can be in contact with the low temperature growth layer 27 and the superlattice layer 29 can be interposed therebetween as in the present invention or the current diffusion 33 between the active layer 33 and the low temperature growth layer 27 Layer may be interposed.

The quantum barrier layer and the quantum well layer of the active layer 33 may be formed of an undoped layer which is not doped with an impurity to improve the crystal quality of the active layer 33. However, in order to lower the forward voltage, May be doped.

As described above, when the quantum barrier layer of the active layer 33 is formed of AlInGaN, the V-pit V may be formed on the upper surface with the actual potential D as a center. The V-pits V may be formed in the shape of inverted hexagonal horns, and the size of the V-pits V may be made larger according to the position of the low temperature growth layer 27 and the composition ratio and thickness of the superlattice layer 29 . At this time, the superlattice layer 29 and the active layer 33 grow due to the strain caused by the difference in lattice constant between the superlattice layer 29 formed of InGaN / InGaN and the active layer 33 formed of AlInGaN, The pits V are continuously formed and can be formed larger due to the influence of the low temperature growth layer 27. [

The V-pit V can be formed in the active layer 33 even if the low-temperature growth layer 27 is not interposed between the n-type nitride semiconductor layer 25 and the superlattice layer 29. However, the size of the V-pit V may be less than 100 nm. On the other hand, if the content of In included in the low-temperature growth layer 27 is adjusted while the low-temperature growth layer 27 is interposed, as in the embodiment of the present invention, the size of the V- And can be formed to have a maximum size of 200 nm. In addition, the interface can be more sure. Here, the size of the V-pit (V) means the maximum width of the width.

The V-pits V are formed across the superlattice layer 29 and the active layer 33, Grown growth layer 27 to the upper end of the low-temperature growth layer 27.

In one embodiment of the present invention, a high-concentration Si-doped high-concentration barrier layer 31 may be interposed at the starting point where the active layer 33 is grown. The high-concentration barrier layer 31 can be rapidly grown to achieve higher Si doping and can include In or Al to improve the horizontal dispersion of electrons, and Si can be doped to a concentration of 1E19 / cm2 to 5E19 / cm2 have. At this time, the thickness of the high-concentration barrier layer 31 is preferably 10 nm or more in consideration of the horizontal dispersion effect of electrons. Further, a lightly doped layer 30 may be interposed between the high-concentration barrier layer 31 and the n-type nitride semiconductor layer 25. [ The superlattice layer 29 sandwiched between the high concentration barrier layer 31 and the n-type nitride semiconductor layer 25 can be doped at a low concentration. By forming the low-concentration layer between the high-concentration layers in this manner, a capacitor can be formed inside to improve the electrostatic discharge characteristics. At this time, the doping concentration of the lightly doped superlattice layer 29 may be equal to or lower than the doping concentration of the lightly doping layer 30.

Although not shown in the drawing, the high-concentration barrier layer 31 is provided between the lightly doped layer 30 and the lightly doped superlattice layer 29, between the lightly doped superlattice layer 29 and the active layer 33 A plurality of internal capacitors can be formed in series. When a plurality of low concentration layers are formed between the high concentration layers and the capacitors are connected in series, the capacitance can be improved while facilitating the injection of the former active layer 33 upon application of the forward voltage.

On the other hand, a V-pit V can be formed from the low-temperature growth layer 27 to be formed across the high-concentration barrier layer 31, the lightly doped layer 30, and the active layer 33. Accordingly, the high-concentration barrier layer 31 is formed in a three-dimensional shape in which the V-pits V are formed instead of the layered two-dimensional structure, compared with the prior art in which the V-pits V are absent or small. As the V-pit V increases in size due to the high concentration barrier layer 31 formed in the three-dimensional shape, the horizontal area of the high concentration barrier layer 31 widens and the capacity of the capacitor increases. The electrostatic discharge characteristic can be further improved.

When only the high-concentration Si-doped high-concentration barrier layer 31 is interposed without the low-temperature growth layer 27 interposed therebetween, V-pits V having a very low density and a small size are formed. . Therefore, by forming the low-temperature growth layer 27 and increasing the size of the V-pit V and interposing the high-concentration barrier layer 31, the leakage current through the actual potential D during the generation of the electrostatic discharge is effectively blocked, The electrostatic discharge characteristics can be improved.

On the other hand, after the low temperature growth layer 27 is grown, there may be an annealing process. The annealing is performed while raising the temperature to about 1050 DEG C and lowering the temperature after the low temperature growth layer 27 is grown. 2, the starting point at which the V-pit V is generated is formed on the low temperature growth layer 27. However, if the annealing process is omitted, as shown in Fig. 3, the V- The pit V generation starting point may be formed down to the low temperature growth layer 27. [ Therefore, it is possible to more finely control the size of the V-pit V by adjusting the maximum temperature and the fall time of the annealing process than by adjusting the composition ratio or the thickness of the superlattice layer 29.

Therefore, the annealing process may be added or omitted as a process for adjusting the size of the V-pit (V).

The EBL 35 may be formed between the active layer 33 and the high resistance buried layer 37. The EBL 35 may be formed on the active layer 33, Located. The electron blocking layer 35 may be formed of AlGaN or AlInGaN and may be formed of AlInGaN to mitigate lattice mismatch with the active layer 33. [ At this time, the electron blocking layer 35 may contain about 25% Al, and may be doped with P-type impurities such as Mg, but may not intentionally be doped with impurities. In one embodiment of the present invention, the electron blocking layer 35 may be formed to a thickness of about 20 nm to 25 nm.

The electron blocking layer 35 is located on the active layer 33 and fills a part of the V-pit V formed over the active layer 33 and the superlattice layer 29. That is, the electronic block layer 35 covers the upper surface of the active layer 33 and the surface of the V-pit V. The electronic block layer 35 is not formed to have a thickness enough to fill all of the V-pits V formed over the active layer 33 and the superlattice layer 29, and thus only a part of the V-pits V is filled.

A high-resistance filling layer 37 is disposed on the top of the electronic block layer 35. The high-resistance filling layer 37 is located above the electron blocking layer 35, filling the V-pits V that are not filled by the electron blocking layer 35. Therefore, the electrostatic discharge characteristic of the nitride light-emitting diode of the present invention can be improved by blocking the action of the actual electric potential D as a path of the leakage current in the high-resistance filling layer 37.

Also, since the V-pit V is filled with the high-resistance buried layer 37 without filling it with the p-type nitride semiconductor layer 39, the resistivity of the inner region of the V-pit (V) It grows.

In particular, the high-resistance filling layer 37 may be formed of AlGaN containing Al. By filling the V-pit (V) with the high-resistance filling layer 37 containing Al, the resistivity of the V-pit (V) inner region can be further lowered, It is possible to block the action.

The p-type nitride semiconductor layer 39 may be formed of a semiconductor layer doped with a p-type impurity such as Mg. The p-type nitride semiconductor layer 39 may be a single layer or a multilayer, and may include a p-type cladding layer and a p-type contact layer. A transparent electrode such as ITO may be disposed on the p-type nitride semiconductor layer 39. On the other hand, an electrode is formed on the exposed n-type nitride semiconductor layer 25 by partially removing the p-type nitride semiconductor layer 39, the high-resistance buried layer 37, the active layer 33 and the low-temperature grown layer 27 . Thereby, the electrode formed on the n-type nitride semiconductor layer 25 is formed as the second electrode 45 on the first electrode 43 and the transparent electrode 41 formed on the p-type nitride semiconductor layer 39, Can be completed.

FIG. 4 is a TEM photograph of a nitride semiconductor device according to an embodiment of the present invention, and FIG. 5 is a TEM photograph of a conventional nitride semiconductor device.

As shown in FIG. 4, the maximum width of the V-pit (V) width is about 191 nm, and the depth of the V-pit (V) Which is about 153 nm. 5, the V-pits V formed in the conventional nitride light emitting diode without the low temperature growth layer 27 interposed therebetween can be confirmed. Therefore, it can be confirmed that the size of the V-pit V formed in the nitride light-emitting diode of the present invention including the low-temperature growth layer 27 is larger than that of the prior art.

6 is a partial cross-sectional view illustrating a nitride semiconductor device according to another embodiment of the present invention.

Other embodiments of the present invention described above will be described while omitting the same descriptions as those of the first embodiment, and the same reference numerals can be used for the same configurations.

In another embodiment of the present invention, the nitride semiconductor device is applied by changing the p-type nitride semiconductor layer into the high-resistance buried layer 37 without growing the buried V-pit V into the high-resistance buried layer 37 . To increase the resistance of the high-resistance filling layer 37, Al may be added.

The process of using the p-type nitride semiconductor layer to fill the V-pit V with the high-resistance filling layer 37 will be described in more detail as follows. The p-type nitride semiconductor layer is used to grow the electron block layer 35 before filling the p-type nitride semiconductor layer. In another embodiment of the present invention, the electronic block layer 35 is not formed in the V-pit V, unlike in the embodiment, but may be formed along the V-pit V, have. That is, in another embodiment of the present invention, an electron blocking layer 35 may be formed on the active layer 33 along the V-pit (V).

6, only the active layer 33 is shown. However, the superlattice layer 29 and the high concentration barrier layer 31 may be formed in the same manner as in the embodiment of the present invention.

7 is a flowchart illustrating a process for forming a high-resistance buried layer in a V-pit of a nitride semiconductor device according to another embodiment of the present invention. Referring to FIG. 7, a high-resistance buried layer As shown in Fig. 8 is a partial cross-sectional view showing a high-resistance buried layer in the V-pit of the nitride semiconductor device according to another embodiment of the present invention.

Referring to FIGS. 7 and 8, the undoped layer 37a is grown to a thickness of 30 to 40 nm, and the p-type nitride semiconductor layer 37b is grown to a thickness of 3 to 5 nm. Then, the undoped layer 37a and the p-type nitride semiconductor layer 37b as a doping layer are grown in order. In another embodiment of the present invention, the undoped layer 37a and the p-type nitride semiconductor layer 37b are sequentially grown in three cycles. The hole injection can be improved by periodically and repeatedly growing the undoped layer 37a and the p-type nitride semiconductor layer 37b. The undoped layer 37a and the p-type nitride semiconductor layer 37b are sequentially grown in three cycles and then the undoped layer 37a is thickened so that the high-resistance buried layer 37 is buried in the V- can do.

In one embodiment of the present invention, the density of the V-pits V may be between 1E8 cm ^-1 and 5E8 cm ^-1 , and the size of the V-pits V may be between 100 nm and 200 nm. When the area of the V-pit (V) is calculated using this, the area of the V-pit (V) may be 2 to 23% of the total area, and the hole injection efficiency can be correspondingly improved. The improvement of the hole injection efficiency can be applied not only to the non-high-resistance buried layer 37 but also to the high-concentration barrier layer 31. [

At this time, TMGa shown in FIG. 7 is a Ga source, and TMAl can be used as a source of Al. And Cp2Mg can be used as a source of Mg.

9 is a graph showing electrostatic discharge characteristics of a nitride semiconductor device according to another embodiment of the present invention.

In order to measure the electrostatic discharge characteristics, a reverse voltage and a forward voltage were sequentially applied to a plurality of nitride semiconductor devices three times at 3 kV, and a leakage current of the total number of nitride semiconductor devices before and after the application was -5 V, The number was defined as the yield.

As described above, according to another embodiment of the present invention, it can be seen that the electrostatic discharge yield is improved compared to the conventional art. That is, when the conventional nitride semiconductor device has an electrostatic discharge defective ratio of 1 to 3%, it can be seen that the electrostatic discharge defective rate of the nitride semiconductor device according to another embodiment of the present invention is improved to 0 to 1.5% . When the resistance of the nitride semiconductor device to electrostatic discharge is strengthened, it is possible to prevent the light emitting element from being damaged by static electricity generated by a machine or a person.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. And the scope of the present invention should be understood as the following claims and their equivalents.

21: substrate 23: buffer layer
25: n-type nitride semiconductor layer 27: low temperature growth layer
29: superlattice layer 30: lightly doped layer
31: high-concentration barrier layer 33: active layer
35: Electronic block layer 37: High resistance buried layer
39: p-type nitride semiconductor layer 41: transparent electrode
43: first electrode 45: second electrode
D: Actual potential V: V-foot

Claims (17)

an n-type nitride semiconductor layer;
A low-temperature growth layer located above the n-type nitride semiconductor layer and grown at a lower temperature than the n-type nitride semiconductor layer;
An active layer located on the low-temperature growth layer and having a V-pit formed therein;
A high-resistance buried layer located on the active layer and filling the V-pit; And
And a p-type nitride semiconductor layer located on top of the high-resistance buried layer,
Wherein the fixed binding layer is formed by alternately stacking the undoped layer and the doped layer at least once such that holes are injected into the active layer through the V-pit inner slope. The method according to claim 1,
The undoped layer is a uAlGaN layer, and the doping layer is a p-type nitride semiconductor layer. The method according to claim 1,
The undoped layer is a uGaN layer, and the doping layer is a p-type nitride semiconductor layer. The method according to claim 1,
And the undoped layer and the doped layer are stacked three times at an intersection. The method according to claim 1,
Wherein the low temperature growth layer contains In. The method of claim 5,
Wherein the low-temperature growth layer is formed by alternately stacking an AlInGaN-based nitride-based semiconductor layer and an AlGaN-based nitride-based semiconductor layer. The method according to claim 1,
And a super lattice layer positioned between the low temperature growth layer and the active layer and for growing the active layer. The method of claim 7,
And the V-pit is formed over the active layer and the superlattice layer. The method according to claim 1,
Further comprising an electronic block layer located between the active layer and the high-resistance buried layer and filling a portion of the V-pit,
And the high-resistance buried layer filling the remaining portion of the V-pit. The method according to claim 1,
And a high-concentration barrier layer doped with Si between the low temperature growth layer and the active layer. The method of claim 10,
And the concentration of doped Si in the high concentration barrier layer is not less than 1E19 / cm2 and not more than 5E19 / cm2. Forming an n-type nitride semiconductor layer on a substrate;
Forming a low-temperature growth layer on the n-type nitride semiconductor layer at a temperature lower than that of the n-type nitride semiconductor layer;
Forming an active layer having a top surface surrounding the V-pit and the V-pit on the low-temperature grown layer;
Forming a high-resistance buried layer filling the V-pits on the active layer; And
And forming a p-type nitride semiconductor layer on the high-resistance buried layer,
Wherein the step of forming the high-resistance buried layer comprises forming at least one of the undoped layer and the doped layer by alternately laminating the undoped layer and the doped layer. The method of claim 12,
The n-type nitride semiconductor device is formed at a temperature of 1000 ° C to 1200 ° C,
Wherein the low-temperature growth layer is formed at 900 DEG C or lower. The method of claim 12,
Wherein the undoped layer is a uAlGaN layer, and the doping layer is a p-type nitride semiconductor layer. 15. The method of claim 14,
And the p-type nitride semiconductor layer as the doping layer are repeatedly stacked for three cycles. The method of claim 12,
Wherein the undoped layer is a uGaN layer and the doping layer is a p-type nitride semiconductor layer. 18. The method of claim 16,
Wherein the u-GaN layer and the p-type nitride semiconductor layer, which is a doping layer, are repeatedly stacked for three cycles.

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