KR102071038B1 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a nitride semiconductor device and a manufacturing method thereof, the nitride semiconductor device according to an embodiment of the present invention, n-type nitride semiconductor layer; A low temperature growth layer positioned on the n-type nitride semiconductor layer and grown at a lower temperature than the n-type nitride semiconductor layer; A lightly doped layer positioned on the cold growth layer; A high concentration barrier layer positioned on the low concentration doping layer and doped with Si; An active layer positioned on the high concentration barrier layer; And a p-type nitride semiconductor layer disposed on the active layer, wherein the doping concentration of the low concentration doping layer is lower than the doping concentration of the high concentration barrier layer and the n-type nitride semiconductor layer to form a capacitor. V-pits may be formed over the superlattice layer. According to the present invention, a high concentration barrier layer doped with a high concentration of Si is interposed at a position where the active layer starts, and a low temperature growth layer is interposed between the n-type nitride semiconductor layer and the high concentration barrier layer to increase the internal capacitance of the nitride semiconductor device, thereby electrostatic discharge. There is an effect that the characteristics are improved.

Description

Nitride semiconductor device and its manufacturing method {NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF}

The present invention relates to a nitride semiconductor device and a method for manufacturing the same, and more particularly to a nitride semiconductor device and a method for manufacturing the same for improving the electrostatic discharge characteristics.

The nitride semiconductor is used as a light source of a display device, a signal lamp, an illumination or an optical communication device, and may be used in a light emitting diode or a laser diode emitting blue or green light. It can also be used for heterojunction bipolar transistors (HBT) and high electron mobility transistors (HEMT).

Nitride semiconductors are not easy to obtain a lattice matched substrate, and can be grown on a lattice mismatch such as sapphire, silicon carbide or silicon. Accordingly, nitride semiconductors grown on such substrates have a significantly higher threading dislocation desity (TDD) of about 1E9 / cm 3 or more.

These real potentials provide electronic trap sites to cause non-luminescing recombination or to provide current leakage paths. In such a state, when an overvoltage such as static electricity is applied to the semiconductor device, current is concentrated through the real potential, thereby causing damage due to electrostatic discharge (ESD).

Several proposals have been made to compensate for the poor electrostatic discharge characteristics of nitride semiconductor devices. Typically, a Zener diode is used together with a nitride semiconductor element. The Zener diode is connected in parallel with the nitride semiconductor element to bypass the unexpected electrostatic discharge with the zener diode to protect the nitride semiconductor element. However, Zener diodes are relatively expensive, and there is a problem in that cost and processing time increase due to an additional process for using a Zener diode.

Alternatively, a substrate that lattice matches with a nitride semiconductor, such as a GaN substrate, may be used, but the GaN substrate has a high manufacturing cost, which makes it difficult to apply except for certain devices such as lasers.

In another method, a technique of growing a nitride semiconductor layer having a V-pit in an active layer by controlling a growth temperature to improve electrostatic discharge characteristics of a nitride semiconductor device, and then growing the p-type semiconductor layer at a high temperature to fill the V-pit There is (see the Republic of Korea Patent Registration No. 10-1026031). This technique allows the V-pits formed in the active layer to form potential barriers to the injection carrier to improve the electrostatic discharge characteristics. However, there is a problem that the leakage current may increase according to the Mg doping conditions because the growth process margin of the p-type semiconductor layer to fill the V-pit is small.

Republic of Korea Patent No. 10-1026031 (Registration Date: 2011.03.23)

The problem to be solved by the present invention is to provide a nitride semiconductor device and a manufacturing method with improved electrostatic discharge characteristics.

A nitride semiconductor device according to an embodiment of the present invention, an n-type nitride semiconductor layer; A low temperature growth layer positioned on the n-type nitride semiconductor layer and grown at a lower temperature than the n-type nitride semiconductor layer; A lightly doped layer positioned on the cold growth layer; A high concentration barrier layer positioned on the low concentration doping layer and doped with Si; An active layer positioned on the high concentration barrier layer; And a p-type nitride semiconductor layer positioned on the active layer, wherein the doping concentration of the low concentration doping layer is lower than the doping concentration of the high concentration barrier layer and the n-type nitride semiconductor layer to form a capacitor. V-pits may be formed over the superlattice layer.

In this case, the concentration of Si doped in the high concentration barrier layer may be 1E19 / cm 3 or more and 5E19 / cm 3 or less.

And a low concentration superlattice layer between the low concentration doping layer and the high concentration barrier layer, and the doping concentration of the low concentration superlattice layer may be equal to or lower than the doping concentration of the low concentration doping layer.

In addition, a low concentration doping layer may be interposed between the high concentration barrier layer and the n-type nitride semiconductor layer.

In addition, by forming a capacitor according to an embodiment of the present invention it is possible to improve the electrostatic discharge characteristics when applying a reverse voltage.

The superlattice layer may be lightly doped, and the doping concentration of the low concentration superlattice layer may be equal to or lower than that of the low concentration doping layer. And a superlattice layer doped at a high concentration between the lightly doped layer and the lightly doped superlattice layer. Thus, by forming the capacitors in series in two rows according to the embodiment, it is possible to improve the electrostatic discharge characteristics when applying reverse voltage.

In addition, the V-pit may be formed across the high concentration barrier layers, and thus the high concentration barrier layers may be formed into a three-dimensional shape from a conventional two-dimensional shape. Therefore, as the area of the V-pit increases, the horizontal area of the high-concentration barrier layers of the V-pit can be widened, thereby increasing the capacitance.

And a high resistance fill layer disposed between the active layer and the p-type nitride semiconductor layer and filling the V-pit, and located between the active layer and the high concentration barrier layer and filling a portion of the V-pit. Further comprising a block layer, wherein the high resistance fill layer may fill the remaining portion of the V-pit.

In this case, the low temperature growth layer may be grown at a temperature of 900 degrees or less.

On the other hand, the nitride semiconductor device manufacturing method according to an embodiment of the present invention, forming an n-type nitride semiconductor layer on a substrate; Forming a low temperature growth layer on the n-type nitride semiconductor layer at a lower temperature than the n-type nitride semiconductor layer; Forming a lightly doped layer with low concentration of Si on the low temperature growth layer; Forming a high barrier layer doped with Si on the low doping layer; Forming an active layer on the cold growth layer, the active layer having a V-pit and a top surface surrounding the V-pit formed across the high concentration barrier layer; And forming a p-type nitride semiconductor layer on the active layer.

In this case, the concentration of Si doped in the high concentration barrier layer may be 1E19 / cm 3 or more and 5E19 / cm 3 or less.

The n-type nitride semiconductor device may be formed at 1000 ° C. to 1200 ° C., and the low temperature growth layer may be formed at 900 ° C. or less.

The method may further include forming a superlattice layer for growing the active layer between forming the low temperature growth layer and forming the active layer. In this case, the doping concentration of the superlattice layer may be equal to or lower than the doping concentration of the low concentration doping layer.

The method may further include forming a high resistance filling layer filling the V-pit between the forming of the active layer and the forming of the p-type nitride semiconductor layer.

By adopting the low temperature growth layer, the size of the V-pit can be increased, and the efficiency of injecting electrons into the active layer through the high concentration barrier layer increases, thereby improving the electrostatic discharge characteristics without deteriorating the brightness or electrical characteristics of the nitride semiconductor device. can do.

In addition, since the V-pit is filled using a high resistance filling layer instead of the p-type nitride semiconductor layer, there is an effect that a problem such as an increase in leakage current according to Mg doping conditions does not occur. Furthermore, since the V-pit is filled using the high resistance filling layer, it is possible to prevent the real potential from acting as a path of the leakage current, thereby preventing the nitride semiconductor element from being destroyed by an external high voltage.

In addition, a high concentration barrier layer doped with a high concentration of Si is interposed at the starting point of the active layer, and a low concentration doping layer is interposed between the n-type nitride semiconductor layer and the high concentration barrier layer, thereby increasing the internal capacitance of the nitride semiconductor device, thereby causing electrostatic discharge. There is an effect that the characteristics are improved. In this case, the internal capacitance is proportional to the area of the high concentration barrier layer. Since the high concentration barrier layer is formed in a three-dimensional shape and the area is increased by the area of the V-pit, the internal capacitance is increased, thereby improving the electrostatic discharge characteristics more effectively.

In addition, the V-pit formed inside the nitride semiconductor element is filled with a high resistance filling layer, thereby preventing the V-pit from acting as a leakage pass.

In addition, when the high-resistance filling layer is grown, the p-type nitride semiconductor layer region is changed to an AlGaN layer to be grown, so that a nitride semiconductor device having stronger resistance than the conventional one can be grown. In addition, since the uAlGaN layer, the p-type nitride semiconductor layer, and the uGaN layer and the p-type nitride semiconductor layer are periodically grown, holes are injected into each well layer in the active layer through the inner slope of the V-pit, thereby improving the hole injection efficiency. . In addition, since the V-pit is spread over the active layer, holes can be effectively injected into the well layer closest to the n-type nitride semiconductor layer, which is difficult to inject.

1 is a cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention.
2 is a partial cross-sectional view for describing a nitride semiconductor device according to an embodiment of the present invention.
3 is a partial cross-sectional view for describing a nitride semiconductor device according to another exemplary embodiment of the present invention.
4 is a TEM photograph of a nitride semiconductor device according to an embodiment of the present invention.
5 is a TEM photograph of a conventional nitride semiconductor device.
6 is a partial cross-sectional view for describing a nitride semiconductor device according to another exemplary embodiment of the present invention.
7 is a flowchart illustrating a process for forming a high resistance filling layer in a V-pit of a nitride semiconductor device according to another exemplary embodiment of the present invention.
8 is a partial cross-sectional view showing a high resistance filling layer in a V-pit of a nitride semiconductor device according to another exemplary embodiment of the present invention.
9 is a graph showing the electrostatic discharge characteristics of a nitride semiconductor device according to another embodiment of the present invention.

Embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention, and FIG. 2 is a partial cross-sectional view illustrating a nitride semiconductor device according to an embodiment of the present invention. In the present invention, a nitride light emitting diode will be described as an example of a nitride semiconductor element.

Referring to FIG. 1, the nitride light emitting diode includes a substrate 21, an n-type nitride semiconductor layer 25, a low temperature growth layer 27, a superlattice layer 29, an active layer 33, an electron block layer 35, A high resistance fill layer 37 and a p-type nitride semiconductor layer 39 are included.

The substrate 21 is for growing a gallium nitride based semiconductor layer, and sapphire, SiC, Si, spinel, or the like may be used. In addition, the buffer layer 23 may be grown to improve crystal quality of the nitride semiconductor single crystal grown on the substrate 21.

The buffer layer 23 usually includes a low temperature buffer layer and a high temperature buffer layer. The low temperature buffer layer may be formed of (Al, Ga) N on the substrate 21 at a low temperature of 400 ° C to 600 ° C. For example, the low temperature buffer layer may be formed of GaN or AlN. The low temperature buffer layer can be formed, for example, about 25 nm thick. The high temperature buffer layer may be grown at a relatively high temperature to mitigate the occurrence of defects such as dislocations between the substrate 21 and the n-type nitride semiconductor layer 25. The high temperature buffer layer may be formed of undoped GaN or GaN doped with n-type impurities. At this time, while the buffer layer 23 is formed, the real potential D is generated by lattice mismatch between the substrate 21 and the buffer layer 23.

The n-type nitride semiconductor layer 25 may be a nitride-based semiconductor layer doped with n-type impurities, for example, a nitride semiconductor layer doped with Si. The Si doping concentration doped in the n-type nitride semiconductor layer 25 may be 5E17 / cm 3 to 5E19 / cm 3. The n-type nitride semiconductor layer 25 may be grown under a growth pressure of 150 Torr to 200 Torr at 1000 ° C. to 1200 ° C. (eg, 1050 ° C. to 1100 ° C.) by supplying a metal source gas into the chamber using a MOCVD technique. In this case, the n-type nitride semiconductor layer 25 may be continuously formed on the buffer layer 23, and the actual potential D formed in the buffer layer 23 may be transferred to the n-type nitride semiconductor layer 25.

The low temperature growth layer 27 is located above the n-type nitride semiconductor layer 25. In an embodiment of the present invention, the low temperature growth layer 27 may have a structure in which one or more AlInGaN layers 27a and one or more AlGaN layers 27b are alternately stacked. At this time, the stacking number should be as much as possible, but it is better to stack so that the luminance intensity of the nitride light emitting diode does not decrease.

The low temperature growth layer 27 may be grown at a relatively lower temperature than the n-type nitride semiconductor layer 25. In one embodiment of the present invention, the low temperature growth layer 27 may be grown at a temperature of about 900 ℃. Thus, the low temperature growth layer 27 is grown at a relatively lower temperature than the n-type nitride semiconductor layer 25, thereby artificially lowering the crystal quality and promoting three-dimensional growth to the nucleus of the V-pit (V). As a result, the size of the V-pits V generated in the active layer 33 can be artificially increased.

In addition, in order to increase the size of the V-pit V more efficiently, the lattice constant may be relatively larger than that of the n-type nitride semiconductor layer 25. For example, the low temperature growth layer 27 may be formed by containing In. That is, as described above, the AlInGaN layer 27a is included in the low temperature growth layer 27. When In is contained, the low temperature growth layer 27 has a lattice constant difference between the n-type nitride semiconductor layer 25 and the phenomenon that negative defects of the real potential D are radiated in a V-pit (V) shape. This speeds up the interface of the V-pit V and makes the V-pit V larger in size. InGaN or InAlN may be used in addition to AlInGaN.

The active layer 33 is positioned on the upper portion of the low temperature growth layer 27, and in one embodiment of the present invention, a superlattice layer 29 may be formed between the low temperature growth layer 27 and the active layer 33. have. The superlattice layer 29 may be implemented with InGaN / InGaN. Further, the V-pit (V) diffusion is accelerated due to the difference between the average lattice constant of the superlattice layer 29 and the lattice constant of the lower low temperature growth layer 27 and the n-type nitride semiconductor layer 25.

For example, the lattice constant of the low temperature growth layer 27 may be the smallest, the average lattice constant of the superlattice layer 29 may be an intermediate value, and the lattice constant of the active layer 33 may be the largest. Accordingly, the compressive strain is continuously given to the V-pits V, thereby increasing the size of the V-pits V. FIG. As another example, the cold growth layer 27 may have the smallest constant, the average lattice constant of the superlattice layer 29, and the lattice constant of the active layer 33 may have an intermediate value. Since the magnification of the V-pit (V) is proportional to the difference in the average lattice constant between the superlattice layer 29 and the low temperature growth layer 27 and the thickness of the superlattice layer 29, the V-pit (V) can be further expanded. However, when the lattice constant difference between the superlattice layer 29 and the active layer 33 is large, the piezoelectric field increases in the inner quantum well layer of the active layer 33 due to an electron hole polarization phenomenon (quantum confined stark effect). Since the internal quantum efficiency of the active layer 33 may be lowered, an appropriate thickness and composition ratio are required for the superlattice layer 29. In an embodiment of the present invention, the average thickness of the superlattice layer 29 may be about 70 nm to 100 nm, and InGaN may have a composition ratio of 5% to 10%. In addition, the composition ratio of the well layer in the active layer 33 may be an InGaN layer having In of 10% to 20%. In composition ratio of the low temperature growth layer 27 may be 5% or less. As the composition ratio of In is higher than that of the lower layer, the upper layer is subjected to compressive strain, and thus the V-pit (V) may be gradually diffused.

The active layer 33 emits light having a predetermined energy by recombination of electrons and holes. The active layer 33 may have a single quantum well structure or a multi-quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately stacked. The quantum barrier layer may be formed of a nitride semiconductor layer such as GaN, InGaN, AlGaN, or AlInGaN having a wider band gap than the quantum well layer. In one embodiment, the quantum barrier layer may be formed of AlInGaN to improve the recombination efficiency of the carrier.

The quantum well layer may be formed of a nitride semiconductor layer having a narrower band gap than the quantum barrier layer. For example, the quantum well layer may be formed of a gallium nitride based semiconductor layer such as InGaN, and the composition ratio for band gap control may be determined by a desired light wavelength. Can be. The active layer 33 may be in contact with the low temperature growth layer 27, and as in the present invention, the superlattice layer 29 may be interposed, or the current dispersion between the active layer 33 and the low temperature growth layer 27. A layer may be interposed.

The quantum barrier layer and the quantum well layer of the active layer 33 may be formed of an undoped layer which is not doped with impurities in order to improve the crystal quality of the active layer 33. This may be doped.

As described above, when the quantum barrier layer of the active layer 33 is formed of AlInGaN, the V-pit V may be formed on the upper surface of the actual potential D. The V-pit V may be formed in an inverted hexagonal pyramid shape, and the size of the V-pit V may be larger depending on the location of the low temperature growth layer 27 and the composition ratio and thickness of the superlattice layer 29. Can be. At this time, the superlattice layer 29 and the active layer 33 grow as V- is grown due to strain due to the lattice constant difference between the superlattice layer 29 formed of InGaN / InGaN and the active layer 33 formed of AlInGaN. The pit V is formed continuously and may be formed larger by the influence of the low temperature growth layer 27.

Even if the low temperature growth layer 27 is not interposed between the n-type nitride semiconductor layer 25 and the superlattice layer 29, V-pits V may be formed in the active layer 33. However, the size of the V-pit (V) at this time may be formed to 100nm or less. On the other hand, as in an embodiment of the present invention, by controlling the content of In included in the low temperature growth layer 27 while the low temperature growth layer 27 is interposed, the size of the V-pit (V) may be increased by 100 nm or more. It can be formed up to 200nm in size. In addition, the interface can be more certain. Here, the size of the V-pit V means the maximum width of the width.

V-pits (V) are formed over the superlattice layer 29 and the active layer 33, as the case may be. It may be formed to a depth up to the top of the low temperature growth layer 27.

In one embodiment of the present invention, a high concentration barrier layer 31 doped with high Si may be interposed at the starting point at which the active layer 33 is grown. The high concentration barrier layer 31 can be grown quickly to achieve higher Si doping, can contain In or Al to improve the horizontal dispersion of electrons, and Si can be doped at 1E19 / cm 3 or more and 5E19 / cm 3 or less. have. At this time, the thickness of the high concentration barrier layer 31 is preferably formed to 10nm or more in consideration of the horizontal dispersion effect of the electrons. In addition, a lightly doped layer 30 may be interposed between the high concentration barrier layer 31 and the n-type nitride semiconductor layer 25. The superlattice layer 29 interposed between the high concentration barrier layer 31 and the n-type nitride semiconductor layer 25 may be lightly doped. Thus, by forming a low concentration layer between the high concentration layer, it is possible to form a capacitor (capacitor) in the interior to improve the electrostatic discharge characteristics. In this case, the doping concentration of the lightly doped superlattice layer 29 may be equal to or lower than the doping concentration of the lightly doped layer 30.

In addition, although not shown in the figure, the high concentration barrier layer 31 is disposed between the lightly doped layer 30 and the lightly doped superlattice layer 29 and between the lightly doped superlattice layer 29 and the active layer 33, respectively. By interposing, the some internal capacitor can be formed in series. Thus, by forming a plurality of low concentration layers between the high concentration layers and connecting the capacitors in series, the capacitance can be improved while facilitating the injection of the active layer 33 of electrons when a forward voltage is applied.

Meanwhile, the V-pit V may be formed from the low temperature growth layer 27 to cross the high concentration barrier layer 31, the low concentration doping layer 30, and the active layer 33. Accordingly, the high-concentration barrier layer 31 is formed in a three-dimensional shape in which the V-pit V is formed, rather than a layered two-dimensional structure, as compared with the prior art in which no or small V-pits V are formed. Due to the high concentration of the barrier layer 31 formed in the three-dimensional shape as the size of the V-pit (V) increases the horizontal area of the high concentration barrier layer 31 increases the capacity of the capacitor, according to the increased capacity of the capacitor Electrostatic discharge characteristics can be further improved. In this case, as the V-pit (V) is formed, the area of the high concentration barrier layer 31 may be increased by 2 to 23% than when the V-pit is not formed.

If only the high concentration Si-doped high concentration barrier layer 31 is interposed without the low temperature growth layer 27 interposed therebetween, a very low density and small V-pit (V) is formed, and in this case, electrostatic discharge is improved. It is effective. Therefore, by forming the low temperature growth layer 27 to increase the size of the V-pit (V) and intervening the high concentration barrier layer 31, the leakage current through the real potential (D) is effectively blocked due to this. Electrostatic discharge characteristics can be improved.

On the other hand, after the low temperature growth layer 27 is grown, there may be an annealing (annealing) process. Annealing is performed by increasing the temperature to about 1050 ℃ after the low temperature growth layer 27 is grown, and lowering the temperature. If there is an annealing process, as shown in FIG. 2, the starting point at which the V-pit V is generated is formed on the low temperature growth layer 27, but if the annealing process is omitted, as shown in FIG. Pits (V) starting point can be formed to descend to the low temperature growth layer (27). Therefore, by adjusting the maximum temperature and the fall time of the annealing process, it is possible to finely control the size of the V-pit (V) than to adjust by using the composition ratio or thickness of the superlattice layer (29).

Therefore, the annealing process may be added or omitted as a process for adjusting the size of the V-pit (V).

The high resistance fill layer 37 may be formed to be in contact with the active layer 33, but in one embodiment of the present invention, the electron blocking layers EBL and 35 may be formed between the active layer 33 and the high resistance fill layer 37. Located. The electron block layer 35 may be formed of AlGaN or AlInGaN, and may be formed of AlInGaN to mitigate lattice mismatch with the active layer 33. In this case, the electron block layer 35 may contain about 25% of Al, and may be doped with P-type impurities such as Mg, but may not be intentionally doped. In an embodiment of the present invention, the electron block layer 35 may be formed to a thickness of about 20 nm to 25 nm.

The electron block layer 35 is positioned on the active layer 33 to fill a part of the V-pit V formed over the active layer 33 and the superlattice layer 29. That is, the electron block layer 35 covers the upper surface of the active layer 33 and the surface of the V-pit V. The electron block layer 35 fills only a part of the V-pits V because the electron block layer 35 is not formed to a thickness sufficient to fill all of the V-pits V formed over the active layer 33 and the superlattice layer 29.

The high resistance filling layer 37 is positioned on the electron block layer 35. The high resistance filling layer 37 fills all of the V-pits V not filled by the electron blocking layer 35 and is positioned on the electron blocking layer 35. Therefore, by blocking the high potential filling layer 37 from acting as a path for leakage current, the electrostatic discharge characteristics of the nitride light emitting diode of the present invention can be improved.

In addition, since the V-pit (V) is not filled with the p-type nitride semiconductor layer 39 but filled with the high-resistance filling layer 37, the specific resistance of the V-pit (V) inner region is higher than that of the p-type nitride semiconductor layer. Grows

In particular, the high resistance fill layer 37 may be formed of AlGaN containing Al. By filling the V-pit (V) with the high resistive filling layer 37 containing Al, the specific resistance of the region inside the V-pit (V) can be further lowered, so that the actual potential (D) is a path of the leakage current. You can block it from working.

The p-type nitride semiconductor layer 39 may be formed of a semiconductor layer doped with p-type impurities such as Mg. The p-type nitride semiconductor layer 39 may be a single layer or multiple layers, and may include a p-type cladding layer and a p-type contact layer. In addition, a transparent electrode such as ITO may be positioned on the p-type nitride semiconductor layer 39. Meanwhile, the p-type nitride semiconductor layer 39, the high resistance filling layer 37, the active layer 33, and the low temperature growth layer 27 are partially removed to form an electrode on the exposed n-type nitride semiconductor layer 25. Can be. As a result, an electrode formed on the n-type nitride semiconductor layer 25 is formed as a second electrode 45 on the first electrode 43 and the transparent electrode 41 formed on the p-type nitride semiconductor layer 39 to form a light emitting diode. Can be completed.

4 is a TEM picture of a nitride semiconductor device according to an embodiment of the present invention, Figure 5 is a TEM picture of a conventional nitride semiconductor device.

As shown in FIG. 4, when the size of the V-pit (V) formed in the nitride light emitting diode according to the exemplary embodiment of the present invention, the maximum width of the V-pit (V) width is represented by about 191 nm, and the depth is It can be seen that it is about 153nm. Referring to FIG. 5, the V-pits V formed in the conventional nitride light emitting diode in a state in which the low temperature growth layer 27 is not interposed can be confirmed. Therefore, it can be seen that the size of the V-pit (V) formed in the nitride light emitting diode of the present invention with the low temperature growth layer 27 formed is larger than that of the prior art.

6 is a partial cross-sectional view for describing a nitride semiconductor device according to another exemplary embodiment of the present invention.

While explaining another embodiment of the present invention described above, the same description as the embodiment is omitted, and the same reference numerals may be used for the same configuration.

In another embodiment of the present invention, the nitride semiconductor device does not grow the V-pit V formed by filling the high resistance filling layer 37 and applies the p-type nitride semiconductor layer to the high resistance filling layer 37. . Al may be added to increase the resistance of the high resistance filling layer 37.

The process of using the p-type nitride semiconductor layer to fill the V-pit V into the high resistance filling layer 37 is described in more detail as follows. The growth of the electron block layer 35 takes place prior to filling using the p-type nitride semiconductor layer in the V-pit (V). In another embodiment of the present invention, the electron block layer 35 is not formed in the V-pit V, unlike in the exemplary embodiment, and may be formed along the V-pit V as shown in FIG. 6. have. That is, in another embodiment of the present invention, the electron block layer 35 may be formed on the active layer 33 along the V-pit (V).

Here, although only the active layer 33 is shown in the drawing shown in FIG. 6, as in the exemplary embodiment of the present invention, the superlattice layer 29 and the high concentration barrier layer 31 may be formed together.

FIG. 7 is a flowchart illustrating a process for forming a high resistance filling layer in a V-pit of a nitride semiconductor device according to another exemplary embodiment of the present invention. The high resistance filling layer is formed by using a u-AlGaN and a p-type nitride semiconductor layer. It is a flowchart which shows the process of forming a process. 8 is a partial cross-sectional view showing a high resistance filling layer in a V-pit of a nitride semiconductor device according to another exemplary embodiment of the present invention.

Referring to FIGS. 7 and 8, the undoped layer 37a is grown by 30 to 40 nm, and the p-type nitride semiconductor layer 37b is grown by 3 to 5 nm. Then, the undoped layer 37a and the p-type nitride semiconductor layer 37b serving as the doped layer are grown in order. In another embodiment of the present invention, the undoped layer 37a and the p-type nitride semiconductor layer 37b are sequentially grown in three cycles. As such, hole injection may be improved by periodically repeating growth of the undoped layer 37a and the p-type nitride semiconductor layer 37b. The undoped layer 37a and the p-type nitride semiconductor layer 37b are grown in three cycles in turn, and then the undoped layer 37a is formed thick so that the high resistance filling layer 37 fills the V-pit V to planarize. can do.

In one embodiment of the present invention, the density of the V-pit (V) may be 1E8cm ^-1 to 5E8cm ^-1 , and the size of the V-pit (V) may be 100nm to 200nm. When the area of the V-pit V is calculated using this, the area of the V-pit V may be 2 to 23% of the total area, and the hole injection efficiency may be improved accordingly. The improvement of the hole injection efficiency is not only applied to the high resistance filling layer 37 but also to the high concentration barrier layer 31.

In this case, TMGa shown in FIG. 7 is a Ga source, and TMAl may be used as a source of Al. And Cp2Mg can be used as a source of Mg.

9 is a graph showing the electrostatic discharge characteristics of a nitride semiconductor device according to another embodiment of the present invention.

In order to measure the electrostatic discharge characteristics, 3 kV of reverse and forward voltages were sequentially applied to the plurality of nitride semiconductor devices three times each, and the leakage current of the total number of nitride semiconductor devices before and after application was -5V and 1uA or less. The number was defined as the yield.

As described above, according to another embodiment of the present invention it can be seen that the electrostatic discharge yield is improved compared to the conventional. That is, when the electrostatic discharge failure rate of the conventional nitride semiconductor device is 1 to 3%, it can be seen that the electrostatic discharge failure rate of the nitride semiconductor device according to another embodiment of the present invention is improved to 0 ~ 1.5% level compared to the conventional. . When the nitride semiconductor device is thus more resistant to electrostatic discharge, it is possible to prevent the light emitting device from being damaged by static electricity generated by a machine or a person.

As described above, the detailed description of the present invention has been made by the embodiments with reference to the accompanying drawings. However, since the above description has only been described with reference to the embodiments of the present invention, it is understood that the present invention is limited to the above embodiments. It should not be understood that the scope of the present invention will be understood by the claims and equivalent concepts described below.

21: substrate 23: buffer layer
25: n-type nitride semiconductor layer 27: low temperature growth layer
29: superlattice layer 30: lightly doped layer
31: high concentration barrier layer 33: active layer
35: electron blocking layer 37: high resistance filling layer
39: p-type nitride semiconductor layer 41: transparent electrode
43: first electrode 45: second electrode
D: actual potential V: V-feet

Claims (14)

an n-type nitride semiconductor layer;
A superlattice layer on the n-type nitride semiconductor layer;
A lightly doped layer positioned on the superlattice layer;
A high concentration barrier layer positioned on the low concentration doping layer and doped with a higher concentration of Si than the low concentration doping layer;
An active layer positioned on the high concentration barrier layer; And
It includes a p-type nitride semiconductor layer located on top of the active layer,
The doping concentration of the low concentration doping layer is lower than that of the high concentration barrier layer and the n-type nitride semiconductor layer,
And a V-pit over the superlattice layer, the low concentration doping layer, the high concentration barrier layer, and the active layer. The method according to claim 1,
The nitride semiconductor device having a concentration of Si doped in the high concentration barrier layer is 1E19 / cm 3 or more and 5E19 / cm 3 or less. The method according to claim 1,
Located at the top of the n-type nitride semiconductor layer, further comprising a low temperature growth layer grown at a lower temperature than the n-type nitride semiconductor layer,
The superlattice layer is a nitride semiconductor device located on the cold growth layer. The method according to claim 1,
And a doping concentration of the superlattice layer less than or equal to the doping concentration of the lightly doped layer. The method according to claim 1,
And a V-pit formed across the high concentration barrier layer such that the high concentration barrier layer has a three-dimensional shape. The method according to claim 1,
And a high resistance fill layer interposed between the active layer and the p-type nitride semiconductor layer and filling the V-pit. The method according to claim 6,
And an electron block layer disposed between the active layer and the high resistance filling layer and filling a portion of the V-pit.
The high resistance filling layer fills the remaining portion of the V-pit. The method according to claim 3,
The low temperature growth layer is a nitride semiconductor device grown at a temperature of 900 degrees or less. Forming an n-type nitride semiconductor layer on the substrate;
Forming a superlattice layer on the n-type nitride semiconductor layer;
Forming a lightly doped layer in which Si is lightly doped than the n-type nitride semiconductor layer on the superlattice layer;
Forming a high concentration barrier layer doped with Si on the low concentration doping layer at a higher concentration than the low concentration doping layer;
Forming an active layer having a V-pit formed across said superlattice layer, a lightly doped layer, and a high barrier layer and a top surface surrounding said V-pit; And
Forming a p-type nitride semiconductor layer on the active layer;
The superlattice layer is a nitride semiconductor device manufacturing method for forming the active layer growth. The method according to claim 9,
And a concentration of Si doped in the high concentration barrier layer is 1E19 / cm 3 or more and 5E19 / cm 3 or less. The method according to claim 9,
Forming a low temperature growth layer at a lower temperature than the n-type nitride semiconductor layer on the n-type nitride semiconductor layer,
The superlattice layer is formed on the low temperature growth layer. The method according to claim 11,
The n-type nitride semiconductor layer is formed at 1000 ℃ to 1200 ℃,
The low temperature growth layer is a nitride semiconductor device manufacturing method formed at 900 ℃ or less. The method according to claim 9,
And a doping concentration of the superlattice layer less than or equal to the doping concentration of the lightly doped layer. The method according to claim 9,
And forming a high resistance fill layer filling the V-pit between the forming of the active layer and the forming of the p-type nitride semiconductor layer.

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