KR20140120681A - Nitride semiconductor device having improved esd characteristics - Google Patents

Nitride semiconductor device having improved esd characteristics Download PDF

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KR20140120681A
KR20140120681A KR20130036840A KR20130036840A KR20140120681A KR 20140120681 A KR20140120681 A KR 20140120681A KR 20130036840 A KR20130036840 A KR 20130036840A KR 20130036840 A KR20130036840 A KR 20130036840A KR 20140120681 A KR20140120681 A KR 20140120681A
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layer
semiconductor layer
pit
nitride semiconductor
nitride
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KR20130036840A
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Korean (ko)
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문수영
김은진
김재헌
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서울바이오시스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape

Abstract

Disclosed are a nitride semiconductor device having improved ESD characteristics and a manufacturing method thereof. The nitride semiconductor device includes a n-type contact layer of nitride series; a V-pit generation layer of nitride series which is located on the n-type contact layer and has a V-pit and an upper surface surrounding the V-pit; a low resistance nitride semiconductor layer which covers the V-pit generation layer and has a larger thickness on an upper surface surrounding the V-fit compared to the inner part of the V-fit; a high resistance nitride semiconductor layer which is formed on the low resistance nitride semiconductor layer and fills the V-pit; a p-type contact layer located on the high resistance nitride semiconductor layer; and an active layer located between the resistance nitride semiconductor layer and a p-type contact layer. Here, the low resistance nitride semiconductor layer has a higher impurity concentration compared to the V-pit generation layer. The high resistance nitride semiconductor layer has a lower impurity concentration compared to the V-pit generation layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a nitride semiconductor device having improved electrostatic discharge characteristics, and a nitride semiconductor device having improved electrostatic discharge characteristics,

The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device having improved electrostatic discharge characteristics.

AlGaInN-based nitride semiconductors are widely used as ultraviolet light, blue / green light emitting diodes or laser diodes as light sources for full color displays, traffic lights, general illumination and optical communication devices, and heterojunction bipolar transistors (HBT) and high electron mobility transistors (HEMT).

In general, nitride semiconductors are grown on a substrate such as sapphire, silicon carbide, or silicon, where lattice mismatch occurs, since it is difficult to obtain a lattice-matched substrate. Accordingly, the nitride semiconductor layer grown on the substrates was about 1E9 / cm 2 or more above the extremely high density public performance: has the (threading dislocation density TDD).

The actual potential provides an electron trap site to induce non-luminescent recombination, and also provides a current leakage path. Accordingly, when an overvoltage such as static electricity is applied to the semiconductor device, the current is concentrated through the actual potential and damage due to the electrostatic discharge occurs.

Because of the poor electrostatic discharge characteristics of the nitride semiconductor device, a zener diode is usually used with the nitride semiconductor device. However, zener diodes are relatively expensive and also require a process and space for mounting zener diodes.

On the other hand, although a substrate which is lattice-matched with a nitride semiconductor such as a GaN substrate can be used, the manufacturing cost of the GaN substrate is extremely high, and there is a limit to apply it except for a specific device such as a laser.

On the other hand, in order to improve the electrostatic discharge characteristics of the nitride light emitting device, a nitride semiconductor layer having V-pits is grown in the active layer by adjusting the growth temperature, and then, the p-type contact layer is grown at a high temperature, Technology. This technique improves the electrostatic discharge characteristics by forming a potential barrier for the implanted carrier by the V-pits formed in the active layer. However, since the V-pit penetrates the active layer, there is a problem that the light emitting area of the active layer decreases. Also, since the p-type contact layer for filling the V-pit has little growth margin, can do.

SUMMARY OF THE INVENTION The present invention provides a nitride semiconductor device having improved electrostatic discharge characteristics and a method of manufacturing the same.

Another problem to be solved by the present invention is to improve the electrostatic discharge characteristics of the nitride semiconductor device while preventing the reduction of the light emission area due to the V-pit.

Another object of the present invention is to provide a light emitting diode having improved luminous efficiency and a method of manufacturing the same.

A semiconductor device according to one aspect of the present invention includes: a nitride-based n-type contact layer; A V-pit formation layer on the n-type contact layer, the V-pit formation layer having a V-pit and a top surface surrounding the V-pit; A low-resistance nitride semiconductor layer overlying the V-pit formation layer, the low-resistance nitride semiconductor layer having a greater thickness on an upper surface surrounding the V-pit than within the V-pit; A high-resistance nitride semiconductor layer located on the low-resistance nitride semiconductor layer and filling the V-pit; A nitride-based p-type contact layer located on the high-resistance nitride semiconductor layer; And an active layer positioned between the high-resistance nitride semiconductor layer and the p-type contact layer. Here, the low-resistance nitride semiconductor layer has a higher impurity concentration than the V-pit generating layer, and the high-resistance nitride semiconductor layer has a lower impurity concentration than the V-pit generating layer.

The V-pit is located on the path through which the actual potential is transferred. By using the low-resistance nitride semiconductor layer and the high-resistance nitride semiconductor layer, it is possible to prevent the leakage current through the actual potential and to prevent the semiconductor element from being broken due to the abrupt high voltage applied from the outside, Discharge characteristics.

The nitride semiconductor device may be a light emitting diode, but is not limited thereto, and may be a semiconductor device such as HBT or HEMT.

The nitride semiconductor device may further include a nitride-based current dispersion layer disposed between the high-resistance nitride semiconductor layer and the active layer and for dispersing an electric current. The current-spreading layer may be a nitride-based semiconductor layer having a Si doping concentration in the range of 1E19 to 4E19 / cm3, a nitride-based semiconductor layer for forming a 2DEG, or a nitride-based semiconductor layer having a superlattice structure. The current can be widely dispersed by the current dispersion layer, and thus the luminous efficiency of the light emitting diode can be improved.

On the other hand, the low-resistance nitride semiconductor layer may have a Si doping concentration within a range of 1E19 to 4E19 / cm3. Since the low-resistance nitride semiconductor layer has a thickness different from the inside and the outside of the V-pit, the current flow through the inside of the V-pit can be prevented as the resistivity of the low-resistance nitride semiconductor layer is lowered.

On the other hand, the high-resistance nitride semiconductor layer may be formed of an undoped nitride which is not intentionally doped with impurities or a low-doped nitride doped with a relatively low impurity. Since the high-resistance nitride semiconductor layer is thicker inside than outside of the V-pit, the higher the resistivity of the high-resistance nitride semiconductor layer, the more the current flow through the V-pit can be prevented.

In some embodiments, the p-type contact layer may include SiN nanoparticles therein. The SiN nanoparticles may be located on a practical potential, thus preventing the transfer of the actual potential. Furthermore, SiN nanoparticles improve light extraction efficiency of light emitting diodes by scattering light.

The p-type contact layer includes a lower p-type nitride-based semiconductor layer, an upper p-type nitride-based semiconductor layer, and a middle p-type nitride-based semiconductor layer located between the lower p- The SiN nanoparticles may include lower nano particles located on the lower p-type nitride based semiconductor layer and upper nano particles located on the middle p-type nitride based semiconductor layer.

The lower end of the V-pit may be located on the upper surface of the n-type contact layer. The deeper the V-pit is, the higher the resistance inside the V-pit is, and the current flow through the actual potential can be better prevented.

The nitride semiconductor device may further include a substrate. In some embodiments, the substrate may be located below the n-type contact layer. The substrate may be a growth substrate of nitride-based semiconductor layers including the n-type contact layer. In other embodiments, the substrate may be located above the p-type contact layer.

The nitride semiconductor device may further include an n-electrode electrically connected directly to the n-type contact layer.

The V-pit generation layer, the low-resistance nitride semiconductor layer, and the high-resistance nitride semiconductor layer may all be gallium nitride compound semiconductor layers having the same composition, for example, a GaN layer, but are not limited thereto.

According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a nitride-based n-type contact layer on a substrate; forming a V-pit on the n-type contact layer and a top surface surrounding the V- Pit formation layer on the V-pit formation layer, wherein the low-resistance nitride semiconductor layer is formed on the V-pit formation layer, Forming a high-resistance nitride semiconductor layer having a larger thickness on the upper surface, filling the V-pit, forming an active layer on the high-resistance nitride semiconductor layer, and forming a nitride-based p-type contact layer on the active layer . Here, the low-resistance nitride semiconductor layer has a higher impurity concentration than the V-pit formation layer, and the high-resistance nitride semiconductor layer has a lower impurity concentration than the V-pit formation layer. By forming the low-resistance nitride semiconductor layer and the high-resistance nitride semiconductor layer on the V-pit generating layer, it is possible to prevent current leakage through the actual potential. Furthermore, the V-pit generation layer, the low-resistance nitride semiconductor layer, and the high-resistance nitride semiconductor layer can all be in-situ with a nitride semiconductor layer.

The V-pit formation layer may be grown at a lower growth temperature and / or a higher growth pressure than the n-type contact layer. For example, the n-type contact layer may be grown at a temperature in the range of 1050 to 1100 ° C, and the V-pit formation layer may be grown at a temperature in the range of 900 to 1050 ° C. Also, the n-type contact layer may be grown at a growth pressure of 150 to 200 Torr, and the V-pit formation layer may be grown at a growth pressure of 300 to 500 Torr.

In addition, In may be contained before or during growth of the V-pit formation layer to form the V-pit formation layer. When an In source gas such as TMIn is flowed while a nitride semiconductor layer such as gallium nitride is grown, In, which is relatively larger than Ga or N, is placed on the actual electric field to help the V-pit generation.

The V-pit generation layer may be formed by adjusting the wafer carrier rotation speed. Specifically, the V-pit generating layer may be grown at a wafer carrier rotational speed that is slower than the rotational speed of the wafer carrier during growth of the n-type contact layer.

The high-resistance nitride semiconductor layer may be formed to be equal to or thicker than the V-pit generating layer. Accordingly, the high-resistance nitride semiconductor layer can sufficiently fill the V-pit and have a flat upper surface.

The nitride semiconductor device manufacturing method may further include forming a nitride-based current dispersion layer for dispersing an electric current on the high-resistance nitride semiconductor layer before forming the active layer. The current-spreading layer may be formed of a nitride-based semiconductor layer or a superlattice-structure nitride-based semiconductor layer for forming a nitride-based semiconductor layer or a two-dimensional electron gas (2DEG) layer having low resistivity by doping with impurities.

In some embodiments, the p-type semiconductor layer may include SiN nanoparticles therein. The SiN nanoparticles may be formed in situ with the p-type semiconductor layer.

According to the present invention, by forming the low-resistance nitride-based semiconductor layer and the high-resistance nitride-based semiconductor layer on the V-pit generating layer, current flow through the actual potential can be suppressed, Can be provided. Furthermore, by growing the nitride semiconductor layer having the V-pit and the nitride semiconductor layer covering the V-pit by controlling the growth temperature of the nitride semiconductor, the semiconductor layers can be continuously grown by the in-situ process. Furthermore, by forming SiN nanoparticles in the p-type contact layer, it is possible to block the transfer of the actual potential and to scatter light, thereby improving the luminous efficiency.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
2 is a partial enlarged cross-sectional view of FIG. 1 for explaining a semiconductor device according to an embodiment of the present invention.
3 is a partially enlarged cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.
4 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of constituent elements can be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a partially enlarged cross-sectional view of FIG. 1 illustrating a semiconductor device according to an embodiment of the present invention. Here, a nitride light emitting diode will be described as an example of a semiconductor device.

Referring to FIG. 1, the light emitting diode includes a substrate 21, a buffer layer 23, an n-type contact layer 25, a V-pit generation layer 27, a low-resistance nitride semiconductor layer 28, The current spreading layer 31, the superlattice layer 33, the active layer 35, the p-type contact layer 39, the transparent electrode 41, the first electrode 43 and the second electrode 45 ).

The substrate 21 is a substrate for growing a gallium nitride-based semiconductor layer, and is not particularly limited to sapphire, SiC, Si, spinel, or the like. The substrate 21 is a heterogeneous substrate which lattice mismatches with the semiconductor layer to be grown thereon.

The buffer layer 23 typically includes a low-temperature buffer layer (a nucleus layer) and a high-temperature buffer layer. The low-temperature buffer layer may be formed of (Al, Ga) N on the substrate 21 at a low temperature of 400 to 600 ° C, preferably GaN or AlN. The low-temperature buffer layer may be formed to a thickness of about 25 nm. The high-temperature buffer layer is a layer for relieving the occurrence of defects such as dislocation between the substrate 21 and the lower n-type semiconductor layer 25, and is grown at a relatively high temperature. The high-temperature buffer layer may be formed of, for example, undoped GaN or n-type doped GaN. During the formation of the buffer layer 23, a real electric potential D is generated due to lattice mismatching between the substrate 21 and the buffer layer 23.

The n-type contact layer 25 is formed of a nitride-based semiconductor layer doped with an n-type impurity, for example, a gallium nitride-based semiconductor layer doped with Si. The n-type contact layer 25 may include a GaN layer, and may be formed as a single layer or a multi-layer. The Si doping concentration of the n-type contact layer 25 may be in the range of 5 × 10 17 / cm 3 to 5 × 10 19 / cm 3. The metal source gas may be supplied into the chamber using the n-type contact layer 25 MOCVD technique and grown under a growth pressure of, for example, 150 to 200 Torr at a temperature of, for example, 1000 ° C to 1200 ° C, preferably 1050 ° C to 1100 ° C .

The n-type contact layer 25 may be continuously formed on the buffer layer 23 and the actual potential D formed in the buffer layer 23 is transferred to the n-type contact layer 25.

The V-pit generation layer 27 is located on the n-type contact layer 25. The lower end of the V-pit of the V-pit generating layer 27 may be located on the n-type contact layer 25. The V-pit generating layer 27 may be grown with a gallium nitride-based semiconductor layer, for example, n-GaN, and may be formed to a thickness of about 100 to 500 nm. The V-pit generating layer 27 may be grown at a lower elevated temperature and / or higher growth pressure than the n-type contact layer 25. For example, the V-pit forming layer 27 is grown in the temperature range of 850 캜 to 1050 캜, preferably 900 캜 to 1050 캜, so that a V-pit V surrounded by a relatively flat upper surface is formed . The growth temperature of the V-pit generation layer 27 may vary depending on the source flow rate and the pressure in the chamber. Also, the V-pit generation layer 27 can be grown under a growth pressure of 300 to 500 Torr. When the nitride semiconductor layer is grown at a relatively low temperature or at a relatively high pressure, the growth rate in the vertical direction is faster than the growth in the horizontal direction, so that the V-pit (V) .

Further, the V-pit generation layer 27 may be grown by adjusting the rotation speed of the wafer carrier in the MOCVD chamber. For example, the V-pit formation layer 27 can be grown at wafer carrier rotational speed conditions relatively slow compared to the growth conditions of the n-type contact layer 25, and can be grown easily at a rotational speed of, for example, 500-1000 rpm .

Further, the V-pit can be easily formed by containing In before or during the formation of the V-pit generating layer 27. In is larger than Ga or N, and is located on the path of the actual potential to help generate V-pits. In can be easily contained by flowing an In source gas such as TMIn into the chamber.

A low-resistance nitride semiconductor layer 28 is located on the V-pit generating layer 27. The low-resistance nitride semiconductor layer 28 may have an impurity concentration higher than that of the V-pit generation layer 27, and thus has a relatively low resistivity. The low-resistance nitride semiconductor layer 28 may be formed of, for example, a GaN layer to a thickness of about 50 to 200 nm, and may have a Si dopant concentration of 1E19 to 4E19 / cm3. Also, the low-resistance nitride semiconductor layer 28 may have a superlattice structure to lower a horizontal resistance than a vertical resistance.

The low-resistance nitride semiconductor layer 28 is formed thicker outside the V-pit than inside the V-pit. The greater the difference in thickness between the inside of the V-pit and the outside of the V-pit, the more current can be prevented through the current. Since the low-resistance nitride semiconductor layer 28 is doped at a high concentration, the crystal quality is deteriorated if the thickness is too large. Thus, the low-resistance nitride semiconductor layer 28 is formed to be thinner than the V-pit generating layer 27 outside the V-pit.

A high-resistance nitride semiconductor layer 29 is located on the low-resistance nitride semiconductor layer 28. The high-resistance nitride semiconductor layer 29 fills the V-pit V of the V-pit formation layer 27 and covers the top of the V-pit formation layer 27. The thickness of the high-resistance nitride semiconductor layer 29 in the V-pit V is thicker than the thickness of the high-resistance nitride semiconductor layer 29 on the upper surface of the V-pit generation layer 27. Further, the high-resistance nitride semiconductor layer 29 has a relatively high resistivity as compared with the V-pit generating layer 27. For example, the high-resistance nitride semiconductor layer 29 has a lower impurity concentration than the V-pit generation layer 27. The high-resistance nitride semiconductor layer 29 may be a low-concentration n-type impurity doped layer compared to the V-pit formation layer 27 or an undoped layer formed without intentional doping of the impurity.

 The high-resistance nitride semiconductor layer 29 may be grown to a thickness of about 100 to 500 nm at a relatively high temperature, for example, 1000 to 1200 ° C, the same as or thicker than the V-pit generation layer 27. As the nitride semiconductor layer 29 grows relatively thick at a high temperature of 1000 占 폚 or higher, the high-resistance nitride semiconductor layer 29 dominates in the horizontal direction to fill the V-pit V and has a relatively flat surface. The high-resistance nitride semiconductor layer 29 may be formed of a gallium nitride-based semiconductor layer having the same composition as that of the V-pit generation layer 27, for example, GaN, but is not limited thereto and may be formed of another nitride semiconductor layer have.

The current-spreading layer 31 may be located on the high-resistance nitride semiconductor layer 29. The current-spreading layer 31 may be a layer for distributing current in the horizontal direction, for example, a nitride semiconductor layer or a two-dimensional transfer gas (2DEG) layer or a superlattice layer doped with a high concentration of impurities. The current-spreading layer 31 may be formed to a thickness of 10 to 200 nm, for example, and in the case of a nitride semiconductor layer doped with a high concentration of impurities, Si impurity within a range of 1E19 to 4E19 / cm3 may be doped. When the current-spreading layer 31 exceeds 200 nm, the light output sharply drops. On the other hand, a superlattice layer 33 may be formed on the current spreading layer 31 to help grow an active layer of good crystal quality.

On the other hand, the active layer 35 is located on the high-resistance nitride semiconductor layer 29. The active layer 35 may have a single quantum well structure or a multiple quantum well structure in which barrier layers and quantum well layers are alternately stacked. The barrier layer may be formed of a gallium nitride-based semiconductor layer having a larger bandgap than the quantum well layer, for example, GaN, InGaN, AlGaN, or AlInGaN. The quantum well layer may be formed of a gallium nitride-based semiconductor layer, for example, InGaN, and the composition ratio of In is determined by a desired light wavelength. The active layer 35 may be in contact with the high-resistance nitride semiconductor layer 29, but the present invention is not limited thereto. The current spreading layer 31 and / or the superlattice layer 30 may be interposed between the active layer 35 and the high-resistance nitride semiconductor layer 29, A layer 33 may be interposed.

The barrier layer and the quantum well layer of the active layer 33 may be formed of an undoped undoped layer to improve the crystal quality of the active layer. However, impurities may be doped in some or all of the active regions to lower the forward voltage It is possible.

A p-type contact layer 39 is located on the active layer 35. The p-type contact layer 39 is formed of a nitride-based semiconductor layer doped with a p-type impurity such as Mg, for example, GaN. The p-type contact layer 39 may be a single layer or a multilayer and may comprise SiN nanoparticles, as described below with reference to FIG. The electron blocking layer 37 may be disposed between the active layer 35 and the p-type contact layer 39.

A transparent electrode 41 such as ITO may be disposed on the p-type contact layer 39. An n-electrode 43 is formed on the exposed n-layer portion by partially removing the p-type contact layer 39 and the active layer 35. A p-electrode 45 is formed on the transparent electrode 41, So that a light emitting diode is completed. The n-electrode 43 may directly contact the n-type contact layer 25, but is not limited thereto.

According to this embodiment, a V-pit generating layer 27 having V-pits V is formed and a low-resistance nitride semiconductor layer 28 and a high-resistance nitride semiconductor layer 28 are formed on the V- The resistance in the vertical direction is relatively higher in the V-pit V than in the outside of the V-pit, so that the current flow through the actual potential can be suppressed and the electrostatic discharge characteristic can be improved have.

According to the present embodiment, both the V-pit generation layer 27, the low-resistance nitride semiconductor layer 28, and the high-resistance nitride semiconductor layer 29 can be grown as a nitride-based semiconductor layer, So that the process can be simplified.

On the other hand, in the case of the light emitting diode in which the V-pit generation layer 27, the low-resistance nitride semiconductor layer 28 and the high-resistance nitride semiconductor layer 29 are added on the n-type contact layer 25, The leakage current failure rate could be reduced from about 56% to about 9%.

3 is a partially enlarged cross-sectional view illustrating a semiconductor device according to another embodiment of the present invention.

3, the semiconductor device according to the present embodiment is substantially similar to the semiconductor device described with reference to FIGS. 1 and 2, except that the p-type contact layer 39 includes SiN nanoparticles 40a and 40b There is a difference.

The SiN nanoparticles 40a and 40b may be formed using an Si source gas and an N source gas in the MOCVD chamber and may thus be formed in situ during formation of the p-type contact layer 39 It is possible to prevent the process from being complicated.

The SiN nano-particles 40a and 40b can be easily formed on the actual potential, and thus the transfer of the actual potential can be prevented. Furthermore, the SiN nanoparticles 40a and 40b improve the light extraction efficiency by scattering the light generated in the active layer 35.

The SiN nanoparticles 40a, 40b may be located at a single level and may be located at a dual level as shown in FIG.

3, the p-type contact layer 39 includes a lower p-type nitride-based semiconductor layer 39a, an upper p-type nitride-based semiconductor layer 39c, and a lower p-type nitride- And a middle p-type nitride-based semiconductor layer 39b located between the upper p-type nitride-based semiconductor layer 39c and the upper p-type nitride-based semiconductor layer 39c. Here, the lower SiN nano particles 40a may be located on the lower p-type nitride based semiconductor layer 39a and the upper SiN nano particles 40b may be located on the middle p-type nitride based semiconductor layer 39b Can be located. In a similar manner, SiN nanoparticles may be located at more levels.

4 is a schematic cross-sectional view illustrating a vertical light emitting diode as a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 4, the semiconductor device according to the present embodiment includes an n-type contact layer 25, a V-pit generation layer 27, and a p-type contact layer 25, similarly to the semiconductor device described with reference to Figs. 1 and 2 or 3 Resistance nitride semiconductor layer 28, high resistance nitride semiconductor layer 29, current spreading layer 31, superlattice layer 33, active layer 35 and p-type contact layer 39, The detailed description of the components is omitted in order to avoid redundancy.

The semiconductor device according to this embodiment may include a reflective metal layer 47, a barrier metal layer 49, a substrate 51, a bonding metal layer 53, and an n-electrode 55.

The substrate 51 is a supporting substrate formed on the p-type contact layer 39, which is distinguished from a growth substrate for growing a semiconductor layer. The substrate 51 may be bonded to the p-type contact layer 39 through the bonding metal layer 53.

On the other hand, the reflective metal layer 47 and the barrier metal layer 49 may be positioned between the substrate 51 and the p-type contact layer 39. The reflective metal layer 47 reflects light traveling from the active layer 35 toward the substrate 51 side to improve luminous efficiency and the barrier metal layer 49 prevents diffusion of metal atoms to protect the reflective metal layer 47. The reflective metal layer 47 and the barrier metal layer 49 may be used as p-electrodes.

On the other hand, the surface of the n-type contact layer 25 may be exposed, and a rough surface R may be formed. In addition, an n-electrode 55 may be formed on the n-type contact layer 25. [

Although the horizontal flat type light emitting diode and the vertical type light emitting diode have been described above by way of example, the present invention is not limited thereto and can be applied to light emitting diodes having various structures such as a flip chip type light emitting diode.

Although the embodiments have been described with reference to light emitting diodes, the spirit of the present invention is not limited to light emitting diodes and may be employed to improve electrostatic discharge characteristics in various devices employing nitride semiconductors, such as HBTs and HEMTs. have. In particular, these semiconductor devices include a nitride based V-pit creation layer 27 having a V-pit and a top surface surrounding the V-pit, Resistant nitride semiconductor layer 28 having a greater thickness on the upper surface surrounding the V-pit than in the low-resistance nitride semiconductor layer 28, and a high-resistance nitride semiconductor layer 28 located on the low- Layer (29).

Claims (21)

A nitride-based n-type contact layer;
A V-pit formation layer on the n-type contact layer, the V-pit formation layer having a V-pit and a top surface surrounding the V-pit;
A low-resistance nitride semiconductor layer overlying the V-pit formation layer, the low-resistance nitride semiconductor layer having a greater thickness on an upper surface surrounding the V-pit than within the V-pit;
A high-resistance nitride semiconductor layer located on the low-resistance nitride semiconductor layer and filling the V-pit;
A nitride-based p-type contact layer located on the high-resistance nitride semiconductor layer; And
And an active layer located between the high-resistance nitride semiconductor layer and the p-type contact layer,
Wherein the low-resistivity nitride semiconductor layer has a higher impurity concentration than the V-pit formation layer, and the high-resistance nitride semiconductor layer has a lower impurity concentration than the V-pit formation layer. The method according to claim 1,
And a nitride-based current-spreading layer located between the high-resistance nitride semiconductor layer and the active layer and for dispersing an electric current. The method of claim 2,
Wherein the current dispersion layer is a nitride based semiconductor layer having a Si doping concentration in a range of 1E19 to 4E19 / cm < 3 > or a nitride based semiconductor layer or a superlattice structure nitride based semiconductor layer for forming a 2DEG. The method according to claim 1,
Wherein the low-resistance nitride semiconductor layer has an Si doping concentration within a range of 1E19 to 4E19 / cm3. The method according to claim 1,
And the high-resistance nitride semiconductor layer is formed of an undoped nitride which is intentionally not doped with impurities. The method according to claim 1,
Wherein the p-type contact layer comprises SiN nanoparticles inside. The method of claim 6,
The p-type contact layer includes a lower p-type nitride-based semiconductor layer, an upper p-type nitride-based semiconductor layer, and a middle p-type nitride-based semiconductor layer located between the lower p- / RTI >
Wherein the SiN nanoparticles include lower nano particles located on the lower p-type nitride based semiconductor layer, and upper nano particles located on the middle p-type nitride based semiconductor layer. The method according to claim 1,
And a lower end of the V-pit is located on an upper surface of the n-type contact layer. The method according to claim 1,
Further comprising a substrate,
Wherein the substrate is located below the n-type contact layer. The method according to claim 1,
Further comprising a substrate, wherein the substrate is located above the p-type contact layer. The method according to claim 9 or 10,
And an n-electrode electrically connected directly to said n-type contact layer. A nitride-based n-type contact layer is formed on a substrate,
Pit formation layer having a V-pit on the n-type contact layer and a top surface surrounding the V-pit,
Forming a low-resistance nitride semiconductor layer on the V-pit formation layer, wherein the low-resistance nitride semiconductor layer has a greater thickness on an upper surface surrounding the V-pit than in the V-pit interior,
Forming a high-resistance nitride semiconductor layer filling the V-pits,
Forming an active layer on the high-resistance nitride semiconductor layer,
And forming a nitride-based p-type contact layer on the active layer,
Wherein the low-resistance nitride semiconductor layer has a higher impurity concentration than the V-pit formation layer, and the high-resistance nitride semiconductor layer has a lower impurity concentration than the V-pit formation layer. The method of claim 12,
Wherein the V-pit formation layer is grown at a lower growth temperature and / or a higher growth pressure than the n-type contact layer. 14. The method of claim 13,
Wherein the n-type contact layer is grown at a temperature in the range of 1050 to 1100 占 폚 and the V-pit formation layer is grown at a temperature within a range of 900 to 1050 占 폚. The method of claim 12,
Further comprising incorporating In prior to or during the growth of the V-pit formation layer to form the V-pit formation layer. 13. The method of claim 12, wherein the V-pit generating layer is grown at a wafer carrier rotational speed that is slower than the rotational speed of the wafer carrier during growth of the n-type contact layer. The method of claim 12,
And the high-resistance nitride semiconductor layer is formed to be equal to or thicker than the V-pit generation layer. The method of claim 12,
And forming a nitride-based current dispersion layer for dispersing a current on the high-resistance nitride semiconductor layer before forming the active layer. The method of claim 12,
Wherein the p-type semiconductor layer includes SiN nanoparticles. 21. The method of claim 19, wherein the SiN nanoparticles are formed in situ with the p-type semiconductor layer. A nitride based V-pit formation layer having a V-pit and an upper surface surrounding the V-pit;
A low-resistance nitride semiconductor layer overlying the V-pit formation layer, the low-resistance nitride semiconductor layer having a greater thickness on an upper surface surrounding the V-pit than within the V-pit; And
And a high-resistance nitride semiconductor layer located on the low-resistance nitride semiconductor layer and filling the V-pit,
Wherein the low-resistivity nitride semiconductor layer has a higher impurity concentration than the V-pit formation layer, and the high-resistance nitride semiconductor layer has a lower impurity concentration than the V-pit formation layer.
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