KR20150118395A - Display device and method of manufacturing the same - Google Patents

Abstract

A display device according to an embodiment of the present invention arranges a substrate including a display unit and a non-display unit, and forms a thin film transistor including an oxide semiconductor layer and a pixel electrode connected to the thin film transistor in the display unit. A panel driving unit including a pad unit transmitting a signal to the thin film transistor or the pixel electrode is arranged in the non-display unit. Additionally, in the non-display unit, a first conductive layer, a second conductive layer and a third conductive layer are formed and a first area where the first conductive layer and the second conductive layer come into contact with each other, and a second area where the second conductive layer and the third conductive layer come into contact with each other are formed. An embodiment of the present invention provides the display device, which makes the first conductive layer, the second conductive layer and the third conductive layer function as a wiring contact unit coming into contact with the pad unit of the panel driving unit and forms the second area, where the second conductive layer comes into contact with the third conductive layer, to be overlapped with the pad unit of the panel driving unit, thereby being capable of increasing a contact area between the wiring contact unit and the pad unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same,

The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device capable of increasing a contact area between a wiring contact portion formed in a non-display portion and a pad portion to facilitate signal transmission, and a method of manufacturing the same .

The display device comprises a display portion for displaying an image and a non-display portion which is a peripheral region of the display portion. The non-display portion is provided with a wiring connected to a panel driving portion for providing a signal to the display portion, and the pad portion of the panel driving portion is connected to the wiring contact portion to supply various signals to the display portion. The panel driver may be a driver IC or a flexible printed circuit (FPC) according to the panel structure.

In general, the wiring and wiring contact portions are formed together in the process of forming the thin film transistor and the pixel electrode on the display portion. That is, when a conductive layer or an insulating layer is deposited on a substrate and then patterned, an insulating layer of a pixel electrode, a thin film transistor, or a thin film transistor is formed on the display portion, and a wiring or wiring contact portion is formed on the non-display portion. Therefore, the lamination structure of the wiring contact portion also changes depending on the type and structure of the thin film transistor. For example, a thin film transistor formed using an amorphous silicon (a-Si) semiconductor layer and an inverted staggered structure will be described in detail. A thin film transistor having an inverted staggered structure is formed by sequentially laminating a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode on a substrate. Further, the source electrode or the drain electrode of the thin film transistor is connected to the pixel electrode through the contact hole of the passivation layer serving as a protective film of the thin film transistor. According to the stacking sequence of this structure, the wiring contact portion of the non-display portion is formed by stacking a conductive layer of the same material as that of the gate electrode and a conductive layer of the same material as that of the pixel electrode in the insulating layers of the same material as the gate insulating layer and the passivation layer The gate insulating layer and the passivation layer may be etched at the same time when forming the contact hole because the same insulating layer material is used for forming the contact hole. In general, the insulating layer material may be silicon nitride (SiN _x ), which is advantageous for insulating properties and moisture barrier.

1. [Flat Panel Display] (Patent Application No. 10-2006-0128418)

In recent years, interest in high image quality and 3D implementation has increased, and a thin film transistor of an oxide semiconductor layer has been attracting attention as a thin film transistor using amorphous silicon as a semiconductor layer. The thin film transistor of the oxide semiconductor layer is advantageous for low power consumption because of high charge mobility and low leakage current compared to the amorphous silicon thin film transistor. In addition, it contributes to the improvement of cross-talk and flicker, which is advantageous in realizing high image quality and fast driving.

However, since the oxide semiconductor layer is sensitive to hydrogen, the material of the insulating layer used in the thin film transistor is limited in order to secure device characteristics. In the case of silicon nitride (SiN x) used as an insulating layer of a conventional amorphous silicon semiconductor layer, since the hydrogen content is high and affects the oxide semiconductor layer, the thin film transistor of the oxide semiconductor layer is formed of an insulating layer It is preferable to use an insulating layer having a low content.

In the structure of the thin film transistor including the oxide semiconductor layer, the structure of the wiring contact portion located in the non-display portion is also affected. The various insulating layers such as the gate insulating layer or the passivation layer located in the wiring contact portion are formed of different materials, so that it is difficult to etch the insulating layer at the time of forming the contact holes. That is, since it is difficult to form the conductive layer of the same material as the gate electrode with the conductive layer of the same material as that of the pixel electrode in one contact hole, a conductive layer of the same material as the source and drain electrodes is provided therebetween, It is necessary to form the contact structure. In other words, the structure of the wiring contact portion located in the non-display portion is such that the conductive layer of the same material as the gate electrode and the conductive layer of the same material as the source and drain electrodes are in contact with each other, And a portion contacting the conductive layer of the same material as the electrode. In this structure, when the area of the pads of the panel driving part is the same, when the thin film transistor of the conventional amorphous silicon is applied, the wiring contact part and the pad part can be brought into contact with one contact hole. On the other hand, when the thin film transistor of the oxide semiconductor layer is applied, at least two contact holes are required to be formed in accordance with the double contact structure, so that the contact area between the wiring contact portion and the pad portion is reduced. As a result, a problem may occur in signal transmission to the display unit due to reduction of the contact resistance, and accordingly, reliability of the display apparatus may be deteriorated due to a defect such as a line defect.

The inventor of the present invention has recognized the above-mentioned problems, and in consideration of the structure of the wiring contact portion located in the non-display portion in the display device using the thin film transistor including the oxide semiconductor layer, the contact between the wiring contact portion and the pad portion A display device of a new structure capable of increasing the area was invented.

A problem to be solved by the present invention is to provide a display device capable of improving the reliability of a display device by improving the contact resistance by increasing the contact area between the wiring contact part and the pad part and further improving the defective screen error will be.

The solution according to an embodiment of the present invention is not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In the display device according to an embodiment of the present invention, a substrate including a display portion and a non-display portion is disposed, and a thin film transistor including an oxide semiconductor layer and a pixel electrode connected to the thin film transistor are formed on the display portion. And a panel driver including a pad portion for transmitting a signal to the thin film transistor or the pixel electrode is disposed on the non-display portion. The first conductive layer, the second conductive layer, and the third conductive layer are formed on the non-display portion, and the first region where the first conductive layer and the second conductive layer are in contact with each other, the second conductive layer, A second region is formed. According to an embodiment of the present invention, the first conductive layer, the second conductive layer, and the third conductive layer function as a wiring contact portion contacting the pad portion of the panel driving portion, and the second conductive layer and the third conductive layer are in contact with each other And the second area is formed so as to overlap with the pad part, thereby increasing the contact area between the wiring contact part and the pad part.

The details of other embodiments are included in the detailed description and drawings.

According to an embodiment of the present invention, in a display device using a thin film transistor including an oxide semiconductor layer, contact resistance between a wiring contact portion and a pad portion located in a non-display portion can be increased, thereby improving contact resistance.

In addition, since signal transmission between the display section and the panel driving section is facilitated, there is an effect that the defective screen error can be reduced.

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

The scope of the claims is not limited by the matters described in the contents of the invention, as the contents of the invention described in the problems, the solutions to the problems and the effects to be solved do not specify essential features of the claims.

1 is a plan view showing a display device according to an embodiment of the present invention.
Figure 2 is a cross-sectional view of portions A and B of Figure 1, according to one embodiment of the present invention.
FIG. 3A is a schematic plan view showing one embodiment of the portion B shown in FIG.
3B is a schematic plan view showing another embodiment of the portion B shown in FIG.
4 is a cross-sectional view of part A and part B of Fig. 1 according to another embodiment of the present invention.
5A is a schematic plan view showing an embodiment of a portion B according to another embodiment of the present invention shown in FIG.
5B is a schematic plan view showing another embodiment of the portion B according to another embodiment of the present invention shown in FIG.
FIG. 6 is a table showing the relationship between the contact area between the wiring contact portion and the pad portion and the defective ratio in the embodiment and the comparative example of the present invention. FIG.
7A to 7D are cross-sectional views showing a manufacturing process of a thin film transistor, a pixel electrode, and a wiring contact portion located in a non-display portion, which are located in a display portion, according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the case where the word 'includes', 'having', 'done', etc. are used in this specification, other parts can be added unless '~ only' is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if a temporal posterior relationship is described by 'after', 'after', 'after', 'before', etc., 'May not be contiguous unless it is used.

In the case of a description of the signal flow relationship, for example, even if 'signal is transmitted from node A to node B' And a case where a signal is transmitted to the B-node.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, a display device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a display device according to an embodiment of the present invention.

Referring to Fig. 1, the display device includes a display portion 100A for displaying an image and a substrate 100 including a non-display portion 100B which is a peripheral region of the display portion 100A.

A non-display portion 100B is formed with a panel driver unit (PDU), a gate driver unit (GDU), and a line (L) for providing signals to the display unit 100A. The panel driver PDU may be a source driver IC or a flexible printed circuit (FPC) according to the panel structure. The gate driver GDU may be a gate driver IC panel (GIP) or a gate driver IC Gate Driver IC).

Although not shown in FIG. 1, a plurality of pixels are formed on a display unit, and a wiring L connected to a panel driving unit PDU and a wiring L connected to a gate driving unit GDU are formed in a matrix, .

Figure 2 is a cross-sectional view of portions A and B of Figure 1, according to one embodiment of the present invention. More specifically, A is a cross-sectional view of a portion A of the display portion 100A of FIG. 1 and a portion B of the non-display portion 100B where the panel driving portion (PDU) and the wiring L are in contact with each other.

Referring to FIG. 2, A which is a part of the display portion 100A of the substrate 100 will be described first.

A thin film transistor TFT and a pixel electrode 170A are formed on the display portion 100A of the substrate 100. [

The thin film transistor TFT is composed of a gate electrode 110A, an intermediate insulating layer 120A, an oxide semiconductor layer 130A, a source electrode 142A and a drain electrode 144A. 2 is a thin film transistor (TFT) having an inverted staggered structure. A gate electrode 110A is formed on a substrate 100, and an intermediate insulating layer 120A is formed on a gate electrode 110A. An oxide semiconductor layer 130A is formed as an active layer on the intermediate insulating layer 120A and a source electrode 142A and a drain electrode 144A are formed on the oxide semiconductor layer 130A.

The gate electrode 110A, the source electrode 142A, and the drain electrode 144A are formed of a conductive material. For example, any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) But it is not limited thereto and may be formed of various materials.

The intermediate insulating layer 120A may be composed of a plurality of insulating layers although not shown in Fig. More specifically, the lower intermediate insulating layer may be formed of a lower intermediate insulating layer formed on the gate electrode 110A and an upper intermediate insulating layer formed on the lower intermediate insulating layer. The upper intermediate insulating layer may be formed in contact with the oxide semiconductor layer 130A have. Since the oxide semiconductor layer 130A is sensitive to hydrogen, when hydrogen flows into the oxide semiconductor layer 130A, the characteristics of the thin film transistor TFT are affected. That is, when hydrogen ions serving as a donor in the oxide semiconductor layer 130A flow into the oxide semiconductor layer 130A of the thin film transistor TFT, the threshold voltage of the thin film transistor TFT shifts, This becomes difficult. For this reason, the upper intermediate insulating layer formed in contact with the oxide semiconductor layer 130A may be composed of an insulating layer having a lower hydrogen content than the lower intermediate insulating layer. For example, the lower intermediate insulating layer is made of silicon nitride (SiN _x ) which is advantageous for preventing moisture permeation and moisture permeation, and the upper intermediate insulating layer formed in contact with the oxide semiconductor layer 130A has a hydrogen content This may be composed of less silicon oxide (SiO _x ).

A pixel electrode 170A connected to a thin film transistor (TFT) is formed on the thin film transistor TFT. The passivation layer 150A and the planarization layer 160A are formed on the source electrode 142A of the thin film transistor TFT and the passivation layer 150A and the contact hole of the planarization layer 160A are formed, The source electrode 142A and the pixel electrode 170A are connected to each other. 2, the source electrode 142A of the thin film transistor TFT is connected to the pixel electrode 170A. However, depending on the type of the thin film transistor TFT, the pixel electrode 170A may be connected to the drain electrode 144A have.

The pixel electrode 170A may be formed of a transparent conductive material such as ITO or IZO, or may be formed of an opaque conductive material such as a metal or a metal alloy.

2, the upper structure of the pixel electrode 170A is not specifically shown, but may be a pixel electrode of a liquid crystal display device or an anode electrode of an organic light emitting display device, depending on the display device.

The passivation layer 150A includes a first passivation layer 152A formed on the source electrode 142A and the drain electrode 144A and in contact with the oxide semiconductor layer 130A and a second passivation layer 152A formed on the planarization layer 160A. 154A. As described above, since the oxide semiconductor layer 130A is sensitive to hydrogen, the first passivation layer 152A contacting the oxide semiconductor layer 130A may be composed of an insulating layer having a hydrogen content lower than that of the second passivation layer 154A. have. For example, the first passivation layer 152A may be composed of silicon oxide (SiO _x ) and the second passivation layer 154A may be composed of silicon nitride (SiN _x ). Although the planarization layer 160A and the second passivation layer 154A are illustrated as being formed on the first passivation layer 152A and the planarization layer 160A in FIG. 2, the first passivation layer 152A may be formed on the first passivation layer 152A. A planarization layer 160A may be formed on the second passivation layer 154A and the second passivation layer 154A.

Referring to FIG. 2, a portion B of the non-display portion 100B of the substrate 100 where the panel driving portion PDU contacts the wiring L will be described as follows.

The first conductive layer 110B, the second conductive layer 140B, and the third conductive layer (not shown), which are part of the wiring line L described in Fig. 1, are formed in the non-display portion 100B of the substrate 100, 170B are formed. More specifically, the wiring L located in the non-display portion is connected to the pad portion 190B of the panel driving portion (PDU) for transmitting a signal to the display portion 100A, and the first conductive layer 110B, And a wiring contact portion 180B composed of a conductive layer 140B and a third conductive layer 170B. The wiring contact portion 180B has a first region in which the first conductive layer 110B and the second conductive layer 140B are in contact with each other and a second region in which the second conductive layer 140B and the third conductive layer 170B are in contact with each other, . A signal is transmitted from the pad portion 190B of the panel driving unit PDU to the second region of the wiring contact portion 180B connected to the pad portion 190B and the transmitted signal is transmitted to the second region of the wiring contact portion 180B (TFT) or pixel electrode 170A of the display portion 100A via the first region.

The first insulating layer 120B is formed between the first conductive layer 110B and the second conductive layer 140B and the first conductive layer 110B and the second conductive layer 120B are formed through the contact holes of the first insulating layer 120B. A first region in which the conductive layer 140B contacts is formed. The second insulating layer 150B is formed between the second conductive layer 140B and the third conductive layer 170B and the second conductive layer 140B is formed through the contact hole of the second insulating layer 150B. A second region in which the third conductive layer 170B contacts is formed.

2, the pad portion 190B and the second region of the wiring contact portion 180B are separated from each other. However, in reality, the pad portion 190B and the second region are formed of an adhesive material such as ACF (Anisotropic Conductive Film) Lt; / RTI > Specifically, the surface of the third conductive layer 170B corresponding to the second region of the wiring contact portion 180B is connected to the pad portion 190B through an adhesive material, and the third conductive layer 170B is connected to the pad portion 190B, and may not be formed on the first region 194B.

The wiring contact portion 180B of the non-display portion 100B is formed at the same time when the thin film transistor TFT and the pixel electrode 170A of the display portion 100A are formed according to the embodiment of the present invention, . This is explained in detail as follows.

Since the first conductive layer 110B is formed simultaneously with the gate electrode 110A when the gate electrode 110A of the thin film transistor TFT is formed, the first conductive layer 110B and the gate electrode 110A are formed of the same material .

More specifically, when a conductive material is deposited on the substrate 100 and then patterned using a mask, a part of the conductive material remaining in the display portion 100A after the patterning becomes the gate electrode 110A, A part of the remaining conductive material may be the first conductive layer 110B. Accordingly, the gate electrode 110A and the first conductive layer 110B may be formed of the same material through the same process.

Similarly, since the source electrode 142A of the thin film transistor TFT or the second conductive layer 140B is formed simultaneously when the drain electrode 144A is formed, the second conductive layer 140B and the source electrode 142A or the drain electrode 144A may be formed of the same material. Since the third conductive layer 170B is simultaneously formed when the pixel electrode 170A is formed, the third conductive layer 170B and the pixel electrode 170A may be formed of the same material.

Similarly, the first insulating layer 120B and the second insulating layer 150B formed in the non-display portion 100B can be formed at the same time when the insulating layer of the display portion 100A is formed, thereby simplifying the process.

That is, since the first insulating layer 120B is formed simultaneously when the intermediate insulating layer 120A of the thin film transistor (TFT) of the display portion 100A is formed, the first insulating layer 120B and the intermediate insulating layer 120A And may be made of the same material.

More specifically, when an insulating material is deposited on the gate electrode 110A and then patterned, a part of the insulating material remaining in the display portion 100A after the patterning becomes the intermediate insulating layer 120A, A part of the remaining insulating material may be the first insulating layer 120B. Accordingly, the intermediate insulating layer 120A and the first insulating layer 120B may be formed of the same material through the same process.

As described above, the intermediate insulating layer 120A may be composed of a plurality of insulating layers. In the case of the insulating layer formed in contact with the oxide semiconductor layer 130A among the plurality of insulating layers, the intermediate insulating layer 120A may be formed of a material having a hydrogen content lower than that of the other insulating layers Lt; / RTI > Likewise, since the first insulating layer 120B proceeds simultaneously through the same process as the intermediate insulating layer 120A, it can be composed of a plurality of insulating layers. The hydrogen content of one of the plurality of insulating layers may be made smaller than the hydrogen content of the other insulating layer.

Similarly, since the second insulating layer 150B is simultaneously formed when the passivation layer 150A of the display portion 100A is formed, the second insulating layer 150B and the passivation layer 150A may be formed of the same material. Since the passivation layer 150A is formed of the first passivation layer 152A and the second passivation layer 154A as described above, the second insulating layer 150B may be formed of a plurality of the insulating layers 152B and 154B. have. More specifically, a plurality of insulating layers 152B and 154B are formed with contact holes for forming a second region in which the second conductive layer 140B and the third conductive layer 170B are in contact with each other. The side inclination angle of the contact hole of one of the insulating layers 152A and 154B and the side inclination angle of the other insulating layer 154B may be formed to be different from each other.

More specifically, the insulating layer 152B formed of the same material as the first passivation layer 152A is formed of a material having a hydrogen content lower than that of the insulating layer 154B formed of the same material as the second passivation layer 154B . In other words, since the plurality of insulating layers 152B and 154B are formed of different materials, contact holes are formed through respective etching processes. At this time, due to the difference in etchant and process conditions depending on the material of the insulating layer A difference occurs in the side inclination angle of the contact hole.

For example, the insulating layer 152B formed of the same material as the first passivation layer 152A is silicon oxide (SiO _x ), and the insulating layer 154B formed of the same material as the second passivation layer 154B When formed of silicon nitride (SiNx), the side inclination angle 1 of the insulating layer 152B formed of the same material as the first passivation layer 152A may be formed at about 5 to 15 degrees.

The side inclination angle 2 of the insulating layer 154B formed of the same material as that of the second passivation layer 154A may be about 40 degrees to about 50 degrees. However, the present invention is not limited thereto, and may be varied depending on etchant, process conditions, and the like depending on the kind of the insulating layer material.

2, a thin film transistor (TFT) is formed in an inverted staggered structure, but a thin film transistor (TFT) may be formed in a coplanar structure. When a thin film transistor (TFT) is formed in a coplanar structure, an oxide semiconductor layer, a gate insulating layer, a gate electrode, an intermediate insulating layer, a source electrode, and a drain electrode are sequentially formed on the substrate.

According to the design of the thin film transistor (TFT), the gate insulating layer and the intermediate insulating layer may be formed in direct contact with the oxide semiconductor layer. In this case, the gate insulating layer or the intermediate insulating layer may be composed of a plurality of insulating layers, Of the three insulating layers, the hydrogen content of the insulating layer formed in contact with the oxide semiconductor layer may be smaller than the hydrogen content of the other insulating layer.

Accordingly, the structure of the wiring contact portion of the non-display portion can also be changed. For example, the first insulating layer between the first conductive layer and the second conductive layer may be formed of the same material as the intermediate insulating layer insulating the gate electrode and the source or drain electrode, and the intermediate insulating layer may be formed of a plurality of layers The first insulating layer may also be formed of a plurality of layers.

When the thin film transistor is an inverted staggered structure and the intermediate insulating layer is a plurality of insulating layers including a lower insulating layer and an upper insulating layer, since the oxide semiconductor layer is located above the intermediate insulating layer, The hydrogen content of the upper insulating layer in contact may be smaller than the hydrogen content of the lower insulating layer.

However, when the thin film transistor has a coplanar structure, since the oxide semiconductor layer is located below the intermediate insulating layer, the hydrogen content of the lower insulating layer can be made of a material less than the hydrogen content of the upper insulating layer. Accordingly, it can be expected that the order of stacking the insulating layer of the wiring contact portion of the non-display portion will be similarly affected.

FIG. 3A is a schematic plan view showing one embodiment of the portion B shown in FIG.

3A, the panel driving unit PDU includes a pad unit 190B for transmitting a signal to the display unit 100A. The wiring line L is connected to the pad unit 190B, And a wiring contact portion 180B for transmitting a signal to the wiring contact portion 100A. 2, the wiring contact portion 180B includes a second conductive layer 150B overlapping both the first region and the second region, and the wiring contact portion 180B includes a first region and a second region. As shown in FIG. The pad portion 190B of the panel driving portion PDU overlaps with the second region of the wiring contact portion 180B and does not overlap with the first region. That is, a signal is transferred from the pad portion 190B of the PDP to the second region of the wiring contact portion 180B connected to the pad portion 190B, and the transferred signal is transferred to the first region of the wiring contact portion 180B Area to the display unit 100A.

The pad portion 190B is overlapped and connected to the second region of the wiring contact portion 180B and the contact area between the panel driving portion PDU and the wiring L is larger than the contact area between the second region of the wiring contact portion 180B and the second region of the wiring contact portion 180B, . The first region of the wiring contact portion 180B is formed so as not to overlap with the pad portion 190B so that the first region of the first contact region 180B is overlapped with the first region of the first contact region 180B, By increasing the area of the second region by the area, it is possible to increase the contact area between the panel driving unit (PDU) and the wiring line (L). Further, by forming the area of the second region larger than the area of the first region in the wiring contact portion 180B, the contact area between the panel driving portion (PDU) and the wiring line L can be increased.

 An increase in the contact area between the pad portion 190B of the panel driving unit PDU and the wiring contact portion 180B reduces the contact resistance and facilitates the transmission of the signal flowing to the display portion 100A. It can contribute to reducing defects. More preferably, the area of the second region of the wiring contact portion 180B can be formed to occupy about 40% or more of the area of the pad portion 190B of the PDP. More details will be described later with reference to FIG.

3B is a schematic plan view showing another embodiment of the portion B shown in FIG. 3B shows a case where a plurality of second regions of the wiring contact portion 180B formed by overlapping with the pad portion 190B of the panel driving unit PDU are provided. The description of which will be omitted.

Referring to FIG. 3B, a plurality of first regions and second regions of the wiring contact portion 180B are formed, and a plurality of second regions are overlapped with the pad portions 190B of the PDU. At this time, it is preferable that the sum of the areas of the plurality of second regions is formed to occupy about 40% or more from the viewpoint of the area of the pad portion 190B. Accordingly, So that it can be effective to reduce the screen error abnormality. More details will be described later with reference to FIG.

When the design area of the wiring contact portion 180B is sufficient according to the design of the non-display portion 100B of the display device, the area of the second region of the wiring contact portion 180B is equal to or larger than the area of the pad portion 190B . However, when the area of the second area is the same as the area of the pad part 190B, the contact area is already the maximum, so that the area of the second area is about 40% to about 100% is more preferable when the design area of the non-display portion 100B and the efficiency of the contact resistance are considered.

FIG. 4 is a cross-sectional view of a portion A and a portion B of FIG. 1 according to another embodiment of the present invention, and more specifically, a portion A of the display portion 100A and a panel drive portion (PDU) And B, which is a portion where the wiring L is in contact.

In the following description of the present embodiment, the same or corresponding components as those of the display unit 100A of FIG. 2 will not be described. More specifically, the substrate 200, the gate electrode 210A, the intermediate insulating layer 220A, the oxide semiconductor layer 230A, the source electrode 242A, the drain electrode 244A, the passivation The layer 250A, the planarization layer 260A and the pixel electrode 270A are formed on the substrate 100, the gate electrode 110A, the intermediate insulating layer 120A, the oxide semiconductor layers 130A, The source electrode 142A, the drain electrode 144A, the passivation layer 150A, the planarization layer 160A, and the pixel electrode 170A, and a detailed description thereof will be omitted.

A portion B of the non-display portion 200B of the substrate 200 shown in Fig. 4 where the panel driving portion PDU and the wiring L are in contact will be described as follows.

The panel driver PDU including the pad portion 290B and the first conductive layer 210B, the second conductive layer 240B and the third conductive layer 270B are formed on the non-display portion 200B of the substrate 200. [ A wiring contact portion 280B is formed. More specifically, a second conductive layer 240B is formed on the first conductive layer 210B, a third conductive layer 270B is formed on the second conductive layer 240B, A first region where the second conductive layer 210B contacts the second conductive layer 240B and a second region where the second conductive layer 240B and the third conductive layer 270B are in contact with each other.

The second region overlaps with the pad portion 290B of the PDU, and the second region overlaps the first region. That is, the first conductive layer 210B, the second conductive layer 240B and the third conductive layer 270B are in contact with each other in order, and the signal is transmitted from the pad portion 290B of the PDP to the pad portion 290B (TFT) or the pixel electrode 270A of the display portion 200A via the second region and the first region formed overlapping the first region and the second region.

4, the pad portion 290B and the second region are shown as being separated from each other. However, the pad portion 290B and the second region are in contact with each other through an adhesive material such as ACF (Anisotropic Conductive Film). Specifically, the surface of the third conductive layer 270B corresponding to the second region is connected to the pad portion 290B through an adhesive material.

2, the first conductive layer 210B, the second conductive layer 240B and the third conductive layer 270B of the non-display portion 200B are connected to the gate of the thin film transistor TFT of the display portion 200A, May be formed of the same material through the same process as the electrode 210B, the source or drain electrodes 242A and 244A, and the pixel electrode 270A.

The first insulating layer 220B formed between the first conductive layer 210B and the second conductive layer 240B may be formed of the same material through the same process as the intermediate insulating layer 220A of the display portion 200A And the second insulating layer 250B formed between the second conductive layer 240B and the third conductive layer 270B may be formed of the same material through the same process as the passivation layer 250A of the display portion 220A .

Although not shown in FIG. 4, when the intermediate insulating layer 220A of the display portion 200A is formed of a plurality of insulating layers, the first insulating layer 220B may also be formed of a plurality of insulating layers.

When the passivation layer 250A of the display portion 200A is formed of a plurality of insulating layers 252A and 254A, the second insulating layer 250A may be formed of a plurality of insulating layers 252B and 254B have. Thus, by forming the constituent elements of the display section 200A and the non-display section 200B at the same time, the process can be simplified.

5A is a schematic plan view showing an embodiment of a portion B according to another embodiment of the present invention shown in FIG.

5A, the panel driving unit PDU includes a pad unit 290B for transmitting a signal to the display unit 200A, and the wiring L is connected to the pad unit 290B of the panel driving unit PDU And a wiring contact portion 280B for transmitting a signal to the display portion 200A.

The wiring contact portion 280B is composed of a first region and a second region overlapping each other. Referring to FIG. 4, a region of the second conductive layer 250B overlapped with the first region and the second region, Or the area of the third conductive layer 270B.

The pad portion 290B of the PDP is overlapped with the first region and the second region of the wiring contact portion 280B at the same time. The contact area between the actual panel drive part PDU and the wiring line L corresponds to the area of the second area in direct contact with the pad part 290B. That is, by forming the first region and the second region in a superimposed manner, the area of the portion corresponding to the first region can be reduced at the time of designing the wiring of the non-display portion 200B, so that freedom of design can be secured.

If the area of the pad portion 290B is freely adjustable, the area of the second region and the area of the pad portion 290B are increased by reducing the area of the first region, It is possible to greatly increase the contact area of the contact portion.

As described above, the increase of the contact area between the panel driving unit PDU and the wiring line L reduces the contact resistance between the panel driving unit PDU and the wiring line L to facilitate signal transmission, It can contribute to reducing the screen error. More preferably, the area of the second region can be formed to occupy about 40% or more of the area of the pad portion 290B of the panel driving unit (PDU). A more detailed description will be given later in Fig.

5B is a schematic plan view showing another embodiment of the portion B according to another embodiment of the present invention shown in FIG. More specifically, FIG. 5B shows a case where a plurality of second areas of the wiring contact part 280B formed by overlapping with the pad part 290B of the panel driving part (PDU) have a plurality of the same or corresponding components Will not be described.

Referring to FIG. 5B, a plurality of second regions formed to overlap with the first region are formed in the wiring contact portion 280B, and a plurality of second regions are formed by overlapping with the pad portion 290B of the PDP do. At this time, it is preferable that the sum of the areas of the plurality of second regions is formed to occupy about 40% or more from the viewpoint of the area of the pad portion 290B. Accordingly, So that it can be effective to reduce the screen error abnormality. Similarly, more details will be described later in FIG.

The area of the second region of the wiring contact portion 280B is larger than the area of the pad portion 290B in the case where the design area of the wiring contact portion 280B is sufficient according to the design of the non-display portion 200B of the display device. Or may be designed to be equal to or larger than. More preferably, the area of the second region is formed to be about 40% to about 100% from the area of the pad portion 190B, so that the design area of the non-display portion 200B and the efficiency of contact resistance , It can be more effective.

2 to 5, the contact structure between the wiring contact portion and the pad portion of the panel driving portion has been described. However, when the gate driving portion is a gate driver IC, the pad portion and the wiring contact portion of the gate driving portion But may be constructed in the structure of one embodiment.

FIG. 6 is a table showing the relationship between the contact area between the wiring contact portion and the pad portion and the defective ratio in the embodiment and the comparative example of the present invention. FIG.

Referring to the table of FIG. 6, in a display device using a thin film transistor of an oxide semiconductor layer, a comparative example has a first region which is a contact region between the first conductive layer and the second conductive layer, a contact region between the second conductive layer and the third conductive layer The first region and the second region overlap each other with the pad portion of the panel driving unit, and the first region and the second region do not overlap each other. At this time, the portion actually in contact with the pad portion is the second region. When the area of the second region of the wiring contact portion is about 20.5% of the area of the pad portion, about 28% of the screen defect defect rate of the line defect occurs.

In Embodiment 1, in a display device to which a thin film transistor of an oxide semiconductor layer is applied, a first region which is a contact region between the first conductive layer and the second conductive layer, and a second region which is a contact region between the second conductive layer and the third conductive layer 2 are overlapped with the pad portions of the panel driving portion, and correspond to the structure of Fig. 2 described above. At this time, the area of the second area, which is the area actually in contact with the pad part, can be increased by the area of the first area formed so as not to overlap with the pad part. When the area of the second region of the wiring contact portion is formed to be about 40.4% of the area of the pad portion, the defective screen defect rate of the line defect is 0%. As a result, have.

In Example 2, a first region, which is a contact region between the first conductive layer and the second conductive layer, and a second region, which is a contact region between the second conductive layer and the third conductive layer, in the display device using the thin film transistor of the oxide semiconductor layer, And the pad portion of the panel driving portion are overlapped with each other, and corresponds to the structure of Fig. 4 described above. Likewise, when the area of the second area, which is the portion actually in contact with the pad part, is formed at about 40.1% of the area of the pad part, it is confirmed that the screen defect defect rate of the line defect is 0%, which is improved compared with the comparative example.

7A to 7D are cross-sectional views showing a manufacturing process of a thin film transistor, a pixel electrode, and a wiring contact portion located in a non-display portion, which are located in a display portion, according to an embodiment of the present invention. More specifically, it is a cross-sectional view showing a manufacturing process according to the structure of FIG. 4 mentioned above.

Referring to FIG. 7A, a conductive material for a gate electrode is deposited on a substrate 300, and then patterned using a mask. After patterning, a gate electrode 310A is formed on the display portion 300A of the substrate 300, and a first conductive layer 310B is formed on the non-display portion 300B. The gate electrode 310A and the first conductive layer 310B are formed of the same material through the same process.

Referring to FIG. 7B, an insulating material is deposited on the gate electrode 310A and the first conductive layer 310B and then patterned. A wet etch may be used to pattern the insulating material. After the patterning, the intermediate insulating layer 320A is formed on the display portion 300A of the substrate 300, and the first insulating layer 320B is formed on the non-display portion 300B. The first insulating layer 320B formed on the non-display portion 300B has a contact hole on the first conductive layer 310B and a side inclination angle of the contact hole may be about 30 to 40 degrees. The intermediate insulating layer 320A and the first insulating layer 320B are formed of the same material through the same process.

Thereafter, an oxide semiconductor layer 330A is deposited and patterned on the intermediate insulating layer 320A of the display portion 300A.

Referring to FIG. 7C, a conductive material for source and drain electrodes is deposited on the intermediate insulating layer 320A, the first insulating layer 320B, and the oxide semiconductor layer 330A, and then patterned using a mask. The thin film transistor TFT is formed by forming the source electrode 342A and the drain electrode 344A in the display portion 300A after the patterning and the second conductive layer 340B is formed in the non-display portion 300B. The second conductive layer 340B of the non-display portion 300B is contacted with the first conductive layer 310B through the contact hole of the first insulating layer 320B. Similarly, the source electrode 342A and the drain electrode 344A and the second conductive layer 340B are formed of the same material through the same process.

7D, an insulating material is deposited and patterned on the thin film transistor TFT and the second conductive layer 340B. In patterning the insulating material, dry etching is used to form a thin film transistor TFT It is possible to minimize the influence of the oxide semiconductor layer 310A. After patterning, a first passivation layer 352A for protecting the thin film transistor is formed on the display portion 300A, and one (352B) of the second insulating layer 350B is formed on the non-display portion 300B.

Thereafter, a planarization material is deposited to planarize the surface of the thin film transistor (TFT), and then patterned to form a planarization layer 360A. The planarization layer 360A is formed of an organic material and may be formed of a material such as a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin polyimides rein, unsaturated polyesters resins, poly-phenylenethers resins, poly-phenylenesulfides resins, and benzocyclobutenes. But is not limited thereto.

The second passivation layer 354A is formed on the display portion 300A and the other one of the second insulating layers 350B is formed on the non-display portion 300B by patterning the insulating material on the planarization layer 360A again. Is formed. Similarly, when patterning an insulating material, dry etching can be used. The pixel electrode 370A is formed on the display portion 300A and the third conductive layer 370B is formed on the non-display portion 300B by depositing and patterning the conductive material for the pixel electrode on the second passivation layer 354A. .

The pixel electrode 370A in the display portion 300A is connected to the source electrode 342A of the thin film transistor TFT through the contact hole of the passivation layer 350A and the planarization layer 360A. In the non-display portion 300B, the third conductive layer 370B is in contact with the second conductive layer 340B through the contact hole of the second insulating layer 350B.

As described in FIGS. 7A to 7D, when the thin film transistor (TFT) and the pixel electrode 370A of the display portion 300A are formed, the wiring contact portion of the non-display portion 300B is formed at the same time, have.

In the display device according to an embodiment of the present invention, the first area may not overlap the pad part of the panel driving part.

In the display device according to an embodiment of the present invention, the area of the second area may be larger than the area of the first area.

In the display device according to an embodiment of the present invention, the third conductive layer may not be formed on the first region.

In the display device according to an embodiment of the present invention, the area of the second area may be 40% or more based on the area of the pad part of the panel driving part.

In the display device according to an embodiment of the present invention, when a plurality of the second regions are formed, the plurality of second regions are formed so as to overlap the pad portions of the panel driving portion, and the sum of the areas of the plurality of second regions May be 40% or more based on the area of the pad portion of the panel driving portion.

In the display device according to an embodiment of the present invention, the first area may overlap with the second area.

The first conductive layer, the second conductive layer, and the third conductive layer may be in contact with each other in a display device according to an exemplary embodiment of the present invention.

In a display device according to an embodiment of the present invention, the thin film transistor includes a gate electrode, a source or a drain electrode and an intermediate insulating layer, the first conductive layer is formed of the same material as the gate electrode, Layer may be formed of the same material as the source electrode or the drain electrode, and the third conductive layer may be formed of the same material as the pixel electrode.

In a display device according to an embodiment of the present invention, a first insulating layer formed between the first conductive layer and the second conductive layer, a second insulating layer formed between the second conductive layer and the third conductive layer, As shown in FIG.

In the display device according to an embodiment of the present invention, the first insulating layer may be made of the same material as the intermediate insulating layer of the thin film transistor.

In the display device according to an exemplary embodiment of the present invention, the intermediate insulating layer may include a plurality of insulating layers, and the hydrogen content of one of the plurality of insulating layers may be less than the hydrogen content of the other insulating layer.

In the display device according to an embodiment of the present invention, the insulating layer having a small hydrogen content among the plurality of insulating layers may be formed in contact with the oxide semiconductor layer of the thin film transistor.

In the display device according to an embodiment of the present invention, the second insulating layer is composed of a plurality of insulating layers including contact holes for forming the second regions, and the contact of one of the plurality of insulating layers The side inclination angle of the hole and the side inclination angle of the contact hole of the other insulating layer may be different.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments.

Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

100, 200, 300: substrate
100A, 200A, 300A:
110A, 210A, 310A: gate electrode
120A, 220A, 320A: intermediate insulating layer
130A, 230A, and 330A: an oxide semiconductor layer
142A, 242A, and 342A:
144A, 244A, 344A: drain electrode
150A, 250A, 350A: Passivation layer
152A, 252A, 352A: a first passivation layer
154A, 254A, 354A: a second passivation layer
170A, 270A, and 370A:
100B, 200B, and 300B:
110B, 210B, and 310B: a first conductive layer
120B, 220B, and 320B: a first insulating layer
140B, 240B, and 340B: a second conductive layer
150B, 250B, and 350B: the second insulating layers 152B, 154B, 252B, 254B, 352B, and 354B,
170B, 270B, and 370B: a third conductive layer
PDU:
GDU: Gate driver
L: Wiring
TFT: Thin film transistor
180B, and 280B: wiring contact portions
190B and 290B:

Claims (16)

A substrate including a display portion and a non-display portion;
A thin film transistor formed on the display section and including an oxide semiconductor layer;
A pixel electrode formed on the display unit and connected to the thin film transistor;
A panel driver connected to the non-display portion and including a pad portion for transmitting a signal to the thin film transistor or the pixel electrode; And
A first conductive layer, a second conductive layer, and a third conductive layer formed on the non-display portion, wherein the first region is in contact with the first conductive layer and the second conductive layer, 3 conductive layer, and the second region is overlapped with the pad portion of the panel driving portion.
The method according to claim 1,
Wherein the first area does not overlap the pad part of the panel driving part.
3. The method of claim 2,
Wherein an area of the second region is larger than an area of the first region.
The method of claim 3,
And the third conductive layer is not formed on the first region.
3. The method of claim 2,
And the area of the second region is 40% or more based on an area of the pad portion of the panel driving portion.
3. The method of claim 2,
Wherein the plurality of second regions are formed so as to overlap with the pad portions of the panel driving portion and the sum of the areas of the plurality of second regions is set to be larger than the sum of the areas of the pad portions of the panel driving portion Wherein the display device is at least 40%.
The method according to claim 1,
And the first region overlaps with the second region.
8. The method of claim 7,
Wherein the first conductive layer, the second conductive layer, and the third conductive layer are in contact with each other in order.
8. The method of claim 7,
And the area of the second region is 40% or more based on an area of the pad portion of the panel driving portion.
8. The method of claim 7,
Wherein the plurality of second regions are formed so as to overlap with the pad portions of the panel driving portion and the sum of the areas of the plurality of second regions is set to be larger than the sum of the areas of the pad portions of the panel driving portion Wherein the display device is at least 40%.
8. The method according to claim 2 or 7,
Wherein the thin film transistor includes a gate electrode, a source or drain electrode, and a middle insulating layer,
The first conductive layer is formed of the same material as the gate electrode,
The second conductive layer is formed of the same material as the source electrode or the drain electrode,
And the third conductive layer is formed of the same material as the pixel electrode.
12. The method of claim 11,
A first insulating layer formed between the first conductive layer and the second conductive layer; And
And a second insulating layer formed between the second conductive layer and the third conductive layer.
13. The method of claim 12,
Wherein the first insulating layer is made of the same material as the intermediate insulating layer of the thin film transistor.
14. The method of claim 13,
Wherein the intermediate insulating layer is composed of a plurality of insulating layers, and the hydrogen content of one of the plurality of insulating layers is smaller than the hydrogen content of the other insulating layer.
15. The method of claim 14,
Wherein an insulating layer having a small hydrogen content among the plurality of insulating layers is formed in contact with the oxide semiconductor layer of the thin film transistor.
13. The method of claim 12,
Wherein the second insulating layer is composed of a plurality of insulating layers including contact holes for forming the second regions, and the side inclination angle of the contact holes of one of the plurality of insulating layers is different from the side inclination angle of the contact holes of the other insulating layer Wherein the inclination angle is different.

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