KR20170079956A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided. The liquid crystal display device includes a substrate, a first wiring, a first planarization layer, a conductive layer, a second planarization layer, and a second wiring. The first wiring is disposed on the substrate. The first planarization layer is disposed on the first wiring and includes a plurality of first contact holes. The conductive layer is disposed on the first planarization layer and contacts the first wiring through the plurality of first contact holes. The second planarization layer is disposed on the first planarization layer and includes a second contact hole. The second wiring is in contact with the conductive layer through the second contact hole in a region between at least two first contact holes adjacent to each other among the plurality of first contact holes.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device with improved reliability by minimizing damage to a wiring caused in a manufacturing process.

BACKGROUND ART A liquid crystal display (LCD) is a display device that implements an image in such a manner that a light source is disposed under a liquid crystal and an electric field is applied to the liquid crystal to control the arrangement of the liquid crystal to pass or block light generated in the light source , Smart phones and tablet PCs.

On the other hand, in recent years, a liquid crystal display device on which a touch screen is mounted is widely used. The touch screen is a device for sensing a touch input to a user's liquid crystal display device, and the touch screen may be attached on the screen of the liquid crystal display device in an on-cell manner. However, in the case of the on-cell method, the thickness of the liquid crystal display device is increased and the visibility of the liquid crystal display device is lowered due to the increased thickness. To solve this problem, an in-cell type touch screen in which a touch screen is integrated with a liquid crystal display device has been developed.

A liquid crystal display device including an in-cell type touch screen includes a common electrode functioning as a touch electrode. However, the common electrode is made of a transparent conductive oxide (TCO) to minimize the visibility reduction of the liquid crystal display device. Since the common electrode made of the transparent conductive oxide has a higher resistance than the metal electrode, the signal delay of the touch signal can be caused. Thus, a separate metal wiring connected to the common electrode is formed so as to lower the resistance of the common electrode and prevent the signal delay of the touch signal.

In a liquid crystal display device including an in-cell type touch screen, since the common electrode functions as a touch electrode, a touch wiring for transferring a touch signal of the touch electrode to the touch pad portion is disposed on the substrate. That is, a display wiring for driving a pixel of a liquid crystal display device and a touch wiring for transmitting a touch signal are arranged on a substrate.

These wirings can extend on mutually different planes. However, wirings arranged on different planes can be brought into contact with each other for reasons of circuit design. Wirings arranged on different planes from each other can be brought into contact with each other through contact holes provided in the planarization layer. In this case, a plurality of contact holes may be formed in the planarization layer in order to maximize the contact area of the wirings and improve the adhesion between the wirings. The wirings may be in contact with each other through a plurality of contact holes provided in the planarization layer.

However, if the spacing between the contact holes in the process of forming a plurality of contact holes is dense, there may arise a problem that the planarization layer breaks in the region between two adjacent contact holes. In this case, the wiring disposed under the planarization layer in the area where the planarization layer is torn can be exposed. If the wiring over the planarization layer is in contact with the wiring under the planarization layer only in the contact hole region, the wiring under the planarization layer disposed in the region where the planarization layer is torn can be broken in the subsequent process. Specifically, the wiring under the planarization layer disposed in the area where the planarization layer is torn can be exposed to the etchant in the etching process of the substrate. The etchant can be made of a strong acidic liquid, in which case the etchant can partially corrode or damage the underlying wiring of the planarization layer. The corroded wiring below the flattening layer may increase the resistance rapidly and may not transmit signals of the liquid crystal display device well. Thus, there is a problem that the reliability of the liquid crystal display device is reduced.

An array substrate for a liquid crystal display and a method of manufacturing the same (Patent Application No. 10-2012-0057966)

The inventor of the present invention has recognized that a problem arises that the planarization layer is broken due to a small distance between the contact holes in the region where the wirings are in contact with each other in the liquid crystal display device. The present inventors have found that a substrate which can minimize corrosion of a conductive layer which may be generated in a subsequent process by using a second wiring covering the top surface of the exposed conductive layer due to tearing of the flattening layer, and a liquid crystal display .

Accordingly, an object of the present invention is to minimize the corrosion of the conductive layer by using the second wiring covering the conductive layer exposed in the region between the at least two first contact holes adjacent to each other among the plurality of first contact holes, And a liquid crystal display device including the same.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a liquid crystal display device including a substrate, a plurality of thin film transistors, a first planarization layer, a second planarization layer, a common electrode, a first wiring, 2 wiring. The substrate includes a bezel region including an active region and an active region. The plurality of thin film transistors are arranged in the active region of the substrate. The first planarization layer covers a plurality of thin film transistors. The second planarization layer is disposed on the first planarization layer. The common electrode is disposed on the second planarization layer in the active region. The first wiring is disposed below the first planarization layer in the bezel region. The conductive layer is disposed on the first planarization layer in the bezel region and contacts the first wiring through a plurality of first contact holes provided in the first planarization layer. The second wiring is in contact with the conductive layer through a second contact hole provided in the second planarization layer in a region between at least two first contact holes adjacent to each other among the plurality of first contact holes in the bezel region. The liquid crystal display device according to an embodiment of the present invention uses the second wiring in contact with the conductive layer so that even if the second planarizing layer is scratched at a region between two adjacent first contact holes, The contact resistance between the conductive layer and the first wiring is maintained, and the reliability of the liquid crystal display device can be improved.

According to another aspect of the present invention, at least two first contact holes adjacent to each other are exposed by the second contact holes, and the second wiring covers the at least two first contact holes through the second contact hole.

According to another aspect of the present invention, the conductive layer is made of a metal, the second wiring is made of a transparent conductive oxide (TCO), and the first planarization layer and the second planarization layer are made of photo- ; PAC).

According to another aspect of the present invention, a liquid crystal display further includes a third wiring in contact with a second wiring, the second wiring exposing an upper surface of the conductive layer in a region corresponding to the plurality of first contact holes, 3 wiring can be in contact with the upper surface of the conductive layer in a region corresponding to the plurality of first contact holes.

According to another aspect of the present invention, the distance between the centers of the at least two first contact holes may be 22 mu m or less.

According to another aspect of the present invention, there is provided a liquid crystal display device including a substrate, a plurality of thin film transistors, a first planarization layer, a second planarization layer, a common electrode, a first wiring, 2 wiring. The substrate includes a bezel region including an active region and an active region. The plurality of thin film transistors are arranged in the active region of the substrate. The first planarization layer covers a plurality of thin film transistors. The second planarization layer is disposed on the first planarization layer. The common electrode is disposed on the second planarization layer in the active region. The first wiring is disposed below the first planarization layer in the bezel region. The conductive layer is disposed on the first planarization layer in the bezel region and contacts the first wiring through a plurality of first contact holes provided in the first planarization layer. The second wiring covers at least a part of the upper surface of the conductive layer which is provided in the second planarization layer in the bezel region and exposed through the second contact holes corresponding to the at least two adjacent first contact holes among the plurality of first contact holes .

According to another aspect of the present invention, the second wiring and the common electrode may be made of a transparent conductive oxide.

According to another aspect of the present invention, the liquid crystal display further includes a third wiring in contact with the second wiring and made of metal, and the common electrode may function as a touch electrode for sensing the touch input of the user.

According to another aspect of the present invention, the third wiring, the second wiring, the conductive layer, and the first wiring are configured to transmit the touch signal of the touch electrode.

According to another aspect of the present invention, there is provided a liquid crystal display device including a substrate, a plurality of thin film transistors, a first planarization layer, a second planarization layer, a common electrode, a signal wiring, and a link wiring. The substrate includes a display area and a non-display area. The plurality of thin film transistors are arranged in the display region of the substrate. The first planarization layer covers a plurality of thin film transistors. The second planarization layer is disposed on the first planarization layer. The common electrode is disposed on the second planarization layer in the display area. The signal wiring is connected to a plurality of thin film transistors or a common electrode and is configured to transmit a driving signal. The link wiring is connected to the signal wiring in the first contact area. In the first contact region, the link wiring includes a first wiring, a first conductive layer, and a second wiring. The first wiring is disposed under the first planarization layer. The first conductive layer is disposed on the first planarization layer and contacts the first wiring through the plurality of first contact holes of the first planarization layer. The second wiring is in contact with the conductive layer through the second contact hole of the second planarization layer in a region between the at least two first contact holes adjacent to each other among the plurality of first contact holes.

According to another aspect of the present invention, the liquid crystal display may further include a pad wiring connected to the pad disposed in the non-display area and configured to receive a control signal from the pad. The link wiring can be connected to the pad wiring in the second contact area. In the second contact region, the link wiring may include a second conductive layer and a second wiring. The second conductive layer is disposed on the first planarization layer and can contact the first wiring through the plurality of third contact holes of the first planarization layer. The second wiring may be in contact with the conductive layer through the fourth contact hole of the second planarization layer in a region between the at least two third contact holes adjacent to each other among the plurality of third contact holes.

According to another aspect of the present invention, at least two first contact holes adjacent to each other in the first contact region are exposed by the second contact hole, and at least two third contact holes adjacent to each other in the second contact region And the second wiring covers at least two first contact holes through the second contact hole in the first contact region and the second wiring is exposed through the fourth contact hole in the second contact region by the fourth contact hole, And may cover at least two third contact holes.

According to another aspect of the present invention, the liquid crystal display device may further include a third wiring in contact with the second wiring. The second wiring exposes the upper surface of the first conductive layer in the region corresponding to the plurality of first contact holes and exposes the upper surface of the second conductive layer in the region corresponding to the plurality of third contact holes, The second conductive layer can be in contact with the upper surface of the first conductive layer in the region corresponding to the plurality of first contact holes and in contact with the second conductive layer in the region corresponding to the plurality of second contact holes.

According to another aspect of the present invention, the distance between the centers of the at least two first contact holes is 22 占 퐉 or less, and the distance between the centers of the at least two third contact holes is 22 占 퐉 or less.

The details of other embodiments are included in the detailed description and drawings.

The present invention is characterized in that in the region between at least two first contact holes adjacent to each other among the plurality of first contact holes, a second wiring that contacts the conductive layer through the second contact hole is used to form a second flattening layer covering the conductive layer The corrosion of the conductive layer is minimized and the reliability of the display device can be improved.

The present invention has the effect of making the bezel region of a liquid crystal display device thinner by reducing the width of wirings by using the first wiring, the conductive layer and the second wiring which are electrically connected to each other and arranged on different planes.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a schematic plan view for explaining a liquid crystal display device according to an embodiment of the present invention.
2 is a partially enlarged plan view of the region A in Fig.
FIG. 3 is a schematic cross-sectional view of IIIa-IIIa 'and IIIb-IIIb' of FIG. 2. FIG.
4 is a schematic cross-sectional view of a liquid crystal display according to a comparative example for explaining the effect of preventing corrosion of a conductive layer in a liquid crystal display device according to an embodiment of the present invention.
5 is a schematic cross-sectional view for explaining a liquid crystal display device according to another embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer "on ", including both intervening layers or other elements directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic plan view for explaining a liquid crystal display device according to an embodiment of the present invention. 1, a liquid crystal display 100 includes a substrate 110, a first wiring 120, a conductive layer 130, a second wiring 140, a third wiring 150, a first planarization layer, And a second planarization layer. For convenience of explanation, the first planarizing layer and the second planarizing layer are not shown in Fig.

The substrate 110 is a substrate for supporting various components of the liquid crystal display device 100, and may be a glass substrate or a plastic substrate. The substrate 110 includes an active area A / A and a bubble area B / A. The active area A / A refers to an area where an image is displayed in the liquid crystal display device 100, and may be referred to as a display area. The bevel region B / A refers to a region other than the active region A / A, which means an area where no image is displayed. Thus, the bezel area B / A can be referred to as a non-display area.

Display elements are arranged in the active area A / A. The display device may include various elements that constitute a pixel of the liquid crystal display device 100. For example, the display device may include a thin film transistor (TFT), a pixel electrode connected to the thin film transistor, a common electrode spaced apart from the pixel electrode, and a liquid crystal disposed on the pixel electrode. The display elements are supplied with a drive signal from the signal wiring arranged in the active area A / A, and operate based on the drive signal. For example, the thin film transistor is connected to the data signal wiring and the gate signal wiring, and can apply a voltage to the pixel electrode based on the data driving signal transmitted from the data signal wiring and the gate driving signal transmitted from the gate signal wiring.

A touch electrode for sensing the touch input of the user is disposed in the active area A / A. The touch electrode is an electrode for sensing a touch input of the user to the liquid crystal display device 100. For example, when an electrostatic object approaches the touch electrode, such as a user's finger or a stylus, the capacitance of the touch electrode changes, and the touch of the user based on the touch signal generated due to the capacitance variation Input can be detected. The touch electrodes are arranged in an in-cell manner inside the display device. For example, the touch electrode can be realized as a common electrode of the display element. In this case, the common electrode simultaneously performs a function as a touch electrode and a function as a common electrode. For example, a touch driving voltage or a touch scan current may be applied to the common electrode during a touch sensing period in which the touch input is sensed, and a common voltage may be applied to the common electrode during a display period in which an image is displayed. Hereinafter, the common electrode and the touch electrode are referred to as the same components.

The display panel 100 includes a touch pad portion TP, a display pad portion DP, a data driving circuit DI, a gate driving circuit GIP, a first wiring 120, a conductive layer 130, Two wirings 140 and a third wiring 150 are disposed. The touch pad unit TP is disposed at the top of the bezel area B / A and receives a touch signal from the first wiring 120. The first wiring 120 is connected to the conductive layer 130, the second wiring 140 and the third wiring 150 in the second contact region C / A2 and receives a touch signal through the common electrode. 1, the detailed configuration of the touch pad unit TP is not shown, and the area where the touch pad unit TP is disposed is indicated by a dotted line. A touch flexible substrate is connected to the touch pad unit TP, and the touch signal is transmitted to the touch flexible substrate through the touch pad unit TP. The touch pad unit TP includes a touch pad directly contacting the touch flexible substrate and a touch pad wiring connected to the touch pad to transmit the touch signal to the touch pad. The touch pad unit TP is disposed separately on the left upper end and the right upper end of the substrate 110, respectively. However, the present invention is not limited thereto, and the touch pad unit TP may be disposed only on one side of the substrate 110.

The display pad portion DP is disposed between the touch pad portion TP at the upper end of the bevel region B / A and transmits a control signal to the data driving circuit DI and the gate driving circuit GIP. The display pad portion DP includes a display pad directly contacting the display flexible substrate and a display pad wiring connected to the display pad and transmitting a control signal to the data driving circuit DI and the gate driving circuit GIP. 1, the detailed configuration of the display pad unit DP is not shown, and the area where the display pad unit DP is disposed is indicated by a dotted line. A display flexible substrate is connected to the display pad portion DP and a control signal is transmitted to the data driving circuit DI and the gate driving circuit GIP via the display pad portion DP.

The first wiring 120 is connected to both ends of the display pad portion DP. The first wiring 120 transfers a common voltage supplied from the display pad unit DP to the common electrode of the active area A / A. In this case, the first wiring 120 is connected to the second wiring 140 and the third wiring 150 in the contact region, which will be described later with reference to FIG.

The data driving circuit DI is connected to the display pad unit DP and generates a data driving signal based on a control signal supplied from the display pad unit DP. The detailed structure of the data driving circuit DI is not shown in Fig. 1, and the area where the data driving circuit DI is arranged is shown by a dotted line. The data driving circuit DI may be packaged on a substrate 110 by a chip on glass (COG) or a tape carrier package method. The data driving circuit DI provides a data driving signal to a display element of the active area A / A. The data driving circuit DI is connected to the first wiring 120. The first wiring 120 connected to the data driving circuit DI may be connected to the source electrode or the drain electrode of the thin film transistor extended in the active area A / A and arranged in the active area A / A. The first wiring 120 transfers the data driving signal generated in the data driving circuit DI to the source electrode or the drain electrode of the thin film transistor and can be used as a data signal wiring.

The gate drive circuit GIP is arranged to face both sides of the active area A / A. The detailed structure of the gate drive circuit (GIP) is not shown in Fig. 1, and the region where the gate drive circuit (GIP) is arranged is shown by a dotted line. The gate drive circuit GIP may be mounted on the substrate 110 in a COG or TCP manner, but may also be formed directly on the substrate 110. [ In this case, the gate drive circuit (GIP) may be referred to as a gate in panel (GIP). When the gate driving circuit (GIP) is formed by a gate-in-panel method, manufacturing cost of the liquid crystal display device 100 can be reduced, and the weight and volume of the liquid crystal display device 100 can be reduced.

The first wiring 120, the conductive layer 130, the second wiring 140 and the third wiring 150 are extended between the active area A / A and the gate driving circuit GIP. The first wiring 120, the conductive layer 130, the second wiring 140 and the third wiring 150 are connected to the touch electrode (that is, the common electrode) of the active area A / A, Receives the touch signal and transmits it to the touch pad unit TP. Thus, the first wiring 120, the conductive layer 130, the second wiring 140, and the third wiring 150 may be referred to as a touch wiring.

In some embodiments, the touch wiring composed of the first wiring 120, the conductive layer 130, the second wiring 140 and the third wiring 150 may extend outside the gate driving circuit (GIP) But may extend both inside and outside the gate driving circuit GIP.

In the first contact area C / A1, the first wiring 120 is connected to the second wiring 140 and the third wiring 150, and the first wiring 120 (120) is connected in the second contact area C / Are connected to the conductive layer 130, the second wiring 140, and the third wiring 150. Referring to FIGS. 2 and 3 together to explain the connection of the first wires 120, FIG.

2 is a partially enlarged plan view of the region A in Fig. 3 is a schematic cross-sectional view of IIIa-IIIa 'and IIIb-IIIb' of FIG. 2; 2 and 3, in the first contact area C / A1 and the second contact area C / A2, the first wiring 120 is in contact with the conductive layer 130, Contacts the second wiring 140 and the third wiring 150. Specifically, the first wiring 120 is in contact with the conductive layer 130 through the plurality of first contact holes CH1 disposed in the first contact area C / A1 and the second contact area C / A2 And contacts the second wiring 140 through the plurality of second contact holes CH2. The third wiring 150 directly contacts the second wiring 140.

The second wiring 140 and the third wiring 150 extend to the lower end of the first contact area C / A1. As shown in FIG. 1, the second wiring 140 and the third wiring 150 extend to the active area A / A and are connected to the common electrode of the active area A / A. As described above, the first wiring 120 disposed at the top of the first contact area C / A1 is connected to the display pad part DP and receives a common voltage from the display pad part DP. The common voltage supplied from the display pad unit DP is transferred to the first contact region C / A1 through the first wiring 120 and the second wiring 140 and the second wiring 140 in the first contact region C / And then transferred to the third wiring 150. The common voltage provided to the second wiring 140 and the third wiring 150 can be transmitted to the common electrode of the active area A / A. Accordingly, the first wiring 120, the second wiring 140, and the third wiring 150 connected to each other in the first contact area C / A1 function as a common wiring for applying a common voltage.

Referring to FIG. 3, the first wiring 120 is disposed on the substrate 110. Specifically, the first wiring 120 is disposed on the interlayer insulating layer 112 of the substrate 110. The first wiring 120 is disposed on the same plane as the first source electrode or the first drain electrode of the first thin film transistor disposed on the substrate 110. For example, a first active layer is disposed on a substrate 110, and a gate insulating layer 111 is disposed to cover the first active layer. A first gate electrode is disposed on the gate insulating layer 111 so as to overlap with the first active layer, and an interlayer insulating layer 112 is disposed to cover the first gate electrode. A first source electrode and a first drain electrode are disposed on the interlayer insulating layer 112 to be connected to the first active layer through contact holes provided in the interlayer insulating layer 112 and the gate insulating layer 111.

The first wiring 120 is disposed on the same plane as the first source electrode and the first drain electrode and may be formed of the same material as the first source electrode and the first drain electrode. For example, the first wiring 120, the first source electrode, and the first drain electrode may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti) , Neodymium (Nd), and copper (Cu), or an alloy thereof. In some embodiments, the first wiring 120, the first source electrode, and the first drain electrode may be made of a conducting semiconductor. In this case, a second active layer made of a nonconducting semiconductor may be disposed on the interlayer insulating layer 112, and a second thin film transistor having a different electrical characteristic from the first thin film transistor formed on the gate insulating layer 111 May be additionally formed. The first wiring 120, the first source electrode, and the first drain electrode may be formed as a single layer or a multi-layer structure including the above-described materials.

A first planarization layer (113) is disposed to cover the first wiring (120). The first planarizing layer 113 covers the interlayer insulating layer 112, and flattens the upper surface of the substrate 110. Specifically, since the thin film transistor and the first wiring 120 are formed on the substrate 110, a step may be formed on the substrate 110. The first planarizing layer 113 covers the step formed on the substrate 110, and flattenes the top of the substrate 110.

The first planarization layer 113 is formed of an organic material so as to compensate a step on the substrate 110 and flatten the top surface. For example, the first planarization layer 113 may be formed of a photo acryl (PAC). The first planarization layer 113 may be formed to a thickness of 2 탆 to 3 탆 so as to sufficiently cover a step formed on the substrate 110.

The first planarization layer 113 includes a plurality of first contact holes CH1 exposing the first wires 120. [ A plurality of first contact holes CH1 are disposed in the first contact area C / A1 and the second contact area C / A2. The upper surface of the first wiring 120 is exposed through the plurality of first contact holes CH1 and the conductive layer 130 contacts the upper surface of the first wiring 120 through the first contact hole CH1.

The plurality of first contact holes CH1 are formed in a rectangular shape, as shown in Fig. However, the present invention is not limited thereto, and the plurality of first contact holes CH1 may be formed in a polygonal shape, a circular shape, or an elliptical shape except a square shape. The sizes of the plurality of first contact holes CH1 may be variously configured. The conductive layer 130 can not sufficiently fill the first planarization layer 113 and the first planarization layer 113 may not fill the first planarization layer 113. In this case, The conductive layer 130 may not touch. The size of the first contact hole CH1 may be determined to be an appropriate size in consideration of the step coverage of the conductive layer 130 and the thickness of the first planarization layer 113. [

The plurality of first contact holes CH1 are spaced apart from each other by a specific distance. For example, the distance between the centers of two adjacent first contact holes CH1 may be less than 22 mu m. If the distance between the centers of two adjacent first contact holes CH1 exceeds 22 mu m, the size of the first contact area C / A1 can be large, and the distance between the wirings can be increased. In this case, since the physical space for arranging the wirings can be increased, the bezel of the liquid crystal display device 100 can be thickened. However, when the distance between the centers of the first contact holes CH1 is 22 mu m or less, the size of the first contact area C / A1 is sufficiently small so that the distance between the wirings can be reduced, Can be reduced.

The conductive layer 130 is disposed on the first planarization layer 113 and contacts the first wiring 120 through the plurality of first contact holes CH1. The conductive layer 130 is made of a metal having low resistance. For example, the conductive layer 130 may be formed of any one of aluminum, chromium, and copper, or an alloy thereof, but not limited thereto, and may be formed of various materials. The conductive layer 130 may be formed as a single layer or a multi-layer structure including the above-described materials.

2, the conductive layer 130 is disposed in the first contact area C / A1 and improves contact characteristics between the first wiring 120 and the second wiring 140. As shown in FIG. As described above, in the case where the first wiring 120 is made of a conductive semiconductor, the contact resistance between the first wiring 120 and the second wiring 140 can be increased. In this case, the conductive layer 130 may be disposed between the first wiring 120 and the second wiring 140 to form an ohmic contact and reduce the contact resistance of the first wiring 120 .

The second planarization layer 114 is disposed on the first planarization layer 113 and includes a plurality of second contact holes CH2. The upper surface of the conductive layer 130 is exposed through the plurality of second contact holes CH2. The second planarization layer 114 may be formed of an organic material. For example, the second planarization layer 114 may be formed of the same organic material as that of the first planarization layer 113, and may have a thickness of 2 袖 m to 3 袖 m.

At least one second contact hole CH2 of the plurality of second contact holes CH2 may correspond to at least two first contact holes CH1 adjacent to each other among the plurality of first contact holes CH1. That is, at least one second contact hole CH2 of the plurality of second contact holes CH2 may be formed to have a size larger than that of the first contact hole CH1. The second contact hole CH2 of a large size can be formed by parting off the second planarization layer 114 in an exposure process for forming the second contact hole CH2. A more detailed description thereof will be described later with reference to Fig.

The second wiring 140 and the third wiring 150 are disposed on the second planarization layer 114. The second wiring 140 is disposed on the same plane as the common electrode arranged in the active area A / A. The second wiring 140 and the common electrode may be formed of the same material. For example, the second wiring 140 and the common electrode may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide and tin oxide In this case, the decrease in visibility of the liquid crystal display device 100 due to the common electrode disposed in the active area A / A can be minimized.

The third wiring 150 is disposed on the second wiring 140 and is made of a metal having low resistance. For example, the third wiring 150 may be formed of any one of aluminum, chromium, and copper, or an alloy thereof, in the same manner as the conductive layer 130. However, without being limited thereto, the third wiring 150 may be formed of various materials. The third wiring 150 may be formed as a single layer or a multi-layer structure including the above-described materials.

 The third wiring 150 reduces the electrical resistance of the second wiring 140. Specifically, the second wiring 140 is connected to the common electrode in the active area A / A, and transmits the common voltage to the common electrode. As described above, since the second wiring 140 is made of a transparent conductive oxide, the electrical resistance of the second wiring 140 is relatively higher than that of the conductive layer 130. If the common voltage is transmitted only to the second wiring 140, the common voltage, which is transmitted to the common electrode disposed at the central portion of the active area A / A due to the resistance of the second wiring 140, May be lower than a common voltage that is transmitted to the common electrode disposed at the outer portion of the region A / A. However, when the third wiring 150 is formed to be in contact with the second wiring 140, the resistance of the second wiring 140 can be lowered by the third wiring 150, / A in the center portion and the outer portion.

The second wiring 140 and the third wiring 150 are disposed on a plane different from the conductive layer 130 and are in contact with the conductive layer 130 exposed through the second contact hole CH2. More specifically, the second wiring 140 is formed in a region corresponding to the plurality of first contact holes CH1 and in a region between two first contact holes CH1 adjacent to each other among the plurality of first contact holes CH1 And contacts the conductive layer 130. That is, the second wiring 140 covers the upper surface of the conductive layer 130 exposed through the second contact hole CH2, and the third wiring 150 contacts the upper surface of the second wiring 140. The upper surface of the conductive layer 130 in the second contact hole CH2 is covered by the second wiring 140 or the third wiring 150 and the upper surface of the conductive layer 130 is not exposed.

The second wiring 140 and the third wiring 150 minimize the damage of the conductive layer 130 by being exposed to the etchant in the manufacturing process of the liquid crystal display device 100. [ A detailed description thereof will be given later with reference to Fig.

Referring again to FIG. 2, in the second contact area C / A2, the first wiring 120 extends to the top of the second contact area C / A2 and the first wiring 120, the conductive layer 130 ), The second wiring 140 and the third wiring 150 extend to the lower end of the second contact area C / A2. As shown in FIG. 1, the first wiring 120 extending to the upper end of the second contact area C / A2 is connected to the touch pad TP, and the lower end of the second contact area C / The first wiring 120, the conductive layer 130, the second wiring 140 and the third wiring 150 extending from the active region A / A to the gate driving circuit GIP extend to the bezel region B / A). The first wiring 120, the conductive layer 130, the second wiring 140, and the third wiring 150 are connected to a common electrode functioning as a touch electrode. As described above, since the common electrode is disposed on the same plane as the second wiring 140, the first wiring 120 and the conductive layer 130 at the boundary of the active area A / A are electrically connected to the second wiring 140 140 and the second wiring 140 and the third wiring 150 extend to the active area A / A.

The first wiring 120, the conductive layer 130, the second wiring 140 and the third wiring 150 extending to the lower end of the second contact area C / A2 receive the touch signal from the common electrode, It functions as touch wiring. 3, the first wiring 120, the conductive layer 130, and the second wiring 140 are disposed on different planes, and the first planarization layer 113 and the second planarization layer 114 ).

Since the second wiring 140 is in contact with the first wiring 120 and the conductive layer 130 at the boundary between the second contact region C / A2 and the active region A / A, the first wiring 120, The resistance of the conductive layer 130, the second wiring 140 and the third wiring 150 can be lowered and the resistance of the first wiring 120, the conductive layer 130, the second wiring 140, 150 can be reduced. That is, the conductive layer 130 is in contact with the first wiring 120 through the first contact hole CH1 and the second wiring 140 is in contact with the conductive layer 130 through the second contact hole CH2. And the third wiring 150 directly contacts the second wiring 140. Accordingly, the touch signal received through the second wiring 140 is applied to the first wiring 120, the conductive layer 130, and the third wiring 150 in the same manner. Since the first wiring 120, the conductive layer 130 and the second wiring 140 are disposed on different planes from each other, the touch signal transferred to the second wiring 140 is electrically connected to the first wiring 120, 130, the second wiring 140, and the third wiring 150 in contact with the second wiring 140. Therefore, the widths of the first wiring 120, the conductive layer 130, the second wiring 140, and the third wiring 150 can be reduced. That is, since the touch signal is transmitted through three wires rather than one wire, even if the width of the first wire 120, the conductive layer 130, the second wire 140 and the third wire 150 is reduced, Lt; / RTI > can remain the same as before.

4 is a schematic cross-sectional view of a liquid crystal display according to a comparative example for explaining the effect of preventing corrosion of a conductive layer in a liquid crystal display device according to an embodiment of the present invention. The liquid crystal display according to the comparative example of FIG. 4 has the same structure as that of the first embodiment shown in FIGS. 1 to 3 except that a part of the upper surface of the conductive layer 430 is exposed in the region between the adjacent first contact holes CH1. Is the same as the liquid crystal display device 100 according to the embodiment. Therefore, redundant description thereof will be omitted.

Referring to FIG. 4, in the process of exposing the second planarization layer 414, a portion 414b of the second planarization layer 414 is separated and a second contact hole CH2, which is larger than the first contact hole CH1, Can be formed. Specifically, the second planarization layer 414 is formed by applying photoacrylic on the first planarization layer 413, and using a shadow mask exposing an area corresponding to the first contact hole CH1, . ≪ / RTI > In this case, if the amount of exposure is increased due to a process error, a problem may arise that a part 414b of the second planarization layer 414 is separated. The upper surface of the conductive layer 430 is exposed at the portion where the second planarizing layer 414 is separated from the second planarizing layer 414 as the portion 414b of the second planarizing layer 414 is separated.

On the other hand, the second wiring 440 and the third wiring 450 are formed so as to cover only the lower end portions of the first contact region and the second contact region. For example, as shown in FIG. 2, a plurality of first contact holes CH1 are arranged in four rows in the first contact area C / A1 and the second contact area C / A2. The second wiring 440 and the third wiring 450 are formed so as to cover the first contact holes CH1 of the lower two rows in the first contact area C / A1 and the second contact area C / . 4, the conductive layer 430, the second wiring 440, and the third wiring 450 are disposed on a plane higher than the plane where the first wiring 420 is disposed. As described above, the data driving circuit is mounted in the upper part of the bezel region of the substrate 410 in the COG or TCP mode. The data driving circuit is connected to the display pad portion and the wirings connecting the display pad portion and the data driving circuit may be disposed on the same plane as the first wirings 420 or on a lower plane than the first wirings 420 have. In this case, since the data driving circuit directly contacts the wiring extended from the display pad portion, the conductive layer 430, which is disposed on the plane higher than the first wiring 420 in the upper portion of the bezel region where the data driving circuit is disposed, The second wiring 440 and the third wiring 450 may not be disposed. That is, when the conductive layer 430, the second wiring 440, and the third wiring 450 are formed in the upper portion of the bezel region, the data driving circuit may be formed in the same plane as the first wiring 420, 420 may not be in direct contact with pad portions disposed on a lower plane. Therefore, the conductive layer 430, the second wiring 440, and the third wiring 450 may not be formed in the upper portion of the bezel region.

In addition, when the second wiring 440 and the third wiring 450 are deposited on the entire surface of the substrate 410, a large amount of material for forming the second wiring 440 and the third wiring 450 may be consumed The material for forming the second wiring 440 and the third wiring 450 may not be deposited in the upper portion of the bezel region to reduce the material cost. If the portion 414b of the second planarization layer 414 does not fall off, the top surface of the conductive layer 430 is not exposed unexpectedly. However, a portion of the top surface of the conductive layer 430 may be unexpectedly exposed as part 414b of the second planarization layer 414 is dislodged.

On the other hand, a material for forming the second wiring 440 is deposited in a state in which a part of the top surface of the conductive layer 430 is exposed. For example, a material for forming the second wiring 440 may be formed so as to cover the first contact hole CH1 of a part of the plurality of first contact holes CH1. In this case, the upper surface of the conductive layer 430 is exposed in the region where the part 414b of the second planarization layer 414 is separated, and the upper surface of the conductive layer 430 is made of a material for forming the second wiring 440 May not be deposited.

Then, a photoresist may be applied on the material for forming the second wiring 440 and exposure may be performed. As the exposure is performed, the photoresist is formed in a photoresist pattern corresponding to the second wiring 440. Thereafter, an etchant, which is a strongly acidic liquid, flows in between the photoresist patterns, and an etching process is performed. In this case, the second wiring 440 exposed between the photoresist patterns can be etched. Thereafter, the third wiring 450 is formed in the same manner.

Meanwhile, in the process of etching the second wiring 440, the region corresponding to the second wiring 440 may be protected from the etchant by the photoresist pattern, but the region exposed between the photoresist patterns is not protected from the etchant can not do it. Since the upper surface of the conductive layer 430 is exposed in the region exposed by the plurality of first contact holes CH1, the upper surface of the conductive layer 430 may be corroded or damaged by the etchant have. In particular, when the conductive layer 430 is made of aluminum having a low resistance, the conductive layer 430 can be rapidly corroded by an etchant having a strong acidity. In order to prevent this, the region corresponding to the first contact hole CH1 may be covered with a photoresist pattern. In this case, the exposed conductive layer 430 in the region corresponding to the first contact hole CH1 can be protected from the etchant by the photoresist pattern. However, when the portion 414b of the second planarization layer 414 is separated from the region between the adjacent two first contact holes CH1, the portion 414b of the second planarization layer 414 is separated from the region The upper surface of the conductive layer 430 may not be protected. That is, the photoresist pattern is disposed so as to cover the region corresponding to the first contact hole CH1 and not disposed so as to cover the region between the adjacent first contact holes CH1. Thus, the upper surface of the conductive layer 430 is exposed in the region where the portion 414b of the second planarization layer 414 is separated.

In this case, the upper surface of the conductive layer 430 may be exposed to the etchant for etching the second wiring 440 and the third wiring 450, and the upper surface of the conductive layer 430 may be exposed by the etchant, Lt; / RTI > The conductive layer 430 is a member for reducing contact resistance between the first wiring 420 and the second wiring 440. When the conductive layer 430 is corroded or damaged, The resistance can be increased. In this case, the contact resistance between the conductive layer 430 and the first wiring 420 increases, resulting in a problem that the overall resistance of the wiring increases.

3, the liquid crystal display 100 according to an exemplary embodiment of the present invention includes a second wiring 140 and a third wiring 150 formed to cover all the second contact holes CH2, . That is, the material for forming the second wiring 140 and the third wiring 150 may be deposited so as to cover both the first contact region C / A1 and the second contact region C / A2. In this case, even if a part of the second planarization layer 114 is separated from the adjacent first contact holes CH1, the conductive layer 130 is protected by the material for forming the second wiring 140 , The corrosion or damage of the conductive layer 130 can be minimized.

As a result, since the liquid crystal display 100 according to the embodiment of the present invention includes the second wiring 140 and the third wiring 150 arranged to cover all the second contact holes CH2, The corrosion or damage of the substrate 130 can be minimized. That is, even if a part of the second planarization layer 114 is separated in the process of forming the second contact hole CH2, the material for forming the second wiring 140 and the third wiring 150 may be a material The conductive layer 130 is formed to cover the entire second contact hole CH2 formed larger than the hole CH1 in the subsequent process of etching the second wiring 140 and the third wiring 150. Therefore, 140, and the third wiring 150. [0050] Therefore, the corrosion or damage of the conductive layer 130 can be minimized, and the problem of increase in wiring resistance due to damage of the conductive layer 130 can be minimized.

While the present invention has been described with reference to a common wiring for transmitting a common voltage and a wiring resistance increase in a touch wiring for transmitting a touch signal, the concept of the present invention can be applied to all contact areas of other wirings . That is, the liquid crystal display 100 includes various wirings, and according to the wiring design method of the liquid crystal display 100, the respective wirings can be contacted at various points with other wirings disposed on different planes from each other. The problem of tearing off a portion of the second planarization layer 114 can occur at various points where the wirings are in contact with each other, so that the advantages of the present invention can be applied to various points where the wirings are in contact with each other.

The liquid crystal display device according to an embodiment of the present invention includes a data driving circuit DI or a gate driving circuit DI connected to a display pad line of a display pad unit DP, (GIP). In this case, the link wiring can be connected to the display pad wiring in the contact area located at the upper end of the bezel area B / A, and the connection structure of the link wiring and the display pad wiring can be connected to the first contact Can be substantially the same as that of the region C / A1. The liquid crystal display device according to an embodiment of the present invention may further include a driving circuit for driving the driving signal generated by the data driving circuit DI or the gate driving circuit GIP to the signal wiring arranged in the active area A / . ≪ / RTI > In this case, the link wiring can be connected to the signal line in the outer area of the active area A / A, that is, the contact area located at the lower end of the bezel area B / A. The connection structure of the link wiring and the signal wiring can be substantially the same as that of the first contact area C / A1 shown in Figs.

5 is a schematic cross-sectional view for explaining a liquid crystal display device according to another embodiment. The liquid crystal display of FIG. 5 includes the liquid crystal display 100 of FIG. 3 except that it further includes a third wiring 550 directly contacting the conductive layer 130 in a region corresponding to the first contact hole CH1. The description thereof will be omitted.

Referring to FIG. 5, the third wiring 550 directly contacts the third conductive layer 130 through the second contact hole CH2. The third wiring 550 directly contacts the exposed top surface of the conductive layer 130 in the region corresponding to the first contact hole CH1 and contacts the first wiring 120 and the second wiring 120 through the conductive layer 130. [ 3 wiring 550 are electrically connected. In this case, the second wiring 540 is not arranged in the region corresponding to the first contact hole CH1 but is patterned so as to have an opening corresponding to the first contact hole CH1.

The contact resistance of the conductive layer 130 in the contact region can be further reduced when the third wiring 550 directly contacts the conductive layer 130 in the first contact hole CH1. Specifically, the second wiring 540 is made of a transparent conductive oxide, and the transparent conductive oxide has a higher resistance than the third wiring 550 made of a metal. When the conductive layer 130 directly contacts the third wiring 550, the conductive layer 130 made of a metal having a low resistance forms a direct electrical contact with the third wiring 550, The contact resistance of the conductive layer 130 can be lowered compared with the case where the second wiring 540 is electrically contacted.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: liquid crystal display
110, 410: substrate
111, 411: gate insulating layer
112, 412: an interlayer insulating layer
113, 413: a first planarization layer
114, 414: a second planarization layer
120, 420: first wiring
130, 430: conductive layer
140, 440, 540: second wiring
150, 450, 550: Third wiring
414b: the torn portion of the second planarization layer
CH1: first contact hole
CH2: second contact hole
DP:
TP: Touch pad part
DI: Data driving circuit
GIP: Gate driving circuit
A / A: active area
B / A: Bezel area
C / A1: first contact area
C / A2: second contact area

Claims (14)

A substrate comprising an active region and a bezel region surrounding the active region;
A plurality of thin film transistors arranged in an active region of the substrate;
A first planarization layer covering the plurality of thin film transistors;
A second planarization layer disposed on the first planarization layer;
A common electrode disposed on the second planarization layer in the active region;
A first wiring disposed under the first planarization layer in the bezel region;
A conductive layer disposed on the first planarization layer in the bezel region and in contact with the first wiring through a plurality of first contact holes provided in the first planarization layer; And
And a second wiring in contact with the conductive layer through a second contact hole provided in the second planarization layer in a region between the at least two first contact holes adjacent to each other among the plurality of first contact holes in the bezel region The liquid crystal display device. The method according to claim 1,
The at least two first contact holes adjacent to each other are exposed by the second contact holes and the second wiring covers the at least two first contact holes through the second contact holes. The method according to claim 1,
Wherein the conductive layer is made of metal,
The second wiring may be formed of a transparent conductive oxide (TCO)
Wherein the first planarizing layer and the second planarizing layer are made of photoacid (PAC). The method of claim 3,
And a third wiring in contact with the second wiring,
The second wiring exposes an upper surface of the conductive layer in a region corresponding to the plurality of first contact holes,
And the third wiring is in contact with an upper surface of the conductive layer exposed in a region corresponding to the plurality of first contact holes. The method of claim 3,
And a distance between centers of the at least two first contact holes is 22 占 퐉 or less. A substrate comprising an active region and a bezel region surrounding the active region;
A plurality of thin film transistors arranged in an active region of the substrate;
A first planarization layer covering the plurality of thin film transistors;
A second planarization layer disposed on the first planarization layer;
A common electrode disposed on the second planarization layer in the active region;
A first wiring disposed under the first planarization layer in the bezel region;
A conductive layer disposed on the first planarization layer in the bezel region and in contact with the first wiring through a plurality of first contact holes provided in the first planarization layer; And
And at least a portion of the upper surface of the conductive layer, which is provided in the second planarization layer in the bezel region and is exposed through a second contact hole corresponding to at least two adjacent first contact holes among the plurality of first contact holes, And a second wiring. The method according to claim 6,
And the second wiring and the common electrode are made of a transparent conductive oxide. 8. The method of claim 7,
Further comprising a third wiring which is in contact with the second wiring and is made of a metal,
Wherein the common electrode functions as a touch electrode for sensing a touch input of a user. 9. The method of claim 8,
Wherein the third wiring, the second wiring, the conductive layer, and the first wiring are configured to transmit a touch signal of the touch electrode. A substrate including a display region and a non-display region;
A plurality of thin film transistors arranged in a display region of the substrate;
A first planarization layer covering the plurality of thin film transistors;
A second planarization layer disposed on the first planarization layer;
A common electrode disposed on the second planarization layer in the display region;
A signal wiring connected to the plurality of thin film transistors or the common electrode and configured to transmit a driving signal; And
And a link wiring connected to the signal wiring in the first contact region,
Wherein the link wiring in the first contact area comprises:
A first wiring disposed under the first planarization layer;
A first conductive layer disposed on the first planarization layer and in contact with the first wiring through a plurality of first contact holes of the first planarization layer; And
And a second wiring in contact with the conductive layer through a second contact hole of the second planarization layer in a region between at least two first contact holes adjacent to each other among the plurality of first contact holes. 11. The method of claim 10,
And a pad wiring connected to the pad disposed in the non-display area to receive a control signal from the pad,
The link wiring is connected to the pad wiring at a second contact region,
In the second contact area,
A second conductive layer disposed on the first planarization layer and in contact with the first wiring through a plurality of third contact holes of the first planarization layer; And
And a second wiring in contact with the conductive layer through a fourth contact hole of the second planarization layer in an area between at least two third contact holes adjacent to each other among the plurality of third contact holes. 12. The method of claim 11,
The at least two first contact holes adjacent to each other in the first contact region are exposed by the second contact hole,
The at least two third contact holes adjacent to each other in the second contact region are exposed by the fourth contact holes,
The second wiring covers the at least two first contact holes through the second contact hole in the first contact region,
And the second wiring covers the at least two third contact holes through the fourth contact holes in the second contact region. The method of claim 3,
And a third wiring in contact with the second wiring,
The second wiring exposes an upper surface of the first conductive layer in an area corresponding to the plurality of first contact holes and exposes an upper surface of the second conductive layer in an area corresponding to the plurality of third contact holes ,
Wherein the third wiring is in contact with the upper surface of the first conductive layer in a region corresponding to the plurality of first contact holes and in contact with the upper surface of the second conductive layer in a region corresponding to the plurality of third contact holes, Display device. 14. The method of claim 13,
A distance between centers of the at least two first contact holes is 22 占 퐉 or less,
And a distance between centers of the at least two third contact holes is 22 占 퐉 or less.

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