KR20170064125A - Display device - Google Patents

Abstract

A display device according to the present invention includes a mold-releasing active region, a bezel region, a gate driving circuit, a first conductive layer, and an auxiliary conductive layer. The emitter active region has pixels delimited by scan lines and data lines. The bezel region is located outside the active region. The gate driving circuit is disposed in the bezel region, and generates a scan pulse. The first conductive layer is disposed in the bezel region, and a scan pulse is applied from the gate driving circuit. The auxiliary conductive layer is disposed in the bezel region and electrically connects the first conductive layer to the scan line to transfer the scan pulse from the first conductive layer to the scan line. At this time, the first conductive layer and the scan line are separated from each other on the same layer. The auxiliary conductive layer is disposed under the first conductive layer and the scan line. At least one insulating layer is interposed between the auxiliary conductive layer and the first conductive layer and the scan line.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device having a release active region.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. As a result, the organic light emitting diode (OLED), the quantum dot display (QDD), the liquid crystal display (LCD) and the plasma display panel (PDP) The use of the same display device is increasing.

In addition, in recent years, flexible display devices have been commercialized. Flexible display devices are available in various designs and have advantages in portability and durability. Such flexible display devices are being applied not only to mobile devices such as smart phones and tablet PCs but also to various fields such as TVs (Television), automobile displays, and wearable devices. Such a flexible display device is required to be in various shapes other than a conventional rectangular shape in order to be applied to various fields.

Since the mold release display device has a different shape from that of the conventional display devices, the arrangement of various structures constituting the display device can not help but be changed. For example, in the mold release display device, a line array structure different from that of the conventional display device is required. That is, a new line array (not shown) which is arranged in accordance with the characteristics of the display device and can be efficiently arranged so that short-circuit defects do not occur between signal lines to which different signals Structure development is required.

The present invention provides a display device in which defects that may occur between signal lines to which different signals are applied are minimized by differently arranging signal lines passing through a bezel region.

In order to achieve the above object, a display device according to the present invention includes a release active region, a bezel region, a first conductive layer, and an auxiliary conductive layer. The emitter active region has pixels delimited by scan lines and data lines. The bezel region is located outside the active region. The first conductive layer is disposed in the bezel region, and a scan pulse is applied from the gate driving circuit. The auxiliary conductive layer is disposed in the bezel region and transfers the scan pulse from the first conductive layer to the scan line. At this time, the auxiliary conductive layer is disposed under the first conductive layer and the scan line with at least one insulating layer therebetween.

The auxiliary conductive layer may be thinner than the first conductive layer.

At least one of the auxiliary conductive layers connected to the scan lines may be different in length from the other.

The display device according to the present invention may further include a link region and a second conductive layer. The link region is defined between the gate drive circuit and the active region, and the auxiliary conductive layer is disposed. The second conductive layer is disposed over the first conductive layer and the scan line with at least one insulating layer therebetween, and receives the data voltage from the data line. At this time, the second conductive layer overlaps the auxiliary conductive layer in the link region to form the first capacitor.

The display device according to the present invention may further include a third conductive layer. The third conductive layer is disposed on the second conductive layer with at least one insulating layer therebetween. At this time, the second conductive layer overlaps the third conductive layer in the link region to form the second capacitor.

One end of the auxiliary conductive layer is connected to the first conductive layer through the first contact hole passing through the insulating layer and the other end of the auxiliary conductive layer is connected to the scan line through the second contact hole passing through the insulating layer have.

A preferred embodiment of the present invention is a method for improving the step coverage defect on the conductive layer by changing the interlayer line structure between the gate drive circuit and the active region and improving the short circuit between the conductive layers to which different signals are applied circuit can be prevented.

Further, when the shape of the active area is a variation, the lengths of the scan lines may be different depending on their positions. The preferred embodiment of the present invention can change the interlayer line structure between the gate driving circuit and the active area to facilitate compensation of load deviation due to the difference in length of the scan lines formed in the active area.

1 is a block diagram showing a display device according to the present invention.
2 is a view showing a display panel according to the present invention.
Figure 3 is a simplified view of a portion of a pixel array.
Figs. 4 and 5 are views showing various connection forms of the gate driving circuit and the scan lines when the GIP circuit is disposed on both sides of the display panel.
6 is a block diagram schematically showing a connection relationship between a gate driving circuit and an active region.
7 is a diagram showing an example in which a shift register of a gate driving circuit is implemented by a GIP circuit.
8 is a view schematically showing one stage circuit configuration in the GIP circuit.
9 is a schematic diagram showing pixels in the active area.
10 is an equivalent circuit diagram showing an example of a circuit configuration diagram in the pixel shown in FIG.
11 is a waveform diagram showing the operation of the equivalent circuit diagram shown in Fig.
12 is a cross-sectional view for explaining the interlayer arrangement structure of the link area.
13 is a block diagram schematically illustrating a connection relationship between a gate driving circuit and an active region according to a preferred embodiment of the present invention.
Figs. 14 to 16 are cross-sectional views schematically showing an inter-layer arrangement structure of a link region to explain a preferred embodiment of the present invention.
17 is a view for explaining effects according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Terms including ordinals, such as first, second, etc., may be used to describe various elements, but the elements are not limited to these terms. The terms are used only for the purpose of distinguishing one component from another.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The display device according to the present invention can be applied to a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light emitting diode Display, OLED, electrophoresis (EPD), or the like. Hereinafter, for convenience of explanation, a case where the display device includes an organic light emitting diode element will be described as an example.

1 is a block diagram showing a display device according to the present invention. 2 is a view showing a display panel according to the present invention. Figure 3 is a simplified view of a portion of a pixel array. Figs. 4 and 5 are views showing various connection forms of the gate driving circuit and the scan lines when the GIP circuit is disposed on both sides of the display panel.

1 to 3, a display device according to the present invention includes a display driving circuit and a display panel 110. [

The display driving circuit includes a gate driving circuit 120, a data driving circuit 140, and a timing controller 30, and writes the video data voltage of the input image to the pixels of the display panel 110. The data driving circuit 140 converts the digital video data RGB input from the timing controller 30 into an analog gamma compensation voltage to generate a data voltage. The data voltage output from the data driving circuit 140 is supplied to the data lines DL. The gate driving circuit 120 sequentially supplies the scan pulses synchronized with the data voltages to the scan lines GL to select the pixels of the display panel 110 into which the data voltages are written.

The timing controller 30 inputs timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK input from the host system 20 And synchronizes the operation timings of the data driving circuit 140 and the gate driving circuit 120 with each other. The data timing control signal for controlling the data driving circuit 140 includes a source sampling clock (SSC), a source output enable (SOE) signal, and the like. The gate timing control signal for controlling the gate driving circuit 120 includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE .

The host system 20 may be implemented as any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system 20 converts the digital video data RGB of the input image into a format suitable for display on the display panel 110, including a system on chip (SoC) with a built-in scaler. The host system 20 transmits the timing signals Vsync, Hsync, DE, and MCLK to the timing controller 30 together with the digital video data.

The shape of the substrate SUB forming the outer surface of the display panel 110 is not limited to a specific shape. That is, although the substrate SUB has a substantially circular shape in the drawing, it is not limited thereto. The plane shape of the substrate SUB may have various planar shapes such as a polygonal shape, a circular shape, and an elliptical shape. Hereinafter, the case where the shape of the substrate SUB is circular will be described as an example.

The display panel 110 includes an active area AA and a bezel area BZ. The active area AA is a deformed shape that is not a conventional rectangular shape. The planar shape of the active area AA may be the same as the planar shape of the substrate SUB, but may be different. For example, a circular active area AA may be defined on the display panel 110 having a rectangular outline. In the following description, the case where the active area AA is circular will be described as an example.

The active area AA includes data lines DL and scan lines GL intersecting with the data lines DL and data lines DL and scan lines GL defined in a matrix form Pixels 10. Data of the input image is displayed in the active area AA. The active area AA supplies a reference voltage line (reference line, "REF line") for supplying the reference voltage Vref to the pixels 10, a high potential power supply voltage VDD to the pixels 10 (Hereinafter, referred to as "VDD line"). The scan lines GL supply scan pulses to the pixels 10. The scan lines GL include first scan lines GL1 to which a first scan pulse SCAN1 is applied and second scan lines GL2 to which a second scan pulse SCAN2 is applied. The data lines DL transfer the data voltages to the pixels 10. [

Each of the pixels 10 is divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels 10 may further include a white subpixel. A data line DL, a scan line GL, a REF line, and a VDD line are connected to each of the pixels 10.

The bezel region BZ is disposed outside the active region AA. The bezel region BZ includes a data routing unit 111, a multiplexer 160, a high potential routing unit 112, a reference voltage routing unit 113, a gate driving circuit (GIC) 120, 114). In order to prevent mutual shrt circuit, each of the above-described components is preferably spaced apart from each other by a predetermined distance. In order to improve the aesthetics of the display device, it is desirable to minimize the bezel area BZ by appropriately separating and arranging the above structures.

The data routing part 111 extends from the pad part 180 to both sides of the bezel area BZ and can be defined along the shape of the active area AA. A plurality of data routing lines are arranged in the data routing unit 111. The data routing lines are electrically connected to the data driving circuit 140 to supply the data voltages output from the data driving circuit 140 to the pixels 10. [ The data routing lines formed in the data routing unit 111 are electrically connected to the pads provided in the pad unit 180 and correspond to the output channels of the data driving circuit 140 on a one-to-one basis.

The data driving circuit 140 may be mounted on the flexible circuit board 140a and electrically connected to the pad unit 180 through an anisotropic conductive film (ACF). The flexible circuit board 140a may be bent toward the back of the display panel 110 and the data driving circuit 140 may be positioned at the back of the display panel 110. [

A multiplexer (MUX) 160 is disposed between the active area AA and the data routing unit 111. The multiplexer 160 receives the data voltages from the data routing lines provided in the data routing unit 111 and distributes the data voltages to the data lines DL of the active area AA. One end of the multiplexer 160 is electrically connected to the data routing lines of the data routing unit 111 and the other end of the multiplexer 160 is electrically connected to the data lines DL of the active area AA. The multiplexer 160 divides the data signal output from one output terminal in the data driving circuit 140 into a plurality of data lines DL in response to the mux enable signal. Accordingly, the multiplexer 160 reduces the number of output terminals of the data driving circuit 140 and the number of data routing lines connected thereto.

It is preferable that the data routing unit 111 and the multiplexer 160 are disposed adjacent to the active area AA. The data routing unit 111 and the multiplexer 160 may be disposed only in one of the upper half and lower half of the active area AA. The upper half of the active area AA refers to the upper area with respect to the horizontal line passing through the center of the active area AA. The lower half of the active area AA refers to a lower area with respect to a horizontal line passing through the center of the active area AA. It is preferable that the data routing unit 111 and the multiplexer 160 are disposed adjacent to the data driving circuit 140.

An AP (Auto Probe) switch circuit 115 may be further provided at one side of the bezel area BZ. The AP switch circuit 115 is electrically connected to the scan lines GL and the data lines DL of the active area AA and operates to check the lighting of the pixel 10. [

The high potential routing portion 112 extends from the pad portion 180 to both sides of the bezel region BZ and can be defined along the shape of the active region AA. The high-potential routing unit 112 may be defined outside the data routing unit 111. A VDD routing line is disposed in the high potential routing portion 112. [ The VDD routing line is supplied with the high potential power supply voltage (VDD) output from the power generation unit. The VDD routing line is electrically connected to the VDD lines of the active area AA, respectively. The high-potential power supply voltage VDD is transmitted to the VDD lines through the VDD routing line, respectively. The high-potential power supply voltage VDD is a power required to drive a driving thin film transistor (hereinafter referred to as "TFT ") or an organic light emitting diode (OLED) .

The reference voltage routing part 113 extends from the pad part 180 to both sides of the bezel area BZ and can be defined along the shape of the active area AA. The reference voltage routing unit 113 may be defined outside the data routing unit 111. The reference voltage routing unit 113 is provided with a REF routing line. The REF routing line receives the reference voltage Vref output from the power generating unit. The REF routing line is electrically connected to the REF lines of the active area AA, respectively. The reference voltage Vref is transmitted to each of the REF lines through the REF routing line. The reference voltage Vref is a power required to reset the potential of the TFT and the OLED when the compensating pixel is driven. The reference voltage Vref may be an initial (VINI) power source.

One of the high potential routing portion 112 and the reference voltage routing portion 113 extends from the pad portion 180 and is located in the upper half region and the other extends from the pad portion 180, And the lower hemisphere. However, the present invention is not limited thereto, and both the high-potential routing unit 112 and the reference voltage routing unit 113 may extend from the pad unit 180 and be located in the upper half and lower half. As another example, when the pad portion connected to the power generating portion is provided on both the upper and lower sides, one of the high potential routing portion 112 and the reference voltage routing portion 113 extends from the upper pad portion, And the other may extend from the lower pad portion and be located in the lower hemisphere. The VDD routing line and the REF routing line, which are disposed in the high potential routing part 112 and the reference voltage routing part 113, respectively, are preferably formed to have a sufficient area to stably maintain the voltage level.

When the active area AA is a variant, the power supply line (REF line or VDD line) of the active area AA is different in length depending on the formation position. That is, the lengths of the power supply lines disposed in the central part and the outer part of the active area AA are different from each other. Since the power supply lines have different lengths depending on their forming positions, the number of pixels connected to each power supply line also differs. Accordingly, a load deviation may occur between the power supply lines.

In order to prevent luminance uniformity degradation due to load deviation, a high-potential link line 117 and a reference voltage link line 118 are formed in an area adjacent to the active area AA. The high-potential link line 117 and the reference voltage link line 118 refer to a line for forming the equipotential. The VDD routing lines and the VDD lines corresponding to each other are electrically connected to each other by the VDD link channels. The high-potential link line 117 is disposed adjacent to the active area AA to electrically connect the VDD link channels. The REF routing lines and the REF lines corresponding to each other are electrically connected by the REF link channels, respectively. The reference voltage link line 118 is disposed adjacent to the active area AA to electrically connect the REF link channels. The high potential power supply voltage VDD and the reference voltage Vref can be uniformly supplied to the pixel 10 of the active area AA by forming the high potential link line 117 and the reference voltage link line 118. [

When the active area AA is a mold release, the lengths of the data lines DL of the active area AA are different depending on the formation position. That is, the lengths of the data lines DL arranged in the central part and the outer part of the active area AA are different from each other. Since the lengths of the data lines DL are different depending on the forming positions, the number of pixels connected to the data lines DL also differs for each data line DL. The capacitor difference may occur due to the difference in the lengths of the data lines DL, which causes a non-uniformity of luminance and the like, thereby deteriorating the display quality of the display device.

To prevent this, a compensation capacitor 116 may be formed in the bezel region BZ. As shown, the compensation capacitor 116 may be formed in the reference voltage routing unit 113. However, the present invention is not limited thereto. The compensation capacitor 116 may be formed by overlapping the first capacitor electrode and the second capacitor electrode with at least one insulating layer interposed therebetween. The first capacitor electrode is electrically connected to the data line DL of the active area AA. When the compensation capacitor 116 is formed in the reference voltage routing unit 113, the second capacitor electrode may be a REF routing line.

The compensation capacitor 116 may be a dual capacitor formed in the vertical direction. The first capacitor electrode and the second capacitor electrode overlap each other to form a first capacitor. In the lower portion, the first capacitor electrode and the third capacitor electrode overlap each other to form a second capacitor. In this case, the third capacitor electrode may be an electrode to which a scan pulse supplied from the neighboring gate driving circuit 120 is applied.

The compensation capacitor 116 may have a plurality of compensation capacitors 116, and at least one of the plurality of compensation capacitors 116 may have a capacitance value different from the other compensation capacitors 116. That is, the compensation capacitors 116 are provided to have an appropriate capacitance value capable of compensating for the deviation according to the length of the corresponding data line DL.

The gate driving circuit 120 includes a shift register. A shift register includes stages that are connected in a dependent manner. The stages output the scan pulses SCAN1 and SCAN2 in response to the start pulse GSP and shift the outputs of the scan pulses SCAN1 and SCAN2 according to the shift clocks GCLK1 to GCLK4. The gate driving circuit 120 may be disposed directly on the bezel area BZ of the display panel 110 according to the scheme of a gate-driver In Panel (GIP) circuit.

The gate drive circuit 120 may be disposed along the shape of the active area AA and spaced apart from the active area AA by a predetermined distance on the bezel area BZ. The gate driving circuit 120 supplies scan pulses to the scan lines GL. The gate drive circuit 120 may be disposed on each side of the bezel area BZ on the active area AA. However, the present invention is not limited thereto, and the gate driving circuit 120 may be disposed at any side of the bezel region BZ. The gate driving circuit 120 divides the scan lines GL into predetermined groups and supplies scan pulses to the divided groups.

4, the gate driving circuit 120 includes a first GIP circuit GIP (L) arranged on one side of the display panel 110 and a second GIP circuit GIP (L) disposed on the other side of the display panel 110 And a second GIP circuit (GIP (R)).

Each of the first and second GIP circuits GIP (L) and GIP (R) may be connected to all the scan lines GL1 to GLn. Each of the first and second GIP circuits GIP (L) and GIP (R) receives the start pulse GSP and simultaneously outputs a scan pulse. Therefore, the scan pulses output from the first and second GIP circuits GIP (L) and GIP (R) are simultaneously applied to both ends of the same scan line GL.

5, the first GIP circuit GIP (L) is connected to the first group of scan lines GL to sequentially apply scan pulses to the first group of scan lines GL. Supply. The second GIP circuit GIP (R) is connected to the second group of scan lines GL to sequentially supply scan pulses to the second group of scan lines GL. The first group of scan lines GL may be odd-numbered scan lines GL1, GL3, ..., GL2n-1. The second group of scan lines GL may be the even scan lines GL2, GL4, ..., GL2n. The start pulse GSP may be supplied to the first and second GIP circuits GIP (L) and GIP (R) with a predetermined time difference. Therefore, there may be a predetermined time difference between the scan pulse output timing and the carry signal output timing of the first and second GIP circuits 120 (GIP (L), GIP (R)). For example, After the first scan pulse is supplied from the first scan line 120 (GIP (L)) to the first scan line (GL1), a second scan pulse is applied from the second GIP circuit (GIP And may be supplied to the line GL2.

The low potential routing portion 114 extends from the pad portion 180 and can be defined along the shape of the active region AA. The low-potential routing unit 114 receives the low-potential power supply voltage VSS from the power generation unit and supplies the low-potential power supply voltage VSS to the pixel 10.

  Hereinafter, the connection relationship between the gate driving circuit 120 and the pixel 10 in the active area AA will be described with reference to FIGS. 6 to 12. FIG. 6 is a block diagram schematically showing a connection relationship between a gate driving circuit and an active region. 7 is a diagram showing an example in which a shift register of a gate driving circuit is implemented by a GIP circuit. 8 is a view schematically showing one stage circuit configuration in the GIP circuit.

Referring to FIG. 6, the gate driving circuit 120 may be formed on the substrate SUB of the display panel 110 in a GIP manner. Active region AA includes pixels 10 defined by scan lines GL and data lines DL. The gate driving circuit 120 supplies the scan pulses SCAN1 and SCAN2 to the scan lines GL of the active area AA under the control of the timing controller 30. [

With further reference to Figures 7 and 8, the GIP circuit is schematically described. 7 and 8 show one example of the GIP circuit, and it should be noted that the present invention is not limited to this.

The gate driving circuit 120 supplies a first scan pulse SCAN1 to the first scan lines GL and a second scan pulse SCAN2 to the second scan lines GL. The scan pulses SCAN1 and SCAN2 are synchronized with the data voltage. The GIP circuit 120 includes a shift register. The shift register includes the stages S (N-2) to S (N + 2) that are connected in a dependent manner. The stages S (N-2) to S (N + 2) start outputting the scan pulses SCAN1 and SCAN2 in response to the start pulse Vst and output the outputs in accordance with the shift clocks GCLK1 to GCLK4 Shift. Output signals sequentially output from the stages S (N-2) to S (N + 2) are supplied to the scan lines GL as scan pulses SCAN1 and SCAN2. The output of each of the stages S (N-2) to S (N + 2) is input as a start pulse Vst of the next stage and its output is input to the previous stage as a reset signal . The stages may output a carry signal different from the scan pulse and supply the start pulse Vst to the next stage. The carry signal is input as the next stage start pulse, and the reset signal discharges the output of the previous stage. Scan timing control signals such as a start pulse Vst and shift clocks GCLK1 to GCLK4 are input to the stages S (N-2) to S (N + 2) through the scan lines GL. Each of the stages S (N-2) to S (N + 2) includes a Q node Q for controlling a pull-up transistor Tu, a pull-down transistor Td, A QB node QB for controlling the charge and discharge of the Q node QB, and a switch circuit for controlling charge and discharge of the Q node QB and the QB node QB.

9 to 11, a circuit configuration in a pixel is schematically described. 9 is a schematic diagram showing pixels in the active area. 10 is an equivalent circuit diagram showing an example of a circuit configuration diagram in the pixel shown in FIG. 11 is a waveform diagram showing the operation of the equivalent circuit diagram shown in Fig.

9, a plurality of data lines DL and a plurality of gate lines GL are intersected with the display panel DIS, and the pixels 10 are arranged in a matrix form for each of the intersection areas . Each of the pixels 10 includes an OLED, a driving TFT DT for controlling the amount of current flowing in the OLED, and a programming portion SC for setting the gate-source voltage of the driving TFT DT.

The programming portion SC may include at least one switch TFT and at least one storage capacitor. The switch TFT is turned on in response to the scan pulse from the scan line GL, thereby applying the data voltage from the data line DL to one electrode of the storage capacitor. The driving TFT DT controls the amount of current supplied to the OLED according to the magnitude of the voltage charged in the storage capacitor to control the amount of light emitted from the OLED. The amount of light emission of the OLED is proportional to the amount of current supplied from the driving TFT DT. These pixels are connected to a high potential power source VDD and a low potential power source VSS, and are supplied with a high potential power source and a low potential power source, respectively, from a power source not shown. The TFTs constituting the pixel may be implemented as a p-type or an n-type. In addition, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or an oxide. The OLED includes an anode electrode ANO, a cathode electrode CAT, and an organic compound layer interposed between the anode electrode ANO and the cathode electrode CAT. The anode electrode ANO is connected to the driving TFT DT.

Referring to FIG. 10, the pixel may be composed of a transistor 6C (Capacitor). It should be noted, however, that the pixel structure of the present invention is not limited to the 6T 1C structure. That is, the present invention can include all OLED pixel structures using a method of regulating the current flowing in the OLED using a driving TFT.

10 and 11, one frame period of the pixel 10 can be divided into an initialization period Ti, a sampling period Ts, and an emission period Te.

The first scan pulse Scan1 is generated at the ON level during the initialization period Ti and the sampling period Ts to turn the first TFT T1 on and turns off during the emission period Te Level so as to turn off the first TFT < RTI ID = 0.0 > T1. ≪ / RTI >

The second scan pulse Scan2 is generated at the ON level during the initialization period Ti and the emission period Te to turn on the second TFT T2 and is turned off during the sampling period Ts. Level and controls the second TFT T2 to be in the off state.

The OLED is connected between the fourth node N4 and the low potential power supply voltage VSS and emits light in accordance with the driving current applied from the driving TFT DT.

The driving TFT DT controls the driving current flowing in the OLED according to its gate-source voltage. The gate of the driving TFT DT is connected to the first node N1, the source is connected to the input terminal of the high potential power supply voltage VDD, and the drain is connected to the third node N3.

The first TFT T1 turns on / off the current path between the data line DL and the second node N2 in response to the first scan pulse Scan1. The gate of the first TFT T1 is connected to the first scan line GL, the source is connected to the data line DL, and the drain is connected to the second node N2.

The second TFT T2 turns on / off the current path between the first node N1 and the third node N3 in response to the first scan pulse Scan1. The gate of the second TFT T2 is connected to the first scan line GL, the source is connected to the first node N1, and the drain is connected to the third node N3.

The third TFT T3 turns on / off the current path between the input terminal of the reference voltage Vref and the fourth node N4 in response to the first scan pulse Scan1. The gate of the third TFT T3 is connected to the first scan line GL, the source thereof is connected to the input terminal of the reference voltage Vref, and the drain thereof is connected to the fourth node N4.

The fourth TFT T4 turns on / off the current path between the input terminal of the reference voltage Vref and the second node N2 in response to the second scan pulse Scan2. The gate of the fourth TFT T4 is connected to the second scan line GL, the source thereof is connected to the input terminal of the reference voltage Vref, and the drain thereof is connected to the second node N2.

The fifth TFT T5 turns on / off the current path between the third node N3 and the fourth node N4 in response to the second scan pulse Scan2. The gate of the fifth TFT T5 is connected to the second scan line GL, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The storage capacitor Cst is connected between the first node N1 and the second node N2.

During the initialization period Ti, the first to fifth TFTs T1 to T5 are turned on in response to the first and second scan pulses Scan1 and Scan2 at the ON level. During the initialization period Ti, the voltages of the first to fourth nodes N1 to N4 are initialized to the reference voltage Vref.

During the sampling period Ts, the first to third TFTs T1 to T3 maintain a turn-on state in response to the first scan pulse Scan1 at the ON level, whereas the fourth and fifth TFTs The TFTs T4 and T5 are turned off in response to the second scan pulse Scan2 of the OFF level. During the sampling period Ts, the data voltage Vdata is applied to the second node N2 through the data line DL. During the sampling period Ts, the potentials of the first and third nodes N1 and N3 become "VDD-Vth ". Vth indicates the threshold voltage of the driving TFT DT.

The emission period Te continues from the sampling period Ts to the initialization period Ti of the next frame. During the emission period Te, the first to third TFTs T1 to T3 are turned off in response to the first scan pulse Scan1 of the OFF level, and the fourth and fifth TFTs T4, T5 are turned on in response to the second scan pulse Scan2 of the ON level.

The reference voltage Vref is applied to the second node N2 during the emission period Te and the potential change Vref-Vdata of the second node N2 is reflected to the first node N1. During the emission period Te, the potential of the first node N1 is programmed to "(VDD-Vth) + (Vref-Vdata) ". Therefore, during the emission period Te, the gate-source voltage Vgs of the driving TFT DT is programmed to "Vdata-Vref + Vth". The OLED emits light by the driving current Ioled flowing through the OLED during the emission period Te to express the brightness of the input image.

An insulating layer including organic and / or inorganic insulating materials is interposed between the gate driving circuit 120 and the active area AA (hereinafter referred to as "link area") LN, Electrodes to which other signals (or voltages) are applied are disposed. For example, referring to the AR region of FIG. 2, the reference voltage routing unit 113, the compensation capacitor 116, and the AP switch circuit 115 may be provided in the link region LN. In this case, the reference voltage routing line to which the reference voltage Vref is applied, the capacitor electrode forming the compensation capacitor 116, and the AP switch circuit 115 elements may be disposed in the link region LN. The scan pulse supplied from the gate driving circuit 120 to the active area AA is transmitted through the first conductive layer M1 and the first conductive layer M1 passes through the link area LN.

Since a plurality of signal lines and driving elements to which different signals are applied are arranged in the link area LN, a proper layer design that can reduce the bezel area BZ while being spaced apart from each other so that they are not short-circuited A solution is required.

Specifically, the interlayer arrangement structure in the link area LN will be described with reference to FIG. 12 is a cross-sectional view for explaining the interlayer arrangement structure of the link area.

12, three conductive layers, i.e., a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3, to which different signals are applied, are formed on a substrate SUB And are disposed on different layers with layers therebetween.

A buffer layer BUF and a gate insulating film GI are formed on the substrate SUB. The first conductive layer M1 is formed on the gate insulating film GI. A first scan pulse is applied to the first conductive layer (M1) from the gate driving circuit (120). The first conductive layer (M1) extends from the gate drive circuit (120). The first conductive layer M1 is formed on the same layer as the scan line GL of the active area AA and is electrically connected to the scan line GL. The first conductive layer M1 and the scan line GL may extend from the gate driving circuit 120 as a body. The first scan pulse is transmitted from the gate driving circuit 120 to the scan line GL through the first conductive layer M1. The case where the first scan pulse is applied to the first conductive layer M1 has been described as an example, but the present invention is not limited thereto. The present invention may include all the cases where any one of the scan signals applied from the gate driving circuit 120 is applied to the first conductive layer M1.

The second conductive layer M2 is formed on the first conductive layer M1 with the first insulating layer IN1 therebetween. The second conductive layer M2 may be electrically connected to the data line DL of the active area AA to receive the data voltage. In this case, the second conductive layer M2 and the data line DL are formed in different layers. The data line DL is formed in the same layer as the third conductive layer M3 and is in contact with the second conductive layer M2 through the contact hole passing through the first insulating layer IN1. In the link region LN, the first conductive layer M 1 and the second conductive layer M 2 are overlapped with each other with the first insulating layer IN 1 interposed therebetween to form the first capacitor C 1. The first capacitor C1 functions as a compensation capacitor 116 provided to prevent luminance unevenness due to capacitor deviation of the data line DL.

The third conductive layer M3 is formed on the second conductive layer M2 with the second insulating layer IN2 interposed therebetween. The second conductive layer M2 may be a REF routing line to which the reference voltage Vref is applied. The third conductive layer M3 is formed on the same layer as the data line DL of the active area AA. When the second conductive layer M2 is electrically connected to the data line DL, the second conductive layer M2 and the third conductive layer M3 in the link region LN are sandwiched between the second insulating layer IN2 So that the second capacitor C2 is formed. The second capacitor C2 functions as a compensation capacitor 116 provided to prevent luminance unevenness due to capacitor deviation of the data lines DL.

In the link region LN in which the multilayered conductive layers are stacked, the step coverage failure may occur due to the first conductive layer M1 having the predetermined thickness t1. A portion of the insulating layer on the first conductive layer M1 may become thinner due to defective step coverage, and a current may be concentrated on the portion, so that the conductive layers to which different signals are applied are short- May occur. For example, when the static electricity is applied, the insulating layer between the first conductive layer M 1 and the second conductive layer M 2 melts to cause dielectric breakdown, and the neighboring first conductive layer M 1 and the second conductive layer M 2 ) May be short-circuited, and a large current may flow into the driver circuit or the like through the neighboring first conductive layer (M1) and the second conductive layer (M2), and the circuit may be damaged. The short circuit problem of the conductive layers due to the step coverage failure is more problematic as the distance G1 between the first conductive layer M1 and the second conductive layer M2 is closer.

Hereinafter, preferred embodiments of the present invention in which the above-described problems are solved will be described with reference to Figs. 13 is a block diagram schematically illustrating a connection relationship between a gate driving circuit and an active region according to a preferred embodiment of the present invention. Figs. 14 to 16 are cross-sectional views schematically showing an inter-layer arrangement structure of a link region to explain a preferred embodiment of the present invention. 17 is a view for explaining effects according to a preferred embodiment of the present invention.

13 and 14, an auxiliary conductive layer M4 is formed on the substrate SUB of the link region LN. A first scan pulse is applied from the gate drive circuit 120 to the auxiliary conductive layer M4. The first scan pulse is transmitted to the scan line GL of the active area AA through the auxiliary conductive layer M4. To this end, one end of the auxiliary conductive layer M4 is electrically connected to the first conductive layer M1 extending from the gate drive circuit 120. [ The first conductive layer M1 and the auxiliary conductive layer M4 are electrically connected to each other and serve as a signal transmission path for supplying the first scan pulse from the gate drive circuit 120 to the scan line GL. The other end of the auxiliary conductive layer M4 is electrically connected to the scan line GL of the active area AA.

In other words, the first conductive layer M1 connected to the gate driving circuit 120 and the scan lines GL of the active area AA are separated from each other on the same layer. The auxiliary conductive layer M4 is disposed under the first conductive layer M1 and the scan line GL. At least one insulating layer is interposed between the auxiliary conductive layer M4 and the first conductive layer M1 and the scan line GL. The auxiliary conductive layer M4 electrically connects the first conductive layer M1 to the scan line GL and transmits the first scan pulse applied through the first conductive layer M1 to the scan line GL .

15, the gate drive circuit 120 and the auxiliary region formed in the first conductive layer M1 and the link region LN extending from the gate drive circuit 120 in the region where the link region LN is adjacent to the gate drive circuit 120, The conductive layer M4 is electrically connected. That is, the first conductive layer M1 and the auxiliary conductive layer M4 may be in contact through the first contact hole CH1 passing through the gate insulating film GI and the buffer layer BUF.

16, the auxiliary conductive layer M4 formed in the link region LN and the scan line GL formed in the active region AA in the region where the link region LN and the active region AA are adjacent to each other, Are electrically connected. That is, the auxiliary conductive layer M4 and the scan line GL can be contacted through the second contact hole CH2 passing through the gate insulating film GI and the buffer layer BUF. Although the signal transmission path to which the first scan pulse is applied has been described above, the present invention is not limited thereto. The preferred embodiment of the present invention can be applied to all the signal paths in which any one signal applied from the gate driving circuit 120 proceeds.

A preferred embodiment of the present invention uses an auxiliary conductive layer M4 instead of the first conductive layer M1 as a signal transmission path through which a scan pulse is transmitted in the link region LN. At this time, the auxiliary conductive layer M4 is formed to have a thickness t2 that is thinner than the first conductive layer M1. Thus, the present invention can prevent a step coverage failure caused by using only the first conductive layer (M1) as a signal transmission path of a scan pulse. A sufficient distance G2 between the auxiliary conductive layer M4 and the second conductive layer M2 is ensured even if a step coverage failure occurs so that the second conductive layer M2 to which different signals are applied and the auxiliary conductive layer M2, It is possible to prevent a problem that short-circuiting occurs between the first and second terminals M4.

In the link region LN, the second conductive layer M2 is formed on the auxiliary conductive layer M4 with the buffer layer BUF, the gate insulating film GI, and the first insulating layer IN1 interposed therebetween. The second conductive layer M2 may be electrically connected to the data line DL of the active area AA. In this case, the second conductive layer M2 and the data line DL are formed in different layers. The data line DL is formed in the same layer as the third conductive layer M3 and is in contact with the second conductive layer M2 through the contact hole passing through the first insulating layer IN1. In the link region LN, the auxiliary conductive layer M4 and the second conductive layer M2 are stacked with the first insulating layer IN1, the gate insulating film GI, and the buffer layer BUF interposed therebetween, Thereby forming the capacitor C1 '. The first capacitor C1 'functions as a compensation capacitor 116 provided to prevent luminance unevenness due to capacitor deviation of the data line DL.

The third conductive layer M3 is formed on the second conductive layer M2 with the second insulating layer IN2 interposed therebetween. The second conductive layer M2 may be a REF routing line to which the reference voltage Vref is applied. The third conductive layer M3 is formed on the same layer as the data line DL of the active area AA. When the second conductive layer M2 is electrically connected to the data line DL, the second conductive layer M2 and the third conductive layer M3 in the link region LN are sandwiched between the second insulating layer IN2 So that the second capacitor C2 is formed. The second capacitor C2 functions as a compensation capacitor 116 provided to prevent luminance unevenness due to capacitor deviation of the data line DL.

Referring to FIG. 17A, when the active area AA is a release type, the lengths of the scan lines GL in the active area AA are different depending on the formation position. That is, the lengths of the scan lines GL_C arranged in the central part of the active area AA and the lengths of the scan lines GL_E arranged in the outer part are different from each other. Accordingly, a load deviation may occur between the scan lines GL_C and GL_E. The preferred embodiment of the present invention facilitates the load deviation compensation of the scan lines GL_C and GL_E by forming the signal transmission path for supplying the scan pulse to the scan line GL via the auxiliary conductive layer M4 can do.

It is necessary to match the time constant (t = R x C) of the scan pulse applied to the scan lines GL having different lengths in order to compensate for the deviation of the scan lines GL. The preferred embodiment of the present invention can reduce the load deviation between the scan lines GL by designing the resistances R_C and R_E of the signal transmission paths through which the scan pulse is transmitted to the scan lines GL_C and GL_E.

For example, as shown in FIG. 17B, the lengths of the signal transmission paths P_C and P_E for transferring the scan pulse from the gate driving circuit 120 to the scan lines GL_C and GL_E may be different from each other have. The length of the signal transmission paths P_C and P_E may be the auxiliary conductive layer M4 of the link region LN. That is, the auxiliary conductive layer M4 (P_C) connected to the scan lines GL_C disposed at the center of the active area AA and the auxiliary conductive layer (M_4) connected to the scan lines GL_E M4, and P_E may be formed to have different lengths so that the resistance values R_C and R_E may be different from each other. The length of at least one of the auxiliary conductive layers M4 connected to the scan lines GL formed in the active area AA may be different from the length of the other. As shown, the planar shape of the auxiliary conductive layer M4 (P_E) connected to the scan lines GL_E disposed in the outer portion of the active area AA may be a stepped pattern. However, the present invention is not limited thereto. The length of each of the auxiliary conductive layers M4 may be selected to have an appropriate resistance value capable of compensating the load deviation according to the length of the corresponding scan line GL.

Since the preferred embodiment of the present invention uses the auxiliary conductive layer M4 having a higher resistance value by having a thickness smaller than that of the first conductive layer M1, the load variation due to the length difference of the scan lines GL It is advantageous to compensation. In the preferred embodiment of the present invention, since the signal transmission path of the scan pulse passes through the auxiliary conductive layer M4 disposed on the other layer without progressing in the same layer, the length of the signal transmission path becomes longer, Respectively. This is advantageous in compensating the load deviation due to the difference in length of the scan lines GL.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: display device 110: display panel
AA: Release active area BZ: Bezel area
111: data routing unit 112: high-potential routing unit
113: Reference voltage routing unit 114: Low potential routing unit
115: AP switch circuit 116: compensation capacitor
117: high potential link line 118: reference voltage link line
120: Gate driving circuit 140: Data driving circuit
160: multiplexer

Claims (8)

A release active area having pixels delimited by scan lines and data lines;
A bezel region located outside the active region;
A gate driving circuit disposed in the bezel region for generating a scan pulse;
A first conductive layer disposed in the bezel region and to which a scan pulse is applied from the gate driving circuit; And
And an auxiliary conductive layer disposed in the bezel region and electrically connecting the first conductive layer to the scan line to transmit a scan pulse from the first conductive layer to the scan line,
The first conductive layer and the scan line are separated from each other on the same layer,
Wherein the auxiliary conductive layer is disposed on a different layer from the first conductive layer and the scan line. The method according to claim 1,
The auxiliary conductive layer, and at least one insulating layer interposed between the first conductive layer and the scan line. The method according to claim 1,
Wherein the auxiliary conductive layer
Wherein the first conductive layer has a thickness smaller than that of the first conductive layer. The method according to claim 1,
Wherein at least one of the auxiliary conductive layers connected to the scan lines has a different resistance value from the other. The method according to claim 1,
Wherein at least one of the auxiliary conductive layers connected to the scan lines is different in length from the other. The method according to claim 1,
A link region defined between the gate driving circuit and the active region, the link region in which the auxiliary conductive layer is disposed;
A second conductive layer disposed on the first conductive layer and the scan line, the second conductive layer being connected to the data line and receiving a data voltage; And
The second conductive layer, and at least one insulating layer interposed between the first conductive layer and the scan line,
Wherein the second conductive layer comprises:
And in the link region, overlaps the auxiliary conductive layer to form a first capacitor. The method according to claim 6,
A third conductive layer disposed over the second conductive layer; And
Further comprising at least one insulating layer interposed between the third conductive layer and the second conductive layer,
Wherein the second conductive layer comprises:
And in the link region, overlaps with the third conductive layer to form a second capacitor. The method according to claim 1,
Wherein one end of the auxiliary conductive layer
A second conductive layer connected to the first conductive layer through a first contact hole passing through the insulating layer,
And the other end of the auxiliary conductive layer,
And connected to the scan line through a second contact hole passing through the insulating layer.

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