KR20150079011A - Display Device And Driving Method Thereof - Google Patents

Abstract

The present invention relates to an image display device preventing a flicker caused by data remaining and a driving method thereof. The image display device according to the present invention comprises a display panel defining pixels by multiple gate lines and multiple data lines; a gate driver selectively operating multiple gate lines by a first voltage, and stopping operation of the multiple gate lines; a data driver supplying a data voltage to the multiple data lines; and a timing controller supplying the first voltage and the second voltage, supplying data for reset to the data driver, when the reset is needed after determining requirement of reset, and supplying the first voltage by replacing the second voltage to select the pixels of entire area of the display panel by the gate driver.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a driving method thereof.

The present invention relates to an image display apparatus and a driving method thereof, and more particularly to an image display apparatus and a driving method thereof for preventing flicker due to residual data.

2. Description of the Related Art Display devices such as a liquid crystal display (LCD) and an organic light emitting diode (OLED) display device are mainly used in recent display devices.

Such image display devices are used as display devices for various devices of various sales because of their excellent image display quality, low power driving capability, and various sizes.

Although these image display devices are excellent in image display quality, there are still problems that deteriorate image display quality. Typical degradation causes are phenomena such as flicker and blur.

The image display apparatus includes a display panel, a driver for selecting pixels to output an image to the display panel, a controller for supplying data, and a controller for controlling the driver. The pixels constituting the display panel are selected by the gate driver, and the data voltage is supplied by the data driver, and the image is displayed by repeating the process of holding the data voltage for several to several tens of ms.

However, if the power of the video display device is suddenly or forcibly turned off without a normal procedure in this process, a flicker occurs due to previously supplied data when the subsequent video is displayed, There is a problem that the perceived quality of the user is deteriorated.

Therefore, an object of the present invention is to provide an image display apparatus and a driving method thereof for preventing flicker due to data residual.

A video display device according to the present invention includes: a display panel in which pixels are defined by a plurality of gate lines and a plurality of data lines; A gate driver for selectively driving the plurality of gate lines by a first voltage and stopping driving of the plurality of gate lines by a second voltage; A data driver for supplying a data voltage to the plurality of data lines; And supplies data for reset to the data driver if it is necessary to perform the reset. The gate driver supplies data for reset to the pixels of the entire region of the display panel by supplying the first voltage and the second voltage, And a timing controller for supplying the first voltage instead of the second voltage to select the first voltage.

The data for the reset is the lowest gradation data.

Wherein the gate driver includes a shift register including a plurality of stages for sequentially outputting a scan pulse for driving the gate line, the gate driver including a first node for driving the gate line of each of the plurality of stages, And an output terminal for outputting another output signal to the gate line according to a voltage state of the first and second nodes.

The timing controller controls the second node to supply the first voltage to the output terminal.

The timing controller causes the second node to supply the second voltage during a period in which the reset is not performed.

Further comprising a plurality of muxes connected to each of a plurality of output channels of the data driver to supply the data voltages from the output panel to the data lines sequentially selected by switching, The first voltage is supplied to the mux to allow the data lines connected to the mux to be selected at the same time.

According to another aspect of the present invention, there is provided a method of driving a video display device, including: determining whether a plurality of gate lines, a plurality of data lines, and a display panel on which pixels are formed are reset; Supplying a first voltage for driving the plurality of gate lines instead of the second voltage to an input terminal to which a second voltage for stopping driving of the plurality of gate lines is input when the reset is necessary; And supplying a data voltage for the reset to the pixels of the entire area selected in accordance with the supply of the first voltage.

The data for the reset is the lowest gradation data.

Wherein the step of supplying the first voltage includes the step of supplying an output signal to the gate line according to a voltage state of a first node for driving the gate line and a second node for stopping driving of the gate line, 1 < / RTI > voltage is supplied to the second node.

And controlling the second node such that the second voltage is output through the second node during a period when the reset is not performed.

Wherein the step of supplying the first voltage comprises supplying the first voltage to the mux that is connected to each of the plurality of output channels of the data driver and selects the data line supplied with the data voltage from the output panel, And selecting all of the data lines.

The video display device and the driving method thereof according to the present invention can prevent the occurrence of flicker due to the remaining data when the data remaining on the display panel is removed before the video display in the video display after the abnormal power- It is possible to prevent deterioration of the bodily sensation quality.

1 is a diagram illustrating a configuration of a display device according to the present invention.
2 is an exemplary diagram for explaining an abnormal termination and a process of resetting it.
3 is a diagram illustrating a configuration of a gate driver according to the present invention in more detail.
4 is a diagram showing a configuration example of the K-th stage.
5 is an exemplary diagram showing the configuration of the output buffer unit in more detail.
6 is an exemplary diagram illustrating a reset scan signal and a scan pulse.
7 is a flowchart illustrating a method of driving an image display apparatus according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. It should be noted that the drawings denoted by the same reference numerals in the drawings denote the same reference numerals whenever possible, in other drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. And certain features shown in the drawings are to be enlarged or reduced or simplified for ease of explanation, and the drawings and their components are not necessarily drawn to scale. However, those skilled in the art will readily understand these details.

1 is a diagram illustrating a configuration of a display device according to the present invention.

Referring to FIG. 1, an image display apparatus according to the present invention includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8.

The display panel 2 includes a plurality of pixels P at intersections of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLn intersecting each other. Each pixel P displays an image by a video signal (data voltage) supplied through a data line DL in response to a scan pulse Vout supplied through a gate line GL. The display panel 2 may be a liquid crystal panel or an organic light emitting diode display (OLED). Each pixel may include a TFT for driving and a storage capacitor Cst, and a data voltage may be stored in the storage capacitor Cst.

The gate driver 4 sequentially supplies the scan pulses Vout to the plurality of gate lines GL by using the gate control signal GCS provided from the timing controller 8. [ The gate driver 4 may be configured in the form of an integrated circuit and may be mounted in a non-display area of the display panel 2 in the form of a GIP (Gate In Panel) ), But the present invention is not limited thereto. In particular, the gate driver 4 of the present invention supplies a scan signal (Vout) for a reset scan line under the control of the timing controller 8. The method of supplying and resetting the reset signal by the gate driver 4 will be described in more detail below.

The data driver 6 outputs the data voltage in response to the data signal DCS provided from the timing controller 8. [ The data driver 4 latches the image data RGB inputted from the system 10 and converts the latched digital video data into an analog gamma voltage to generate a data voltage. Then, the generated data voltage is supplied to the data line DL by one horizontal line. In particular, the data driver 6 outputs a low gray scale voltage for resetting under the control of the timing controller 8 to perform reset of the display panel 2. [ In the present invention, driving and stopping of the gate line GL or the data line DL means whether or not a signal is supplied, respectively. That is, the driving of the gate line means a gate-high (gate line selection) state in which a scan pulse is outputted, and the driving of the data line DL means a state in which a data voltage is outputted. In addition, the driving stop of the gate line means a gate-low (gate line unselected) state. The data driver 6 is connected to the data line DL using a mux and can supply the data voltage to any one of the plurality of data lines DL selected by the mux have. When the data line DL and the data driver 6 are connected using the mux as described above, the first voltage is also supplied to the reset time mux to simultaneously select the data line connected to the mux, The black data or the low gradation voltage supplied from the driver 6 can be supplied.

The timing controller 8 generates the gate control signal GCS and the data control signal DCS using the synchronous signal Sync supplied from the system 10 and supplies the generated gate control signal GCS to the gate driver 4 and supplies the data control signal DCS to the data driver 6. [ The gate control signal GCS may include a plurality of clock pulses having different phase differences and a gate start pulse (GSP) for instructing the gate driver 4 to start driving. The data control signal DCS includes a source output enable (SOE) for controlling the output period of the data driver 6, a source start pulse (SSP) for instructing the start of data sampling, And a source shift clock (SSC) for controlling the sampling timing of the data. When the display panel 2 is a liquid crystal panel, the display panel 2 further includes a polarity control signal POL for controlling the polarity of the data voltage . The timing controller 8 arranges image data RGB input from the outside in accordance with the resolution of the display panel 2 and supplies the image data RGB to the data driver 6.

In particular, when the timing controller 8 detects an abnormal end, the resetting is performed until the power is completely turned off. To this end, the timing controller 8 controls the gate driver 4 to supply a reset scan signal Vreset for resetting so that all the pixels P are controlled by the previous gate line GL of the display panel 2, Is selected. The timing controller 8 supplies the lowest gray level data for resetting, that is, the black data, to the data driver 6 to supply the discharge voltage of the remaining voltage and the lowest gray level data voltage to the data driver 6 .

In particular, in this process, the timing controller 8 controls the supply of power for generation of the reset scan signal Vreset to the output buffer 12 of the gate driver 4 in order to generate and supply the reset scan signal Vreset . Specifically, the timing controller 8 supplies a charge or an on voltage in place of the discharge or off voltage among the voltages supplied to the output buffer units constituting each stage of the gate driver 4 for resetting, And controls power supply to output a signal. Hereinafter, a general scan process and a reset scan process will be described in more detail.

2 is an exemplary diagram for explaining an abnormal termination and a process of resetting it.

Referring to FIG. 2, the timing controller 8 of the present invention performs a reset on the display panel 2 while it can supply a signal when detecting an abnormal termination during driving. That is, the gate line GL is selected in the gate driver 4, and the data voltage is supplied to the selected gate line GL by the data driver 6, And performs a reset. When the display device is re-driven within a predetermined time after the abnormal termination, a voltage higher than the data voltage newly supplied by the previous residual voltage is supplied to the pixel. As a result, a bright gradation over a desired gradation or a very low gradation .

Specifically, as shown in FIG. 2, the gate lines GL1 to GLa may be sequentially selected by the gate driver 4, and the power supply of the display device may be turned off while the data voltage is being supplied. At this time, the data voltages may not be supplied to the unselected gate lines GLa + 1 to GLn.

The influence of the data voltage supplied previously may occur in the pixel P to which the data voltage is supplied. Specifically, in the video display device, each pixel P includes a capacitor or a device serving as a capacitor, and the data voltage can be written to the capacitor and stored. Such a data voltage may be used for driving a pixel together with a data voltage newly supplied when the data voltage is supplied again for a predetermined period of time. For example, when the OLED is composed of pixels, a flicker may occur in which bright gradations of a desired gradation or higher are expressed by a data voltage supplied before an abnormal termination and a newly supplied voltage.

Therefore, as shown in (b) of the present invention, black data, that is, the latest tone data is supplied to the pixels of the entire region of the display panel 2 in advance and reset is performed. At this time, the reset continues until an abnormal termination is detected and the power supply is completely disconnected. More specifically, reset will be described below.

3 is a diagram illustrating a configuration of a gate driver according to the present invention in more detail.

3, the gate driver 4 according to the present invention includes a gate shift register (not shown) for supplying a scan pulse Vout or a reset scan signal Vreset to a plurality of gate lines GL in accordance with a gate control signal GCS, . The gate shift register supplies the gate-on voltage (Vout) during the scan period of each gate line (GL) using the gate start pulse (GSP) through the gate control signal and supplies the gate-off voltage . In describing the present invention, it is assumed that the gate-on voltage is a high level gate-off voltage is a low level. However, the present invention is not limited to this, and the level of the gate-on voltage and the gate-off voltage may be reversed.

The gate control signal GCS includes a clock pulse CLK and a gate start pulse GSP. This gate start pulse GSP has a gate high voltage (VGH) state once at the start of each frame.

The gate shift register includes first through n-th stages ST1 through STn, and sequentially shifts the scan pulse Vout. In addition, the gate shift register outputs a reset scan signal Vreset in the reset period, and a voltage of the same level as the gate-on voltage is output to the reset scan signal supplied at this time.

Each of the stages ST1 to STn receives a clock pulse CLK, a high potential voltage VDD and a low potential voltage VSS. The high-potential voltage VDD is set to jsdkq higher than the low-potential voltage VSS. When the high-potential voltage VDD is used as the gate-on voltage, the low-potential voltage VSS may be the gate- (VDD) may be a gate-off voltage and a low-potential voltage (VSS) may be a gate-on voltage. In the present invention, it is assumed that the high-potential voltage (VDD) is the gate-on voltage and the low-potential voltage (VSS) is the gate-off voltage.

Each of the stages ST1 to STn outputs a scan pulse Vout or a reset scan signal Vreset through an output terminal.

The scan pulse Vout is applied to the gate line GL of the display panel 2 and serves as carry signals Carry1 and Carry2 transferred to the front stage and the rear stage. The front stage based on the K (1 < k < n) stages STk is, for example, a stage in which the first stages ST1 to k -1 stage (STk-1) ". Likewise, the "rear stage" is located at the bottom of the reference stage and indicates either the (k + 1) staging (STk + 1) to the n-th stage STn. In the present invention, the description will be made on the assumption that the front stage and the rear stage refer to a stage immediately before and after the reference stage.

Each stage ST operates in response to the first carry signal Carry1 of the front stage and the second carry signal Carry2 of the rear stage. However, the first stage receives the gate start pulse GSP instead of the first carry signal Carry1. A carry signal from a dummy stage is input to the n-1 and n-th stages STn-1 and STn instead of the second carry signal Carry2.

Thus, each stage outputs a scan pulse of a gate high voltage to each gate line GL in succession to the scan pulse Vout of the previous stage.

On the other hand, when it is recognized by the timing controller 8 that a situation such as an abnormal termination is necessary, resetting the low potential voltage VSS input to each stage ST and turning off the high potential voltage VDD to the low potential voltage VSS) so that the reset scan signal Vreset is supplied instead of the scan pulse Vout. The reset scan signal Vreset is applied to the display panel 2 for a period of time after the power is completely turned off after the abnormal termination is detected so that the pixels in the entire region of the display panel 2 are selected, So that black data can be supplied to the pixel. This will be described in more detail with reference to FIG. 4 and the subsequent figures.

On the other hand, FIG. 4 is a diagram showing the configuration of the K-th stage. 5 is an exemplary diagram showing the configuration of the output buffer unit in more detail.

Referring to FIGS. 4 and 5, the k-th stage STk includes a node control unit 10 and an output buffer unit 12.

The node control unit 10 includes a plurality of TFTs (not shown) for controlling the voltages of the first and second nodes Q and QB in response to the first and second carry signals Carry1 and Carry2 and at least one capacitor (Not shown). The node controller 10 charges the first node Q to the high potential voltage VDD in response to the first carry signal Carry1 and simultaneously turns the voltage of the second node QB to the low potential voltage VSS Discharge. Thereby outputting a gate high voltage through the output terminal. Then, after the gate high voltage output or the output of the reset scan signal, the node control unit 10 charges the voltage of the second node QB to the high potential voltage VDD in response to the second carry signal Carry2 At the same time, the voltage of the first node Q is discharged to the low potential VSS. In the present invention, it is assumed that the turn-on voltage is the high-potential voltage (VDD) turn-off voltage or the discharge voltage (VSS) And may be the above voltage (VDD). However, for convenience of explanation, it is assumed that the present invention is turned on at a high potential (VDD) and turned off or discharged at a low potential (VSS).

The output buffer unit 12 receives the clock pulse CLK from the timing controller 8 and outputs the clock pulse CLK to the output terminal NO when the first node Q is charged to the high potential voltage VDD. To output a gate high voltage. When the voltage of the second node QB is charged to the high potential voltage VDD by the second carry Carry2, the output buffer unit 12 outputs the voltage of the output terminal NO to the low potential voltage VSS or Charge to a high potential voltage (VDD) for reset. In a general scan operation, when the first node Q of the rear stage is charged to the high potential voltage VDD which is the gate high voltage and the high potential voltage VDD is outputted, the high potential voltage VDD is applied to the second carry ) And is input as a voltage for turning on the second node QB of the previous stage. When the second carry (Carry2) is inputted, the second node QB is turned on, and a low potential voltage VSS is supplied to the gate line to output a scan pulse for selecting the gate line GL .

More specifically, when the first node Q is charged, the pull-up transistor TU is turned on to output the clock pulse CLK, and the gate line GL is brought to the gate high state by the output pulse. On the other hand, when the second node QB is charged, the pull-down transistor TD is turned on to output a low potential voltage VSS for turning the gate line GL to the gate low state in a normal state.

On the other hand, for resetting, the timing controller 8 supplies the high potential voltage VDD to the second node QB instead of the low potential voltage VSS when the second node QB is turned ON. That is, the gate line GL is kept in the gate high state, and the pixel is selected by the gate line GL. At this time, by supplying the lowest gradation data voltage for resetting to the selected pixel on the data line DL, .

Particularly, a gate high voltage is supplied to the gate line GL, and the gate high voltage is supplied to the node control unit 12 at the preceding stage as the second carry (Carry2), so that the second node QB is maintained in the ON state . The high-potential data VDD supplied to the pull-down transistor is supplied to the gate line GL by the second node QB that maintains the ON state, so that the entire gate line GL of the display panel 2 becomes the gate high state . Thus, all the pixels of the display panel 2 are selected during the reset period, and the reset voltage supplied through the data line DL, that is, the lowest gradation data voltage is supplied.

To this end, the timing controller stops the supply of the low potential voltage (VSS) among the voltages supplied to the second node (QB) of the output buffer (12) during the reset period and supplies the reset scan signal Vreset) can be supplied to the gate line GL. The timing controller 8 may further include a switching unit for controlling supply of the low potential VSS and the high potential VDD, but the present invention is not limited thereto.

6 is an exemplary diagram illustrating a reset scan signal and a scan pulse.

Referring to FIG. 6, as described above, the present invention performs a reset until a complete termination or power-off occurs when an abnormal termination occurs. In particular, for this purpose, the present invention switches the supply voltage of the output buffer 12 and supplies it, thereby switching the gate line GL in the entire region of the display panel 2 to the driving state, supplying the lowest gradation data voltage, . Thus, the present invention can perform a reset in a complicated circuit for resetting, an easy method without forming a separate reset line.

As shown in FIG. 6, the scan pulses Vout are sequentially supplied to the gate lines GL1 to GLn in the general driving. At this time, when an abnormal end occurs, the driving of the gate line GL and the data line DL is stopped, and the scan pulse Vout is outputted, so that the data voltage remains in the pixels to which the data voltage is supplied.

At this time, if it is determined that an abnormal termination has occurred, the timing control circuit 8 detects this and supplies a reset scan signal through the gate line GL. The reset scan signal Vreset is maintained until the power supply is completely turned off, thereby allowing each pixel of the display panel to be in a state in which the data voltage remains unremoved. Here, the timing controller 8 may further include means for detecting abnormal termination.

The timing controller 8 controls the supply of power to the output buffer 12, which is configured for each stage ST of the gate driver 4, if it is determined that the normal power-off is not performed.

Specifically, the timing controller 8 supplies the turn-on voltage for turning on the transistors constituting each stage and the turn-off voltage for generating the transistor off (off) and gate low voltage as described above. In the present invention, the description has been made on the assumption that the high-potential voltage (VDD) is supplied to the OFF voltage and the low-potential voltage (VSS) is supplied to the ON-voltage.

The timing controller 8 supplies a voltage for driving the gate line GL to the pull-down transistor of the output buffer of the stage instead of a voltage for stopping the driving of the gate line GL. When the gate lines GL are maintained in the driving state, the data voltages for resetting are reset and the pixels selected by the gate line GL are reset.

7 is a flowchart illustrating a method of driving an image display apparatus according to the present invention.

Referring to FIG. 7, a method of driving an image display apparatus according to the present invention includes a reset step S10, a first voltage supply step S20, and a data voltage supply step S30, (S40).

The reset determination step S10 is a step of determining whether there is a situation in which the timing controller 8 needs to reset, such as abnormal termination of the display panel 2 and the video display device, or data remaining. The reset determination step 10 is a step of determining whether a situation such as an abnormal power off or a system error has occurred and determining whether a reset is necessary.

When the first voltage supply step S20 determines that the reset is necessary, the timing controller 8 controls the power supply input of the pull-down transistor controlled in accordance with the voltage state of the second node QB, 1 < / RTI > More specifically, the gate driver 4 applies the scan pulse Vout to each stage ST of the gate driver 4 by using the first voltage, the second voltage and the clock pulse CLK supplied from the timing controller 8, .

In particular, in the first voltage supply step S20, a power source input terminal of the pull-down transistor TD controlled in accordance with the voltage state of the second node QB is provided with a gate- 2 voltage, it is a step of supplying a voltage for the gate high (or driving of the gate line). The first voltage, that is, the high-potential voltage VDD in the above description, is supplied to select all the gate lines GL of the display panel 2 in a gate-high state, that is, a pixel. Here, when the data driver 6 is connected to the data line by the mux, the first voltage is also supplied to the mux so that the data lines connected to the mux are simultaneously selected.

In the data voltage supply step S30, when all pixels of the display panel 2 are selected as the first voltage is supplied, the lowest gradation data voltage for resetting is supplied to all the pixels through the data line DL, The data voltage remaining in the pixel is initialized.

The second voltage supply step S40 is a step in which the second voltage is supplied to the power input terminal of the pull-down transistor while the reset is not performed. Each stage ST includes a node control unit 10 and an output buffer 12. The node control unit controls the voltage state of the first node Q and the second node QB of the output buffer 12 And outputs a scan pulse Vout. At this time, the first voltage VDD is a voltage supplied to the first node Q to control the operation of the pull-up transistor controlling the voltage of the output terminal, and the first node Q is controlled by the first voltage VDD When activated, the clock pulse CLK is output to the gate line GL through the output terminal. When a clock pulse (CLK) is outputted through the rear stage in this manner, the second node (QB) is activated by the node controller 10 with the second carry (Carry2). The pull-down transistor (TD) operates according to the activation of the second node and outputs the second voltage supplied to the input terminal through the output terminal, thereby stopping the driving of the gate.

In the embodiment of the present invention described above, it is assumed that the selection of the gate line is selected by the gate high signal and the selection of the gate line GL is not performed during the gate low. Due to this, the first voltage is supplied with the high potential voltage (VDD), and the second voltage is supplied with the low potential voltage (VSS). However, the present invention is not limited thereto. When the voltage VSS for stopping the driving is supplied to the second voltage and the voltage VDD for driving the gate line is supplied to the first voltage as described in the description, the polarity of the voltage may be inverted .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, . ≪ / RTI > Accordingly, such modifications are deemed to be within the scope of the present invention, and the scope of the present invention should be determined by the following claims.

2: Display panel
4: Gate driver
6: Data driver
8: Timing controller
10:
12: Output buffer

Claims (11)

A display panel in which pixels are defined by a plurality of gate lines and a plurality of data lines;
A gate driver for selectively driving the plurality of gate lines by a first voltage and stopping driving of the plurality of gate lines by a second voltage;
A data driver for supplying a data voltage to the plurality of data lines;
And supplies data for reset to the data driver if it is necessary to perform the reset. The gate driver supplies data for reset to the pixels of the entire region of the display panel by supplying the first voltage and the second voltage, And a timing controller for supplying the first voltage instead of the second voltage so as to select the first voltage. The method according to claim 1,
And the data for resetting is the lowest gradation data. The method according to claim 1,
The gate driver
And a shift register including a plurality of stages for sequentially outputting scan pulses for driving the gate lines,
A first node for driving the gate line of each of the plurality of stages, a second node for stopping driving of the gate line, and another output signal depending on a voltage state of the first and second nodes, And outputting the video signal. The method of claim 3,
Wherein the timing controller controls the second node to supply the first voltage to the output terminal. 5. The method of claim 4,
The timing controller
And the second voltage is supplied by the second node during a period in which the reset is not performed. The method according to claim 1,
Further comprising a plurality of muxes connected to each of a plurality of output channels of the data driver to supply the data voltages from the output panel to the data lines sequentially selected by switching,
Wherein the timing controller supplies the first voltage to the mux for performing the reset so that the data lines connected to the mux are selected at the same time. Determining whether to reset a display panel on which a plurality of gate lines, a plurality of data lines, and pixels are formed;
Supplying a first voltage for driving the plurality of gate lines instead of the second voltage to an input terminal to which a second voltage for stopping driving of the plurality of gate lines is input when the reset is necessary;
And supplying the data voltage for the reset to the pixels of the entire region selected in accordance with the supply of the first voltage. 8. The method of claim 7,
And the data for resetting is the lowest gradation data. 8. The method of claim 7,
The step of supplying the first voltage
Wherein the first voltage is supplied to an output terminal that outputs an output signal to the gate line according to a voltage state of a first node for driving the gate line and a second node for stopping driving of the gate line, And controlling the driving of the liquid crystal display device. 8. The method of claim 7,
And controlling the second node so that the second voltage is output through the second node during a period when the reset is not performed. 8. The method of claim 7,
The step of supplying the first voltage
Selecting all the data lines connected to the mux by supplying the first voltage to the mux connected to each of the plurality of output channels of the data driver and selecting the data line supplied with the data voltage from the output panel; And a driving method of the liquid crystal display device.

Images