KR20150065327A - Method of manufacturuing Electro-Magnetic Shielding Layer for semiconductor package - Google Patents
Method of manufacturuing Electro-Magnetic Shielding Layer for semiconductor package Download PDFInfo
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- KR20150065327A KR20150065327A KR1020130150505A KR20130150505A KR20150065327A KR 20150065327 A KR20150065327 A KR 20150065327A KR 1020130150505 A KR1020130150505 A KR 1020130150505A KR 20130150505 A KR20130150505 A KR 20130150505A KR 20150065327 A KR20150065327 A KR 20150065327A
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- H—ELECTRICITY
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- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electromagnetic wave shielding layer for a semiconductor package, and more particularly, to a method of manufacturing an electromagnetic wave shielding layer for a semiconductor package capable of improving adhesion between an electromagnetic shielding layer and an epoxy molding compound Layer fabrication method.
Typical semiconductor devices include a semiconductor chip manufacturing process for manufacturing a semiconductor chip on a silicon wafer of high purity silicon, a die sorting process for electrically inspecting the semiconductor chip, and a packaging process for packaging a good semiconductor chip Lt; / RTI >
Here, a semiconductor process for packaging a good semiconductor chip generally includes a die attach process for attaching a semiconductor chip to an upper surface of a base substrate through an adhesive, bonding pads arranged on the upper surface of the semiconductor chip, And a molding process for covering the upper surface of the substrate with the molding resin to form a sealing portion for protecting the semiconductor chip from the external environment.
When the completed semiconductor package is operated through the above-described process, electromagnetic waves are inevitably generated in the process of operating the semiconductor package.
When such a semiconductor package is mounted on an electronic device, electromagnetic waves generated in the semiconductor package are emitted to give electromagnetic interference (EMI) to other electronic components mounted on the electronic device. As a result, troubles such as electromagnetic noise or malfunction are caused in the electronic device in which the semiconductor package is mounted, thereby lowering the reliability of the product. In the recently developed semiconductor package, that is, the semiconductor package having a high response speed and a high capacity, the problem of the electromagnetic interference due to the emission of electromagnetic waves becomes more serious.
In recent years, plastics have been widely used in this field due to the weight reduction and miniaturization of various electric and electronic devices. However, since plastic is an insulator that does not allow electricity to flow, that is, a non-conductive material, surface coating, However, the most effective method is the electroless plating method in which the precision, the shielding ability, and the change in the physical properties of the resin are small.
However, such an electroless plating method is widely used as a plating method of a product made of a thermoplastic resin, ABS resin, but cracks are likely to occur in the coating film due to thermal changes, resulting in weak adhesion of the coating film part, have.
In order to solve the above problems, Korean Unexamined Patent Publication No. 10-0839930 (Jun. 20, 2008) discloses a non-metallic material for electro-magnetic shielding and a non-metallic material for electro-magnetic shielding coated thereon. The plating method is advantageous in that the plating is peeled off because the fine grooves are formed on the surface of the non-metallic material by using the electroless plating method to form one or more electromagnetic wave shielding films. However, There is a problem that the adhesion with the shielding film is insufficient.
An object of the present invention is to provide a method for manufacturing an electromagnetic wave shielding layer for a semiconductor package which can improve the adhesion between an epoxy molding compound (EMC) and an electromagnetic wave shielding layer through laser pretreatment.
In order to achieve the above object, the present invention provides the following means.
The present invention is characterized in that the step of pretreating the surface of the EMC sealed upper and side surfaces of the semiconductor chip using a laser (step 1); Attaching a PCB surface on a lower surface of the semiconductor chip to a masking tape (step 2); Chemical pretreatment of the surface of the EMC pretreated with the laser (step 3); Forming an electroless plating layer on the surface of the chemically pretreated EMC (step 4); And forming an electroplating layer on the electroless plating layer (step 5); The present invention also provides a method for manufacturing an electromagnetic wave shielding layer for a semiconductor package.
In the step 1, in the pretreatment using the laser, the surface roughness is processed so that the Ra value is 2 to 10 탆, and the etch thickness is 3 to 50 탆.
In the step 4, the chemically pretreated EMC is immersed in an electroless plating solution at a temperature of 55 to 60 DEG C for 2 to 4 minutes to form an electroless plating layer on the surface of the chemically pretreated EMC with a thickness of 0.125 to 0.5 mu m Plating the copper film (Copper).
In step 5, the electroless plated EMC is immersed in a first electrolytic plating solution and a Cu electrolytic plating having a thickness of 2.0 to 2.3 탆 is applied by applying a current of 0.5 A for 8 to 10 minutes at a temperature of 20 to 30 캜. After that, the substrate is immersed in a second electrolytic plating solution, and a current of 1A is applied for 4 to 6 minutes at a temperature of 50 to 60 DEG C to conduct Ni electroplating with a thickness of 2.0 to 2.5 mu m.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: (1) attaching a PCB surface on a lower surface of a semiconductor chip to a masking tape; Plasma pretreatment of the surface of the EMC sealed upper and side surfaces of the semiconductor chip (step 2); Forming a deposition layer on the surface of the plasma pretreated EMC by sputtering (Step 3); And forming an electroplating layer on the deposition layer (step 4); The present invention also provides a method for manufacturing an electromagnetic wave shielding layer for a semiconductor package.
In the step 2, the Plasma pretreatment is performed for 20 to 60 seconds.
In the step 3, the Ni + Cr deposition layer is formed first by a method of forming a Cu deposition layer by a sputtering method, a method of forming a Ni + Cr deposition layer by a sputtering method, or a sputtering method, And a method of forming a Cu deposition layer on the deposition layer by a sputtering technique.
In the step 3, the thickness of the deposition layer is 500 to 9,000 ANGSTROM.
The method for manufacturing an electromagnetic wave shielding layer for a semiconductor package according to the present invention has an advantage of improving the adhesion between an epoxy molding compound (EMC) and an electromagnetic wave shielding layer through laser pretreatment or plasma pretreatment.
1 is a photograph showing a PCB side.
Fig. 2 is a photograph showing a PCB surface attached to a Cu tape. Fig.
3 is a photograph showing an electromagnetic wave shielding layer for a semiconductor package.
FIG. 4 is a photograph of a surface treated with plasma for 10 seconds.
FIG. 5 is a photograph of a surface treated with plasma for 40 seconds.
FIG. 6 is a photograph of a surface treated with plasma for 100 seconds. FIG.
Hereinafter, the present invention will be described in detail.
EMC (Epoxy Molding Compound) is most widely used as a material for sealing semiconductor devices such as silicon chips, gold wires and lead frames to protect them from heat, moisture, impact and the like. EMC is used as an encapsulant for transistors, diodes, microprocessors, and semiconductor memories.
A feature of the present invention is to provide a method for improving the adhesion between EMC and an electromagnetic shielding layer plated on the EMC in a semiconductor package.
First, a method of manufacturing an electromagnetic wave shielding layer for a semiconductor package according to an embodiment of the present invention will be described.
In the method for manufacturing an electromagnetic wave shielding layer for a semiconductor package of the present invention,
(Step 1) of pretreating the surface of the EMC sealed upper and side surfaces of the semiconductor chip using a laser;
Attaching a PCB surface on a lower surface of the semiconductor chip to a masking tape (step 2);
Chemical pretreatment of the surface of the EMC pretreated with the laser (step 3);
Forming an electroless plating layer on the surface of the chemically pretreated EMC (step 4); And
Forming an electroplating layer on the electroless plating layer (step 5);
.
In the step 1, when the surface of the EMC (Epoxy Molding Compound) sealing the upper and the side surfaces of the semiconductor chip is cut off using a laser, the surface roughness is improved and the bonding strength with the electromagnetic wave shielding layer is increased . The present invention is characterized in that the surface roughness is improved as compared with the case of pretreatment by the dry sanding method due to pretreatment using a laser.
When the surface of the EMC (Epoxy Molding Compound) is pretreated with a laser, the surface roughness is preferably adjusted to have a Ra value of 2 to 10 탆. When the Ra value is less than 2 탆, Blister And when the Ra value is 10 μm or more, it becomes very rough, resulting in a discolor failure in which the surface color is uneven after plating. The laser etch thickness is preferably 3 to 50 탆, and when the etch depth is less than 3 탆, the surface is not sufficiently treated to cause blister failure. When the etch depth is more than 50 탆, the surface roughness is excessively coarse A discolor defect occurs in which the plating color is uneven.
In the step 2, the top and four side surfaces of the semiconductor chip are sealed with EMC (Epoxy Molding Compound), and the lower surface located on the opposite side of the upper surface is a PCB (Printed Circuit Board) surface. Masking is necessary because the PCB (Printed Circuit Board) surface can not be plated. In the present invention, a masking tape is attached to protect the PCB (Printed Circuit Board) surface, and it can simultaneously perform masking of the PCB surface and ground necessary for electrolytic plating.
In the step 3, the chemical pretreatment step is a conditioner treatment step, a soft etch treatment step, an activator treatment step and a reducer treatment step. The Conditioner treatment process is immersed in a first solution at 40 DEG C for 5 minutes and the Soft Etch treatment process is immersed in a second solution at 40 DEG C for 2 minutes, Minute, and the Reducer treatment process is preferably immersed in the fourth solution at 25 DEG C for 1 minute. The first solution to the fourth solution may be a solution that is conventionally used for chemical pretreatment, so that a detailed description thereof will be omitted. The conditioner treatment process is a typical pretreatment process of electroless plating method of plating metal on the surface of nonconductive material. It removes light organic contaminants on the surface, conditioning the nonconductive material before activator and electroless plating, chemically forming roughness . The soft etch process is a process for removing the oxidizing contaminants or the like that may remain on the surface and activating the surface so that the catalyst can be adsorbed smoothly on the surface in the activator process. The Activator treatment process is an essential step of electroless plating and is a catalyst adsorption process for copper and nickel plating on the nonconductor. The Reducer treatment process is a process of activating a catalyst adsorbed on the nonconductor surface.
In the step 4, the chemically pretreated EMC is immersed in an electroless plating solution at a temperature of 55 to 60 DEG C for 2 to 4 minutes to form a copper film having a thickness of 0.125 to 0.5 mu m on the surface of the chemically pretreated EMC by electroless plating (Copper) plating step. The electroless plating refers to plating a desired metal onto a substrate without applying a current. Since the electroless plating solution used can be a conventional electroless plating solution, a detailed description thereof will be omitted.
Step 5 is a step of forming an electroplating layer on the electroless plating layer. The electroless plated EMC is immersed in a plating solution, and a plating process is performed by applying an electric current. The electroless plated EMC was immersed in a first electrolytic plating solution and Cu electrolytic plating having a thickness of 2.0 to 2.3 탆 was performed at a temperature of 20 to 30 캜 for 8 to 10 minutes under a current of 0.5 A, 2 electrolytic plating solution, and a current of 1A is applied for 4 to 6 minutes at a temperature of 50 to 60 DEG C to conduct Ni electroplating with a thickness of 2.0 to 2.5 mu m. Since the electrolytic plating solution used conventionally can be used as the electrolytic plating solution, a detailed description will be omitted.
After the step 5, a step of performing nickel oxidation-preventing treatment on the electroplating layer may be added. The electrolytic plating layer is preferably immersed in an organic solution at 40 DEG C for 3 minutes. Nickel is less oxidized in air than copper, but oxidized and discolored over time. It is carried out for the purpose of maintaining a unique nickel color by carrying out oxidation prevention treatment using an organic solution after nickel plating.
Next, a method for manufacturing an electromagnetic wave shielding layer for a semiconductor package according to another embodiment of the present invention will be described.
In the method for manufacturing an electromagnetic wave shielding layer for a semiconductor package of the present invention,
Attaching a PCB surface on a lower surface of the semiconductor chip to a masking tape (step 1);
Plasma pretreatment of the surface of the EMC sealed upper and side surfaces of the semiconductor chip (step 2);
Forming a deposition layer on the surface of the plasma pretreated EMC by sputtering (Step 3); And
Forming an electroplating layer on the deposition layer (step 4);
.
In the step 1, the upper surface and the four side surfaces of the semiconductor chip are sealed with EMC (Epoxy Molding Compound), and the lower surface located on the opposite side of the upper surface is a PCB (Printed Circuit Board) surface. Masking is necessary because the PCB (Printed Circuit Board) surface can not be plated. In the present invention, a masking tape is attached to protect the PCB (Printed Circuit Board) surface, and it can simultaneously perform masking of the PCB surface and ground necessary for electrolytic plating.
Step 2 is a step of pretreating the surface of the EMC sealed on the top and four sides of the semiconductor chip using an ion gun, and is performed to improve adhesion by removing impurities and surface modification of the EMC surface. The plasma treatment is preferably performed for 20 to 60 seconds, and the surface modification is not sufficient in the treatment for less than 20 seconds, so that the roughness is not formed, and the roughness formed after the treatment for over 60 seconds is flattened again .
FIG. 4 is a photograph of the surface when the treatment is performed for 10 seconds in the plasma treatment. FIG. 5 is a photograph of the surface when the treatment is performed for 40 seconds. FIG. 6 is a photograph of the surface when treated for 100 seconds.
Referring to FIG. 4, when plasma treatment is performed for 10 seconds, the surface modification is not sufficient and the surface smoothness is maintained, so that the roughness is not formed.
Referring to FIG. 5, when the plasma treatment is performed for 40 seconds, the roughness is uniformly formed and the surface of the metal layer is easily formed.
Referring to FIG. 6, when plasma is treated for 100 seconds, it can be seen that the roughness that has been formed by over-processing is flattened again.
Step 3 is a step of forming a deposition layer by sputtering on the surface of the plasma pretreated EMC to form a seed layer for electroplating in the next step. The deposition layer may be formed by forming a Cu deposition layer by a sputtering method, forming a Ni + Cr deposition layer by a sputtering method, or forming a Ni + Cr deposition layer by a sputtering technique, Or a method of forming a Cu vapor deposition layer by a CVD method. The Ni + Cr is preferably mixed with 90 to 95% by weight of Ni (nickel) and 5 to 10% by weight of Cr (chromium). Thickness of the deposition layer is preferably 500 to 9000 Å. When the thickness of the deposition layer is less than 500 Å, the thickness of the seed layer becomes too thin to increase the electrical resistance value during the electrolytic plating, Å, the thickness of the seed layer becomes too thick, which may deteriorate the adhesion after electroplating.
Step 4 is a step of forming an electroplating layer on the deposition layer, and it is preferable to perform Ni electroplating after Cu electroplating.
After the step 4, a step of performing nickel oxidation-preventing treatment on the electroplating layer may be added. The electrolytic plating layer is preferably immersed in an organic solution at 40 DEG C for 3 minutes. Nickel is less oxidized in air than copper, but oxidized and discolored over time. It is carried out for the purpose of maintaining a unique nickel color by carrying out oxidation prevention treatment using an organic solution after nickel plating.
Hereinafter, the constitution and effects of the present invention will be described in more detail through examples. These embodiments are only for illustrating the present invention, and the scope of the present invention is not limited by these embodiments.
The surface of the EMC sealed top and four sides of the semiconductor chip was pretreated with SPI-G4-20W Laser from SPI. A PCB surface on the lower surface of the semiconductor chip was attached to the Cu tape. A photograph showing the PCB side is shown in Fig. 1, and a photograph of the PCB side attached to the Cu tape is shown in Fig. The surface of the EMC pretreated with the laser was chemically pretreated. The chemical pretreatment was carried out as follows. The conditioner treatment process was immersed in the HA Conditioner solution at 40 DEG C for 5 minutes and the Soft Etch treatment process was immersed in the Etchant B4 solution at 40 DEG C for 2 minutes and the Activator treatment process was performed in the D34C solution at 40 DEG C for 3 minutes And the Reducer treatment process was immersed in the Pre-Dip A solution at 25 占 폚 for 1 minute. The chemically pretreated EMC was immersed in a MID copper solution at a temperature of 58 캜 for 2 minutes, and a copper film having a thickness of 0.125 탆 was plated on the surface of the chemically pretreated EMC by an electroless plating method to form an electroless plating layer Respectively. The electroless plated EMC was immersed in EX5000 solution and subjected to Cu electroplating with a thickness of 2.0 탆 by applying a current of 0.5 A for 8 minutes at a temperature of 25 캜 and immersed in a solution of MID NI and heated at a temperature of 55 캜 A current of 1A was applied for 4 minutes to conduct Ni electroplating with a thickness of 2.25 mu m to form an electroplating layer. The electrolytic plating layer was immersed in an organic solution at 40 DEG C for 3 minutes to prevent oxidation of nickel to form an electromagnetic wave shielding layer. FIG. 3 shows a photograph of the electromagnetic wave shielding layer for a semiconductor package.
[Experimental Example 1]
In the laser pretreatment in Example 1, the surface roughness was fixed to 1 탆 after the Ra value was fixed, and the blister occurrence, the tape peel-off test and the Discolor test were performed while adjusting the etching depth. Respectively. The blister means that the metal ion can not normally rise on the surface of the material to be plated, resulting in swelling when the material is subjected to a drying process after plating. The Tape peel-off test is a method of grinding the plating surface to be tested in a lattice shape using a blade and then using a 3M tape to peel off the tape to confirm whether the plating layer has fallen off the plated body. The Discolor means that the silica fillers embedded in the compound are non-uniformly processed during roughness formation or laser etching, and the plating color is uniform and non-uniform after plating, and the plating color is uneven due to the step difference.
Ra = 1 탆
As shown in Table 1, when the surface roughness was not sufficiently formed by processing Ra = 1 탆, a blister was generated even when the etching depth was increased, and the tape peel test failed under all conditions.
[Experimental Example 2]
In the laser pretreatment in Example 1, the surface roughness was fixed to 2 탆 after the Ra value was fixed, and the blister occurrence, the tape peel-off test and the discolor test were performed while adjusting the etch depth. Respectively.
Ra = 2 탆
As shown in Table 2, when the surface roughness was Ra = 2 탆, defects did not occur within the range of the etching thickness of 3 to 50 탆.
[Experimental Example 3]
In the laser pretreatment in Example 1, the surface roughness was fixed to 4 탆 after the Ra value was fixed, and the blister occurrence, the tape peel-off test and the Discolor test were performed while adjusting the etch depth. Respectively.
Ra = 4 탆
As shown in Table 3, when the surface roughness was Ra = 4 탆, defects did not occur within the range of the etched thickness of 3 to 50 탆.
[Experimental Example 4]
In the laser pretreatment in Example 1, the surface roughness was fixed by setting the Ra value to 6 μm, and then the blister generation, the tape peel-off test and the discolor test were performed while adjusting the etch depth. The results are shown in Table 4 Respectively.
Ra = 6 탆
As shown in Table 4, when the surface roughness was Ra = 6 탆, defects did not occur within the range of the etching thickness of 3 to 50 탆.
[Experimental Example 5]
In the laser pretreatment in Example 1, the surface roughness was fixed to 8 탆 after the Ra value was fixed, and the blister occurrence, the tape peel-off test and the Discolor test were performed while adjusting the etching depth. Respectively.
Ra = 8 탆
As shown in Table 5, when the surface roughness was Ra = 8 占 퐉, no defect occurred within the range of the etched thickness of 3 to 50 占 퐉.
[Experimental Example 6]
In the laser pretreatment in Example 1, the surface roughness was fixed by raising the Ra value to 10 μm, and the blister generation, adhesion peel-off test and Discolor test were performed while adjusting the etch depth. The results are shown in Table 6 Respectively.
Ra = 10 탆
As shown in Table 6, when the surface roughness was Ra = 10 탆, defects did not occur within the range of the etching thickness of 3 to 50 탆.
[Experimental Example 7]
In the laser pretreatment in Example 1, the surface roughness was fixed to 11 탆 after the Ra value was fixed, and the blister occurrence, the tape peel-off test and the discolor test were performed while adjusting the etch depth. Respectively.
Ra = 11 탆
In Table 11, Discolor failure occurred regardless of the etching thickness when the surface roughness was Ra = 11 μm.
Considering the above experiment as a whole, the surface roughness showed the best result in the range of 2 to 10 μm, and when the Ra value was less than 2 μm, The value exceeded 10 탆 and became very rough when processed, resulting in discolor failure where the surface color was uneven after plating.
In the case of laser etching thickness, the surface is not sufficiently treated during etching, resulting in blister failure. If the etching is performed by more than 50 탆, discolor failure such as uneven coating color occurs as in the case where the surface roughness is excessively rough .
The PCB side of the semiconductor chip was attached to the Cu tape. The surface of the EMC sealed with the top and four sides of the semiconductor chip was subjected to plasma pretreatment using an ion gun. The Ni + Cr deposition layer was formed by Ni + Cr sputtering on the surface of the EMC pretreated with the plasma, and a Cu deposition layer was formed by Cu sputtering on the Ni + Cr deposition layer. The Ni + Cr was mixed with 95% by weight of Ni (nickel) and 5% by weight of Cr (chromium). Cu electroplating was performed on the Cu deposition layer, and then Ni electroplating was performed to form an electroplating layer.
[Experimental Example 8]
After the plasma treatment time was fixed to 10 seconds in Example 2, blister formation, tape peel-off test and discolor test were performed while controlling the thickness of the deposition layer. 8.
Processing time
Thickness (a)
Thickness (b)
(a + b)
10 seconds
As shown in Table 8, when the plasma treatment time was changed to 10 seconds, the surface modification was not sufficient and the roughness was very smooth.
[Experimental Example 9]
Table 2 shows the results of the Tape peel-off test and the blister occurrence test while controlling the thickness of the deposition layer after fixing the plasma treatment time to 20 seconds in Example 2. The results are shown in Table 9 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
20 seconds
As shown in Table 9, when the plasma treatment time was 20 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 10]
In the second embodiment, a plasma peeling test and a blister generation test were performed while controlling the thickness of the deposition layer after fixing the plasma treatment time to 30 seconds. The results are shown in Table 10 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
30 seconds
As shown in Table 10, when the plasma treatment time was changed to 30 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 11]
In the second embodiment, the plasma treatment time was fixed to 40 seconds, and then the thickness of the deposition layer was controlled while the blister generation and the tape peel-off test were performed. The results are shown in Table 11 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
40 seconds
As shown in Table 11, when the plasma treatment time was set to 40 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 12]
In the second embodiment, the plasma treatment time was fixed to 50 seconds, and then the thickness of the deposition layer was adjusted while the blister generation and the tape peel-off test were performed. The results are shown in Table 12 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
50 seconds
Table 12 shows that when the plasma treatment time was set to 50 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 13]
In the second embodiment, the plasma treatment time was fixed to 60 seconds, and then the thickness of the deposited layer was adjusted, and blister formation and tape peel-off test were performed. The results are shown in Table 13 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
60 seconds
As shown in Table 13, when the plasma treatment time was set to 60 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 14]
In the second embodiment, the plasma treatment time was fixed to 70 seconds, and then the thickness of the deposition layer was controlled while the blister generation and the tape peel-off test were performed. The results are shown in Table 14 .
Processing time
Thickness (a)
Thickness (b)
(a + b)
70 seconds
As shown in Table 14, when the plasma treatment time was changed to 70 seconds, the surface modification was over-treated and the roughness was flattened again, resulting in failure regardless of the deposition layer thickness.
[Experimental Example 15]
Table 10 shows the results of the Tape peel-off test and the blister occurrence test while controlling the thickness of the deposition layer after fixing the plasma treatment time to 100 seconds in the example 2, .
Processing time
Thickness (a)
Thickness (b)
(a + b)
100 seconds
As shown in Table 15, when the plasma treatment time is set to 100 seconds, the surface modification is over-treated and the roughness is flattened again, resulting in failure regardless of the deposition layer thickness.
The PCB side of the semiconductor chip was attached to the Cu tape. The surface of the EMC sealed with the top and four sides of the semiconductor chip was subjected to plasma pretreatment using an ion gun. A Cu deposition layer was formed by Cu sputtering on the surface of the EMC pretreated with the plasma. Cu electroplating was performed on the Cu deposition layer, and then Ni electroplating was performed to form an electroplating layer.
[Experimental Example 16]
In the third embodiment, the plasma treatment time was fixed to 10 seconds, and the thickness of the deposited layer was adjusted. Blister formation, Tape peel-off test and Discolor test were performed. Respectively.
Processing time
10 seconds
As shown in Table 16, when the plasma treatment time was changed to 10 seconds, the surface was not sufficiently reformed and the roughness was very smooth.
[Experimental Example 17]
In Example 3, the plasma treatment time was fixed to 20 seconds, and then the thickness of the deposited layer was adjusted. Blister occurrence, Tape peel-off test and Discolor test were performed. Respectively.
Processing time
20 seconds
Table 17 shows that when the plasma treatment time was changed to 20 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 18]
After the plasma treatment time was set to 30 seconds in Example 3, blister formation, tape peel-off test and discolor test were performed while controlling the thickness of the deposited layer. Respectively.
Processing time
30 seconds
As shown in Table 18, when the plasma treatment time was set to 30 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 19]
In the third embodiment, the plasma treatment time was fixed to 40 seconds, and the thickness of the deposited layer was controlled while the blister generation, the tape peel-off test and the discolor test were performed. Respectively.
Processing time
40 seconds
Table 19 shows that when the plasma treatment time was set to 40 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 20]
After the plasma treatment time was set to 50 seconds in Example 3, blister formation, tape peel-off test, and Discolor test were performed while adjusting the thickness of the deposited layer. Respectively.
Processing time
50 seconds
As shown in Table 20, when the plasma treatment time was set to 50 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 angstroms.
[Experimental Example 21]
In Example 3, the plasma treatment time was fixed to 60 seconds, and then the thickness of the deposited layer was controlled while the blister generation, the tape peel-off test and the discolor test were performed. Respectively.
Processing time
60 seconds
As shown in Table 21, when the plasma treatment time was set to 60 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 angstroms.
[Experimental Example 22]
In the third embodiment, the plasma treatment time was fixed to 70 seconds, and then the thickness of the deposited layer was adjusted. Blister occurrence, Tape peel-off test and Discolor test were performed. Respectively.
Processing time
70 seconds
As shown in Table 22, when the plasma treatment time was set to 70 seconds, the surface modification was over-treated and the roughness was flattened again, resulting in failure regardless of the deposition layer thickness.
[Experimental Example 23]
In Example 3, the plasma treatment time was fixed to 100 seconds, and then the thickness of the deposited layer was adjusted. Blister formation, Tape peel-off test and Discolor test were performed. Respectively.
Processing time
100 seconds
Table 23 shows that when the plasma treatment time is set to 100 seconds, the surface modification is over-treated and the roughness is flattened again, resulting in failure regardless of the deposition layer thickness.
The PCB side of the semiconductor chip was attached to the Cu tape. The surface of the EMC sealed with the top and four sides of the semiconductor chip was subjected to plasma pretreatment using an ion gun. The Ni + Cr deposited layer was formed by Ni + Cr sputtering on the surface of the EMC pretreated with the plasma. The Ni + Cr was mixed with 95% by weight of Ni (nickel) and 5% by weight of Cr (chromium). The Ni + Cr deposition layer was subjected to Cu electroplating and Ni electroplating to form an electrolytic plating layer.
[Experimental Example 24]
In Example 4, the plasma treatment time was fixed to 10 seconds, and then the thickness of the deposited layer was adjusted. Blister formation, Tape peel-off test and Discolor test were performed. 24.
Processing time
10 seconds
As shown in Table 24, when the plasma treatment time was set to 10 seconds, the surface modification was not sufficient and the roughness was very smooth.
[Experimental Example 25]
After the plasma treatment time was fixed to 20 seconds in Example 4, blister formation, tape peel-off test and discolor test were performed while controlling the thickness of the deposition layer. 25.
Processing time
20 seconds
As shown in Table 25, when the plasma treatment time was 20 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 26]
In Example 4, the plasma treatment time was fixed to 30 seconds, and then the thickness of the deposited layer was adjusted, and blister formation, tape peel-off test and discolor test were performed. Respectively.
Processing time
30 seconds
Table 26 shows that when the plasma treatment time was set to 30 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 angstroms.
[Experimental Example 27]
After the plasma treatment time was set to 40 seconds in Example 4, blister formation, tape peel-off test and discolor test were performed while controlling the thickness of the deposition layer. Respectively.
Processing time
40 seconds
As shown in Table 27, when the plasma treatment time was set to 40 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 28]
After the plasma treatment time was set to 50 seconds in Example 4, blister formation, tape peel-off test and discolor test were performed while adjusting the thickness of the deposited layer. Respectively.
Processing time
50 seconds
Table 28 shows that when the plasma treatment time was set to 50 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 29]
In the fourth embodiment, the plasma treatment time was fixed to 60 seconds, and then the thickness of the deposited layer was adjusted, and blister occurrence, tape peel-off test and discolor test were performed. 29.
Processing time
60 seconds
Table 29 shows that when the plasma treatment time was set to 60 seconds, no defect occurred within the range of the deposition layer thickness of 500 to 9,000 Å.
[Experimental Example 30]
After the plasma treatment time was fixed to 70 seconds in Example 4, blister formation, tape peel-off test and Discolor test were performed while controlling the thickness of the deposited layer. Respectively.
Processing time
70 seconds
As shown in Table 30, when the plasma treatment time was set to 70 seconds, the surface modification was over-treated and the roughness was flattened again, resulting in failure regardless of the deposition layer thickness.
[Experimental Example 31]
After the plasma treatment time was set to 100 seconds in Example 4, blister formation, tape peel-off test and discolor test were performed while controlling the thickness of the deposition layer. Respectively.
Processing time
100 seconds
As shown in Table 31, when the plasma treatment time is set to 100 seconds, the surface modification is over-treated and the roughness is flattened again, resulting in failure regardless of the thickness of the deposited layer.
Considering the above experiment as a whole, when the plasma is treated for less than 20 seconds, the surface modification is not sufficient and the roughness is not formed, and the roughness that was formed during the treatment for over 60 seconds is flattened again.
When the thickness of the deposition layer is less than 500 angstroms, the thickness of the seed layer becomes too thin to increase the electrical resistance value during the electroplating process, thereby deteriorating the plating quality. When the thickness of the deposition layer is more than 9,000 angstroms, layer was too thick to reduce the adhesion after electroplating.
Claims (8)
Attaching a PCB surface on a lower surface of the semiconductor chip to a masking tape (step 2);
Chemical pretreatment of the surface of the EMC pretreated with the laser (step 3);
Forming an electroless plating layer on the surface of the chemically pretreated EMC (step 4); And
Forming an electroplating layer on the electroless plating layer (step 5);
Wherein the electromagnetic wave shielding layer is made of a metal.
Wherein the surface roughness is etched so as to have a Ra value of 2 to 10 占 퐉 and the etch thickness to be 3 to 50 占 퐉 in the pretreatment using a laser.
The chemically pretreated EMC was immersed in an electroless plating solution at a temperature of 55 to 60 ° C for 2 to 4 minutes to form a copper film having a thickness of 0.125 to 0.5 탆 on the surface of the chemically pretreated EMC by electroless plating Wherein the electromagnetic wave shielding layer is plated.
The electroless plated EMC was immersed in a first electrolytic plating solution and Cu electrolytic plating having a thickness of 2.0 to 2.3 탆 was performed at a temperature of 20 to 30 캜 for 8 to 10 minutes under a current of 0.5 A, 2 electrolytic plating solution, and performing a Ni electroplating with a thickness of 2.0 to 2.5 占 퐉 by applying a current of 1A for 4 to 6 minutes at a temperature of 50 to 60 占 폚.
Plasma pretreatment of the surface of the EMC sealed upper and side surfaces of the semiconductor chip (step 2);
Forming a deposition layer on the surface of the plasma pretreated EMC by sputtering (Step 3); And
Forming an electroplating layer on the deposition layer (step 4);
Wherein the electromagnetic wave shielding layer is made of a metal.
Wherein the plasma pretreatment is performed for 20 to 60 seconds.
The deposition layer may be formed by forming a Cu deposition layer by a sputtering method, forming a Ni + Cr deposition layer by a sputtering method, or forming a Ni + Cr deposition layer by a sputtering technique, And forming a Cu vapor-deposited layer on the copper foil.
Wherein the thickness of the deposition layer is 500 to 9,000 ANGSTROM.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018143718A1 (en) * | 2017-02-03 | 2018-08-09 | (주)잉크테크 | Method for forming coating that blocks electromagnetic waves |
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| KR102026705B1 (en) | 2018-03-23 | 2019-09-30 | 서울과학기술대학교 산학협력단 | Fan-out package with reducing warpage and shielding emi |
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| KR20020071437A (en) * | 2001-03-06 | 2002-09-12 | 유승균 | Plating method of metal film on the surface of polymer |
| KR100464799B1 (en) * | 2003-11-19 | 2005-01-14 | 허삼만 | Processing and product for manufacturing multi-layer flexible printed circuit board |
| KR100629861B1 (en) * | 2005-08-31 | 2006-10-02 | 서피스텍 주식회사 | A method for manufacturing base film unit for electromagnetic wave shield filter and a base film unit for electromagnetic wave shield filter according to the method |
| KR101332332B1 (en) * | 2011-12-27 | 2013-11-22 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package having electromagnetic waves shielding means, and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2018143718A1 (en) * | 2017-02-03 | 2018-08-09 | (주)잉크테크 | Method for forming coating that blocks electromagnetic waves |
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