KR102026705B1 - Fan-out package with reducing warpage and shielding emi - Google Patents

Abstract

The present invention relates to a fan-out package process among semiconductor package processes and, more specifically, to a fan-out wafer level package (FOWLP) or fanout-panel wafer level package (FO-PLP) capable of simultaneously alleviating an electro magnetic interference (EMI) shielding effect between chips shielding electromagnetic waves occurred in chips and warpage occurred in a process by performing an EMC molding process on a metal thin film made of Cu, Ni, etc. and then depositing a metal thin film.

Description

FAN-OUT PACKAGE WITH REDUCING WARPAGE AND SHIELDING EMI}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fan-out package process in a semiconductor package process, and more particularly, to deposit a metal thin film such as Cu or Ni after an EMC molding process, to block electromagnetic waves generated from a chip. Fan-out wafer level package (FOWLP) or fanout-panel level package to simultaneously mitigate electro magnetic interference (EMI) shielding effects and process warpage wafer level package (FO-PLP).

Recently, many researches on packaging technology have been conducted. In particular, FOWLP (Fanout Wafer Level Package) is a technology that can be mounted using standard solder and bumps by constructing input / output terminal wiring using RDL (Redistribution Layer). It is a technology that has many advantages of being thinner and reducing power consumption.

In the FOWLP or FO-PLP process, an adhesive is applied on a carrier, an silicon chip is disposed, an epoxy mold compound is molded, and an adhesive layer is removed using a heat source or a chemical solution. Remove the carrier.

However, during high temperature EMC molding, warpage occurs due to the difference in coefficient of thermal expansion between EMC, carrier, and silicon chip, which warp the wafer and make subsequent semiconductor process impossible, and it is a problem for future chip reliability. Causes

In connection with the present invention, US Pat. No. 9,349,613 dated 24 May 2016 'Electronic package with embedded materials in a molded structure to control warpage and stress'; US Patent No. 9,006,030, filed April 14, 2016 'Warpage management for fan-out mold packaged integrated circuit'; Republic of Korea Patent Registration 10-1504272 (Registration Date 2015.03.13) 'Compound semiconductor and its manufacturing method'; Republic of Korea Patent Registration 10-1540583 (Registration date 2015.07.24) 'Method for manufacturing electromagnetic shielding layer for semiconductor package'; Republic of Korea Patent Application Publication No. 10-2002-0063466 (published: 2002.08.03) 'electromagnetic wave absorption blocking composition for interior and exterior materials for automobiles or semiconductor packages'; US published patent US 2010/0109131 published on May 6, 2010 'Reduced wafer warpage in semiconductors by stress engineering in the metallization system'; Republic of Korea Patent Registration 10-1393700 (Registration Date 2014.05.02) 'Fan out wafer level packaging process to strengthen the warp prevention function of the wafer'; Korean Patent Registration No. 10-1743460 (Date 2017.05.30) discloses a 'fan-out wafer level package process for 3D stacking to minimize warpage of wafers'.

United States Patent US 9,349,613 (Registration date 2016.05.24) United States Patent US 9,006,030 (Registration date 2016.04.14) Republic of Korea Patent Registration 10-1504272 (Registration Date 2015.03.13) Republic of Korea Patent Registration 10-1540583 (Registration date 2015.07.24) Republic of Korea Patent Publication No. 10-2002-0063466 (published date 2002.08.03) United States Patent Application Publication No. 2010/0109131 (published 2010.05.06) Republic of Korea Patent Registration 10-1393700 (Registration Date 2014.05.02) Republic of Korea Patent Registration 10-1743460 (Registration Date 2017.05.30)

The present invention can prevent the warpage of the wafer by artificially generating the residual stress of the metal by depositing and annealing a metal thin film such as Ni and Cu after the EMC molding process, and at the same time to have a EMI (Electro Magnetic Interference) shield function on the silicon chip To provide a fan-out package process consisting of a fan-out wafer-level package process or a fan-out-panel-level package process with both warpage reduction and EMI shielding, which produces an effect of shielding electromagnetic waves generated from a chip. It is an object of the invention.

In order to achieve the above object,

According to the present invention, after forming an adhesive layer by applying an adhesive on a surface of a carrier, a first step (S10) of disposing a silicon chip on the adhesive layer,

A second step (S20) of molding the carrier and the silicon chip with an epoxy mold compound (EMC);

By depositing and annealing a metal thin film on top of the epoxy mold compound (EMC), the residual stress of the metal is artificially generated to prevent warpage of the wafer, and at the same time, electromagnetic wave (EMI) generated from the silicon chip is prevented. Third process (S30) to allow the shield,

A fourth step (S40) of removing the carrier by removing the adhesive layer with a heat source or a chemical solution,

A fifth step (S50) of attaching a redistribution layer (RDL) to a surface on which the silicon chip is formed;

It provides a fan-out package process having a bending reduction and EMI shielding at the same time comprising a sixth step (S60) for attaching the solder ball to the surface to which the redistribution layer (RDL) is attached.

The fan-out level package process having both warpage reduction and EMI shielding function according to the present invention has the following effects.

first. After the EMC molding process, the metal thin film is deposited and annealed to artificially generate residual stress of the metal to prevent warpage of the wafer, and at the same time, the silicon chip has an EMI (Electro Magnetic Interference) shield function to shield electromagnetic waves generated from the chip. It has an effect that can be done.

second. Stresses generated by warpage during the process, the biggest problem with fan-out wafer level package (FOWLP) or fanout-panel wafer level package (FO-PLP) technology This allows for subsequent processing and improves package yield, yield and reliability.

third. EMI shielding effect between chips prevents chip errors due to EMI, and more semiconductor chips can be packaged in a limited space.

fourth. One-time warpage protection and EMI shielding effect of Fan-Out Wafer Level Package (FOWLP) or Fanout-panel Wafer Level Package (FO-PLP) technology By implementing the process, the process is simple and low cost, and ultimately, the chip yield and reliability are improved.

1 is a fan-out wafer level package (FOWLP) overall process diagram having a bending reduction and EMI shielding function in accordance with the present invention.
FIG. 2 is a fanout-panel wafer level package (FO-PLP) overall process diagram having both warpage reduction and EMI shielding functionality in accordance with the present invention. FIG.
Figure 3 is a perspective view showing the warpage of the conventional fan-out wafer level package (FOWLP) process.
FIG. 4 is an overall perspective view of a silicon chip wafer having a metal thin film deposition process on top of an epoxy mold compound (EMC) during a fan-out wafer level package overall process having a warpage reduction and EMI shielding function according to the present invention. .
Figure 5 is another perspective view of a silicon chip wafer (silicon chip wafer) completed the metal thin film deposition process.
FIG. 6 illustrates a metal thin film deposition process on top of an epoxy mold compound (EMC) during a fanout-panel wafer level package (FO-PLP) overall process having warpage reduction and EMI shielding according to the present invention. Overall perspective view of a finished silicon chip wafer.

Hereinafter, a detailed description of the technical configuration according to the present invention with reference to the drawings.

The present invention provides a fan having both a bending reduction and an EMI shielding function of a fan-out wafer level package (FOWLP) or a fan-out panel wafer level package (FO-PLP). The out-of-package technology consists of a silicon chip and EMC, and directly forms the RDL and solder balls on the EMC, eliminating the need for conventional PCBs. This makes the package thinner and cheaper.

Fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) is a technology for mounting chips directly on silicon wafers rather than PCBs. It does not use PCB, it has low manufacturing cost, thin thickness, and has various advantages such as improved heat dissipation function, reduced power consumption, and improved frequency band.However, in high temperature EMC molding, EMC, carrier and Due to the difference in thermal expansion coefficient between silicon chips, warpage occurs in the wafer, which makes subsequent semiconductor processing difficult. It also causes problems with future chip reliability.

The present invention is a warpage generation problem which is a key issue of the fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) process The present invention seeks to solve the problem and to block the electromagnetic waves generated from the chip.

As shown in Figures 1 and 2,

The fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) process according to the present invention,

After the adhesive layer 20 is formed by applying an adhesive on the surface of the carrier 10, a first process S10 of disposing a silicon chip 30 on the adhesive layer 20 is performed. and,

A second step (S20) of molding the carrier 10 and the silicon chip 30 with an epoxy mold compound (EMC) 40,

The metal thin film 50 is deposited on the epoxy mold compound 40 and annealed to artificially generate residual stress of the metal, thereby preventing warping of the wafer, and simultaneously occurring in the silicon chip 30. Third process (S30) to shield the electromagnetic wave (EMI, Electro Magnetic Interference),

A fourth step (S40) of removing the carrier layer 10 by removing the adhesive layer 20 with a heat source or a chemical solution,

A fifth step (S50) of attaching a redistribution layer (RDL) 60 to a surface on which the silicon chip 30 is formed;

And a sixth step (S60) of attaching the solder ball 70 to the surface on which the redistribution layer (RDL) 60 is attached.

The fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) process is different in wafer form but by the same process. Is done.

That is, the fan-out wafer level package (FOWLP) is circular, but the fan-out panel wafer level package (FO-PLP) has a rectangular panel structure.

The rectangular panel structure has an advantage in that the same area reference chip arrangement area is wider than that of the circular structure. That is, the rectangular panel structure can produce more semiconductor chips than the circular structure.

Since the fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) has no process difference, the process is not classified. Let's take a closer look at.

<First Step (S10)>

A carrier 10 having the same size as a wafer is prepared, and an adhesive tape is attached to an upper surface of the carrier 10 to form an adhesive layer 20.

A single silicon chip 30 is arranged on the adhesive layer 20 by using a pick-and-place process.

<Second Step (S20)>

After arranging the single silicon chip 30 through the first process S10, the pre-baking process may be performed at a high temperature to prevent the single silicon chip 30 from moving during the liquid phase EMC molding process. pre-baking).

Then, in order to mold the liquid-type epoxy mold (EMC) 40, the carrier 10 and the chip 30 are molded into the liquid-type EMC 40 in a high temperature state.

The liquid EMC 40 molding temperature is set to 120 ~ 170 ℃.

After applying the liquid type EMC 40 at a high temperature and lowering the temperature to room temperature, the EMC 40 is molded while curing.

The liquid type EMC 40 is an abbreviation of epoxy molding compound, which is a part of a resin that forms an exterior of a semiconductor device, and is a thermosetting resin, and is a plastic molding material having a property of not being restored to its original state once cured. It is the most important polymer material used for packaging. This protects the semiconductor chip from the external environment such as heat, shock and chemicals, and prevents damage due to thermal shrinkage of the package itself.

A semiconductor chip is integrated with a large number of fine electric circuits, but cannot serve as a finished semiconductor product by itself, and can be easily damaged by external physical and chemical shocks. An epoxy resin is typically used to solve this problem. That is, the liquid EMC is a compound that can protect the semiconductor device from heat and impact with protection from external moisture or impurities.

The EMC (Epoxy Molding Compound),

With silica 80.0-92.0 wt%,

Epoxy resin 5.0 to 15.0 wt%,

1.5 to 7.3 wt% of any one or more hardeners selected from phenolic noblocks, acid anhydrides or amines,

0.1 to 1.0 wt% of a catalyst of amidazole or organic phosphines,

0.1 to 1.0 wt% of a higher fatty acid wax (release agent),

0.1 to 5.0 wt% of a retardant, antimony trioxide,

It is composed of a mixture of 0.1 to 1.0 wt% of a silane-based surface treatment agent.

When the amount of the silica used is less than 80.0 wt%, it is difficult to give excellent characteristics of wear resistance and mechanical strength, and when the amount of the silica used exceeds 92.0 wt%, there is a problem of increase in viscosity and poor workability. It is preferable to limit the amount to within the range of 80.0 to 92.0 wt%.

The epoxy resin is used a low viscosity epoxy resin, more specifically diglycidyl-ether of bisphenol F (DGEBF) is used.

This is to improve the fluidity of the filler when mixed with the filler to lower the defective product molding.

If the amount of the epoxy resin is less than 5.0 wt%, there is a problem inferior in workability, and if the amount of the epoxy resin is more than 15.0 wt%, the amount of other components may be relatively reduced, which may affect electrical, flame retardant, and mechanical properties. It is preferable to limit the amount of epoxy resin to be used in the range of 5.0 to 15.0 wt% based on the total amount of the composition.

The hardener (Hardener) plays a role in determining the basic properties such as fluidity, the mechanical and thermal properties of the cured product during molding.

In consideration of the compounding ratio with the epoxy resin, the curing agent is specifically formulated with a curing agent: epoxy resin in a ratio of 1: 1, 1: 2 or 1: 3.

When the amount of the curing agent is less than 1.5 wt%, the curing may not be performed properly. When the amount of the curing agent is more than 7.3 wt%, the amount of the curing agent is more economically necessary because the amount of the curing agent is more than necessary. It is preferable to limit the amount to 1.5 to 7.3 wt%.

The catalyst (Catalyst) is to determine the curability and storage stability, when the amount is less than 0.1 wt%, it is difficult to express such characteristics, when the amount exceeds 1.0 wt%, the synergistic effect of the curing and storage stability is insignificant Since it is meaningless, it is preferable to limit the amount of the catalyst used in the range of 0.1 to 1.0 wt% based on the amount of the total composition.

The higher fatty acid wax (release agent) is used to secure mold release properties during molding, and when the amount is less than 0.1 wt%, mold release may not be performed smoothly, and molding may not be performed smoothly, and may exceed 1.0 wt%. In this case, it is difficult to expect the improvement of the release property, meaningless, the amount of the higher fatty acid wax (release agent) is preferably limited to the range of 0.1 to 1.0 wt% based on the total amount of the composition.

The flame retardant (Retardant) is to control the flame retardancy, when the amount of use is less than 0.1 wt%, there is a problem that the flame retardant properties are falling, and when the amount exceeds 5.0 wt%, the degree of improvement of the flame retardant properties is insignificant and meaningless, The amount of the retardant to be used is preferably limited within the range of 0.1 to 5.0 wt% based on the total amount of the composition.

The silane-based surface treatment agent is to control the mechanical strength, thermal properties, etc., when the amount of the silane-based surface treatment agent is less than 0.1 wt%, there is a problem that the mechanical strength and thermal properties are falling, and when the amount exceeds 1.0 wt% Since the degree of change in thermal properties is insignificant and meaningless, it is preferable to limit the amount of the silane-based surface treating agent to be in the range of 0.1 to 1.0 wt% based on the total amount of the composition.

The physical properties of the EMC is Viscosity 85.652 poise, Density 2.00 × 10 ^-3 g / ㎣.

More specifically, 87.0 wt% of silica, 8.0 wt% of epoxy resin, 3.5 wt% of hardener of phenol noble, 0.5 wt% of catalyst of amidazole, and higher fatty acid wax ( Release agent) As an EMC (Epoxy mold compound) composed of a mixture of 0.2 wt%, 0.4 wt% of a retardant, antimony trioxide, and 0.4 wt% of a silane-based surface treatment agent, liquid EMC is used.

<Third Step (S30)>

This process is an important process of the present invention, and can solve the warpage problem of the wafer generated in the conventional fan-out wafer level package (FOWLP) process and at the same time can provide the effect of blocking the electromagnetic wave generated in the chip.

As described above, a general fan-out wafer level package (FOWLP) process involves applying an adhesive on a carrier wafer, placing a silicon chip, molding an epoxy mold compound (EMC), and then applying the adhesive to a heat source. Alternatively, the carrier is removed by using a chemical solution.

However, warpage occurs in a wafer due to a difference in coefficient of thermal expansion between the epoxy mold compound (EMC), a carrier, and a silicon chip during high temperature molding of the epoxy mold compound (EMC). That is, if the carrier is removed after the EMC molding process, the wafer is warped.

 Such warpages render subsequent semiconductor processes impossible and cause future chip reliability problems.

To solve this problem,

In this process, the metal thin film 50 is deposited and annealed on the epoxy mold compound 40 to artificially generate residual stress of the metal to prevent warping of the wafer. At the same time, the metal thin film 50 functions as an electromagnetic shield (EMI) of the silicon chip 30, and thus electromagnetic waves (EMI, Electro) generated from the silicon chip 30 without undergoing a separate process for EMI shielding. Magnetic Interference) shielding is possible.

As this third process is included in the entire fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP), the yield and reliability of the process are improved. In addition, it is possible to realize a low price due to the simplification of the process.

More specifically, this process will be described.

The metal thin film 50 may be formed by various methods such as deposition, plating or coating performed in semiconductor vacuum equipment. At this time, the deposition, plating or coating process is performed under various conditions such as various temperatures, pressures.

The thickness of the metal thin film 50 formed through the deposition, plating or coating process is 1.0 nm to 500 μm, and when the thickness is less than 1.0 nm, residual stress is too small to have an effect, and when the thickness exceeds 500 μm, Since there is a problem that the process takes a lot of time is too thick, the thickness of the metal thin film 50 is preferably limited to within the range of 1.0 nm ~ 500 ㎛.

The deposition is sputtering deposition.

The sputtering deposition is formed by evacuating the air in the chamber of the sputtering equipment to form an initial vacuum, and after adjusting the working vacuum degree by argon (Ar) 30 ~ 50 sccm into the reaction gas, Cu, Ni , Any one or two or more metals selected from Al, Ag, Au, or Cr as a metal target, and is deposited at 40 to 60 W of microwave power.

The plating is 5 to 10 wt% of any one or two or more metal salts selected from copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au) or chromium (Cr),

Boron hydride compounds, amineboranes, hypophosphorous acids, aldehydes, ascorbic acids, hydrazines, polyhydric phenols, polyhydric naphthol, phenolsulfonic acids, naphtholsulfonic acid, sulfinic acid, ethylene glycol, TEG (tetraethylene glycol), ethanol, 10 to 30 wt% of any one or two or more reducing agents selected from ascorbic acid, sodium borohydride, EDOT (3,4-ethylenedioxythiophene), D-glucose, sodium citrate, glycerol, formaldehyde and glyoxylic acid,

10 to 30 wt% of any one or two or more complexing agents selected from ethylene diamine tetraacetic acid (EDTA), citric acid or sodium citrate,

10 to 30 wt% of any one or two or more catalysts selected from nickel chloride hexahydrate, palladium (II), chloride (PdCl ₂ ) or dimethyl amine borane (DMAB),

10 to 30 wt% of any one or two or more surfactants selected from polyethylene glycol (PEG), amine salts, quaternary ammonium salts, sulfonium salts or phosphonium salts,

It is made by immersion in a plating bath at 40 to 90 ° C., pH 6 to 11, composed of a mixture of 30 to 50 wt% of any one or two or more pH adjusters selected from sodium hydroxide, potassium hydroxide, sulfuric acid or hydrochloric acid.

The plating bath is largely divided into a main component and an auxiliary component. The main components are salts of metals to be plated and reducing agents which give electrons to metal ions and reduce them to metals. In addition, the auxiliary component is used to extend the life of the plating bath and to improve the efficiency of the reducing agent and the surface characteristics of the plating. Auxiliary components include complexing agents, catalysts, surfactants, pH adjusters and the like.

The complexing agent forms a complex ion of the metal to stabilize the metal ions and serves to prevent the metal ions from being precipitated into the hydroxide in the alkaline solution.

In the plating, the pH has a great influence on the plating speed, the utilization efficiency of the reducing agent, and the formation of the coating film, and it is preferable to maintain a proper pH through the pH adjusting agent.

The coating is made by a cold spray method, any one selected from copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au) or chromium (Cr). Or preheating two or more metal powders of 5 to 50 μm to 420 to 450 ° C.,

The distance from the coating object is maintained at 35 to 45 mm under the conditions of the gas temperature 270 ~ 290 ℃, gas pressure 7 ~ 10 kgf / ㎠, powder feed amount 2.1 ~ 2.6 kg / h, injection speed 35 ~ 45 mm / s Coating.

The annealing takes place at various temperatures depending on the metal thin film formed by deposition, plating or coating.

The annealing temperature is for forming the uniformity and stable microstructure of the metal thin film and varies from metal material to metal material. However, in this process, if the annealing temperature is too high, EMC, adhesives such as fan-out wafer level package (FOWLP) or fan-out panel wafer level package (FO-PLP) materials Since the tape or the like is damaged or deformed, it is preferable to maintain the temperature below 300 ° C.

More specifically, it is preferable to maintain the annealing temperature within the range of 200 to 300 ° C.

In addition, the wafer warpage size may be artificially controlled by adjusting the deposition, plating or coating temperature, thickness, and annealing temperature of the metal thin film.

<4th process (S40)>

This step (S40) is a step of removing the carrier (10) by removing the adhesive layer 20 with a heat source or a chemical solution.

Even with this process, since the warpage occurrence problem of the wafer is eliminated in the previous process (S30), there is no problem of the warpage of the wafer so that the subsequent process can be smoothly performed.

<Fifth Step (S50)>

This step (S50) is a step of attaching the redistribution layer (RDL) 60 to the surface on which the silicon chip 30 is formed.

The redistribution layer (RDL) process refers to a process of redistribution so as to easily package an input / output terminal (pad) of the semiconductor chip 30.

<The sixth step (S60)>

This process (S60) is a process of attaching the solder ball 60 to the surface to which the redistribution layer RDL was attached.

The solder ball 60 is a conductive material that serves to transfer an electrical signal by connecting a semiconductor chip and a substrate.

The fan-out level package process having the bending reduction and EMI shielding function according to the present invention can prevent the warpage of the wafer by artificially generating the residual stress of the metal by depositing and annealing the metal thin film after the EMC molding process, and at the same time, By having an EMI (Electro Magnetic Interference) shield function on the chip to shield the electromagnetic waves generated from the chip, the process can be simplified and realized at low cost, and ultimately, the chip yield and reliability are improved. It is highly available.

10: carrier
20: adhesive layer
30: silicon chip
40: epoxy mold compound (EMC)
50: metal thin film
60: redistribution layer (RDL)
70: solder ball

Claims (7)

After forming an adhesive layer 20 by applying an adhesive (Adhesive) to the surface of the carrier 10, the first step (S10) for placing a silicon chip (30) on the adhesive layer 20,
A second step (S20) of molding the carrier 10 and the silicon chip 30 with a liquid-type epoxy mold compound 40;
Deposition and annealing the metal thin film 50 over the liquid-type epoxy mold (EMC) 40 artificially generates residual stress of the metal to prevent warpage of the wafer and simultaneously occurs in the silicon chip 30. Third process (S30) to shield the electromagnetic wave (EMI, Electro Magnetic Interference) to
A fourth step (S40) of removing the carrier layer 10 by removing the adhesive layer 20 with a heat source or a chemical solution,
A fifth step (S50) of attaching a redistribution layer (RDL) 60 to a surface on which the silicon chip 30 is formed;
It is a fan-out wafer level package (FOWLP) process comprising a sixth step (S60) for attaching the solder ball 70 to the surface to which the redistribution layer (RDL) 60 is attached Fan-out package process with reduced bending and EMI shielding.
After forming an adhesive layer 20 by applying an adhesive (Adhesive) to the surface of the carrier 10, the first step (S10) for placing a silicon chip (30) on the adhesive layer 20,
A second step (S20) of molding the carrier 10 and the silicon chip 30 with a liquid-type epoxy mold compound 40;
Deposition and annealing the metal thin film 50 over the liquid-type epoxy mold (EMC) 40 artificially generates residual stress of the metal to prevent warpage of the wafer and simultaneously occurs in the silicon chip 30. Third process (S30) to shield the electromagnetic wave (EMI, Electro Magnetic Interference) to
A fourth step (S40) of removing the carrier layer 10 by removing the adhesive layer 20 with a heat source or a chemical solution,
A fifth step (S50) of attaching a redistribution layer (RDL) 60 to a surface on which the silicon chip 30 is formed;
Fan-out panel wafer level package (FO-PLP) comprising a sixth process (S60) for attaching the solder ball 70 to the surface to which the redistribution layer (RDL) 60 is attached Fan-out package process with reduced bending and EMI shielding.
The method according to claim 1 or 2,
The metal thin film 50 is formed by depositing, plating, or coating any one or two or more metals selected from Cu, Ni, Al, Ag, Au, or Cr to simultaneously reduce warpage and EMI shielding. Having a fan-out package process.
The method according to claim 1 or 2,
The metal thin film 50 is formed by sputtering deposition,
The sputtering deposition is formed by evacuating the air in the chamber of the sputtering equipment to form an initial vacuum, and after adjusting the working vacuum degree by argon (Ar) 30 ~ 50 sccm into the reaction gas, Cu, Ni Reduction of warpage and EMI shielding, characterized in that the deposition of microwave power 40 ~ 60 W using any one or two or more metals selected from Al, Ag, Au or Cr as a metal target At the same time having a fan-out package process.
The method according to claim 1 or 2,
The metal thin film 50 is formed by plating,
The plating is 5 to 10 wt% of any one or two or more metal salts selected from copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au) or chromium (Cr),
Boron hydride compounds, amineboranes, hypophosphorous acids, aldehydes, ascorbic acid, hydrazine, polyhydric phenols, polyhydric naphthol, phenolsulfonic acid, naphtholsulfonic acid, sulfinic acid, ethylene glycol, TEG (tetraethylene glycol), ethanol, 10 to 30 wt% of any one or two or more reducing agents selected from ascorbic acid, sodium borohydride, EDOT (3,4-ethylenedioxythiophene), D-glucose, sodium citrate, glycerol, formaldehyde and glyoxylic acid,
10 to 30 wt% of any one or two or more complexing agents selected from ethylene diamine tetraacetic acid (EDTA), citric acid or sodium citrate,
10 to 30 wt% of any one or two or more catalysts selected from nickel chloride hexahydrate, palladium (II), chloride (PdCl ₂ ) or dimethyl amine borane (DMAB),
10 to 30 wt% of any one or two or more surfactants selected from polyethylene glycol (PEG), amine salts, quaternary ammonium salts, sulfonium salts or phosphonium salts,
It is made by immersing in a plating bath of 40 ~ 90 ℃, pH 6-11, which is composed of a mixture of 30 to 50 wt% of any one or two or more pH adjusters selected from sodium hydroxide, potassium hydroxide, sulfuric acid or hydrochloric acid. Fan-out package process with simultaneous bending reduction and EMI shielding.
The method according to claim 1 or 2,
Metal thin film 50 is formed by a cold spray (Cold spray) coating,
The cold spray coating is any one or two or more selected from copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au) or chromium (Cr). Preheat 50 μm metal powder to 420-450 ° C.,
The distance from the coating object is maintained at 35 to 45 mm under the conditions of the gas temperature 270 ~ 290 ℃, gas pressure 7 ~ 10 kgf / ㎠, powder feed amount 2.1 ~ 2.6 kg / h, injection speed 35 ~ 45 mm / s Fan-out package process with reduced warpage and EMI shielding, characterized in that the coating process.
The method according to claim 1 or 2,
Annealing is a fan-out package process with both bending reduction and EMI shielding, characterized in that it is performed in the temperature range of 200 ~ 300 ℃.

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