KR20150048613A - Wafer Level Packaging Device - Google Patents
Wafer Level Packaging Device Download PDFInfo
- Publication number
- KR20150048613A KR20150048613A KR1020140035462A KR20140035462A KR20150048613A KR 20150048613 A KR20150048613 A KR 20150048613A KR 1020140035462 A KR1020140035462 A KR 1020140035462A KR 20140035462 A KR20140035462 A KR 20140035462A KR 20150048613 A KR20150048613 A KR 20150048613A
- Authority
- KR
- South Korea
- Prior art keywords
- packaging device
- level packaging
- substrate
- reflow
- wafer level
- Prior art date
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 92
- 239000002184 metal Substances 0.000 claims abstract description 40
- 229910052751 metal Inorganic materials 0.000 claims abstract description 40
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 239000012212 insulator Substances 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 73
- 230000000903 blocking effect Effects 0.000 claims description 4
- 239000011247 coating layer Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 238000009736 wetting Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 235000012239 silicon dioxide Nutrition 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 52
- 238000000034 method Methods 0.000 description 19
- 238000005530 etching Methods 0.000 description 17
- 239000010408 film Substances 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910052718 tin Inorganic materials 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000012768 molten material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000009461 vacuum packaging Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Micromachines (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
A wafer level packaging device is provided.
The packaging element of the present invention comprises:
A lower sensor substrate on which a sensor is formed; An upper cap substrate provided on the lower sensor substrate and having a cavity formed on one surface thereof so that the sensor can be received; And a metal solder layer for bonding the lower sensor substrate and the upper cap substrate, wherein the upper cap substrate is an SOI wafer, and the cavity is formed by sequentially removing the lower Si layer and the insulator layer constituting the SOI wafer .
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level packaging device, and more particularly, to a wafer level packaging device using the CAP substrate as an SOI wafer in a wafer level packaging of a sensor substrate on which a CAP substrate and a sensor are formed.
In general, an infrared sensor is a sensor that detects infrared rays emitted by an object and measures the presence or non-contact temperature of an object by using the magnitude of thermal energy of the infrared ray. Such an infrared sensor is applied to various fields. For example, it is possible to detect the presence of a person in the automatic door, automatically open / close the door, automatically turn on / off the light, and detect security devices or the presence of a human body in the middle of the night, An air conditioner or the like for controlling the air conditioner.
2. Description of the Related Art [0002] Conventionally, infrared sensing devices commonly used in such infrared sensors include heat absorbing sensing devices such as pyroelectric, thermopile, and bolometer. Among these infrared sensing elements, the most excellent and smallest volume is a bolometer. Such a bolometer detects an infrared ray by measuring a change in electric resistance due to a rise in temperature when the infrared ray is absorbed from the human body. Other sensing devices 10 7 -10 8 ㎝㎐ 1/2 W, while showing a low infrared sensitivity of -1 degree, the infrared sensitivity of the meter is a ball 10 8 ~ 10 9 ㎝㎐ 1/2 W - 1 is about . Bromomer materials require high TCR (Temperature Coefficient of Resistance) values, low device resistance, and interconnection with IC processes.
However, in the case of the infrared sensor, the infrared sensor is manufactured as a chip on a wafer, separated into individual chips by dicing, and individually packaged in a vacuum chamber. At this time, although the vacuum packaging process is a process necessary for maintaining the performance of the infrared sensor, there is a problem that a large amount of cost is required to occupy a large part of the total cost of the MEMS device. In addition, the size of the cap and the like used in the infrared sensor itself is a serious obstacle to miniaturization of the infrared sensor.
Accordingly, a technique for manufacturing a MEMS sensor using wafer-level packaging technology has been proposed as an invention for solving the above-mentioned prior art. 1, a
In the case of such a MEMS sensor device, it is general to use a Si wafer as a cap wafer. Thus, when using a Si wafer as a cap wafer, the cap wafer on top of the cavity, as in Figure 1, does not have a smooth surface and has a
However, when the upper surface of the cap wafer forming the cavity has a predetermined roughness as described above, as shown in FIG. 1, incident light is scattered and the linearity of light is lowered. Accordingly, There is a problem that it gets worse.
Therefore, in manufacturing a MEMS sensor device using wafer level packaging, an alternative that can solve the above-mentioned problems is emerging.
SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a method of manufacturing a MEMS device using wafer level packaging, And it is an object of the present invention to provide a wafer level packaging device capable of improving the sensing performance of a MEMS sensor element by smoothing the cap wafer surface above the cavity by suppressing erosion.
Further, the technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems which are not mentioned can be understood from the following description in order to clearly understand those skilled in the art to which the present invention belongs .
According to an aspect of the present invention,
A lower sensor substrate on which a sensor is formed;
An upper cap substrate provided on the lower sensor substrate and having a cavity formed on one surface thereof so that the sensor can be received; And
And a metal solder layer for bonding the lower sensor substrate and the upper cap substrate,
The upper cap substrate is an SOI wafer, and
And the cavity is formed by sequentially removing the lower Si layer and the insulator layer constituting the SOI wafer.
It is also preferable to form the dicing grooves by removing the left and right side lower portions of the upper cap substrate to a predetermined height.
Further, by forming the dicing grooves, the electrode pads can be opened by the dicing saw.
It is preferable that the dicing grooves are formed together when the cavity is formed.
It is preferable that the insulator layer is a SiO 2 layer.
It is preferable that a first reflow shielding layer is formed on the lower sensor substrate so as to prevent reflow of the molten metal solder layer generated when the upper and lower substrates are bonded between the sensor and the metal solder layer.
The lower sensor substrate may include an electrode pad electrically connected to an external signal electrode.
Also, a second reflow shielding layer may be formed on the lower sensor substrate between the electrode pad and the metal solder layer.
It is preferable that the reflow blocking film has the same composition as the wetting layer formed on the upper cap substrate.
Also, on the lower sensor substrate, a first reflow receiving groove may be formed between the sensor and the first reflow preventing film.
Also, on the lower sensor substrate, a second reflow receiving groove may be formed between the electrode pad and the second reflow shielding film.
Further, a metal coating layer made of the same metal as the reflow shielding film may be formed in the reflow receiving recess.
The sensor may be an infrared MEMS sensing sensor.
A getter may be formed in the cavity of the upper cap substrate.
Further, an infrared filter may be formed on at least one surface of the upper cap substrate.
The present invention having the above-described configuration has the following effects.
First, the present invention uses a wafer-level packaging as an upper cap wafer to fabricate a device, and the upper surface of the cavity, which is formed by forming the cavity, is smoothed to reduce scattering of incident light and improve straightness, The sensing ability of the sensing element can be improved.
Second, left and right side lower portions of the upper cap wafer are etched away to form a dicing groove, thereby preventing damage to the lower sensor substrate due to dicing in the dicing step.
1 is a schematic cross-sectional view of an infrared sensing sensor manufactured using a conventional wafer level packaging.
2 is a schematic cross-sectional view of a wafer level packaging device according to an embodiment of the invention.
3 is a schematic view showing a process of forming a cavity in an SOI wafer which is an upper cap substrate according to an embodiment of the present invention.
4 is a graph showing the linearity of incident light when an SOI wafer is used as an upper cap substrate.
5 is a schematic cross-sectional view of a wafer level packaging device according to another embodiment of the present invention.
6 is a schematic cross-sectional view of a wafer level packaging device according to another embodiment of the present invention.
7 is a schematic sectional view showing a lower sensor substrate of a wafer level packaging device according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.
The same reference numerals are used for portions having similar functions and functions throughout the drawings.
In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to include an element does not exclude other elements unless specifically stated otherwise, but may also include other elements.
2 is a schematic cross-sectional view of a wafer level packaging device according to an embodiment of the invention. 2, the packaging device of the present invention includes a
The
First, the packaging device of the present invention includes a
In the packaging device of the present invention, the
The present invention is not limited to the type of the
The packaging device 100 of the present invention is provided on the
In the present invention, the
Also, the
3 is a schematic view showing a process of forming a
3 (a), the
3 (b), in order to form a cavity at a predetermined position of the
Next, as shown in FIG. 3 (c), the exposed
On the other hand, the
4 is a diagram schematically showing the straightness of incident light when an SOI wafer is used as the upper cap substrate.
As described above, when the SOI wafer is used as the upper cap substrate, etching of the insulator layer (SiO 2 ) of the SOI wafer is required to remove the etching for forming the cavity, thereby forming the upper Si layer 175 ) Surface is not affected by the SiO 2 etching, and thus has a substantially smooth surface property. Therefore, as shown in FIG. 4, such a smooth surface property improves the straightness of the incident light and improves the detection performance of the downward detection sensor. As shown in FIG. 1, the upper surface of the cavity of the upper cap substrate has a rough surface, which contrasts with the prior art in which the sensing performance of the sensing element must be degraded in accordance with the scattering of incident light.
In the present invention, an infrared filter may be formed on at least one of the inner and outer surfaces of the
One or more getters may be formed on the inner surface of the
In the present invention, as shown in FIG. 5, it is preferable to form the dicing grooves V by removing the left and right side lower portions of the
Further, in the present invention, the
In the present invention, the dicing groove V may be formed through the above-described conventional etching process. Preferably, when the
The packaging device 100 of the present invention includes a
In the present invention, the
The present invention is not limited to the specific bonding method using the
When the
6, the
In the present invention, the
In the present invention, the material forming the
The molten
Accordingly, in the present invention, the second
7 is a schematic sectional view showing a lower sensor substrate of a wafer level packaging device according to another embodiment of the present invention.
7, in the present invention, a first
7, a second
In the present invention, the first and second
In another embodiment of the present invention, a
While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of course, this is possible. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the equivalents as well as the claims that follow.
110:
125a, b ..... Reflow accommodating groove
130 .........
150
170 ........ Upper cap substrate
Claims (15)
An upper cap substrate provided on the lower sensor substrate and having a cavity formed on one surface thereof so that the sensor can be received; And
And a metal solder layer for bonding the lower sensor substrate and the upper cap substrate,
The upper cap substrate is an SOI wafer, and
Wherein the cavity is formed by sequentially removing a lower Si layer and an insulator layer that constitute the SOI wafer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020130127568 | 2013-10-25 | ||
KR20130127568 | 2013-10-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20150048613A true KR20150048613A (en) | 2015-05-07 |
KR101569191B1 KR101569191B1 (en) | 2015-11-16 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020140035462A KR101569191B1 (en) | 2013-10-25 | 2014-03-26 | Wafer Level Packaging Device |
Country Status (1)
Country | Link |
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KR (1) | KR101569191B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019054716A1 (en) * | 2017-09-18 | 2019-03-21 | 주식회사 티지오테크 | Method for manufacturing frame integrated mask |
KR20200136215A (en) * | 2019-05-27 | 2020-12-07 | 주식회사 아이디피 | Wafer level packaging method with solderball for Cap wafer, and Cap wafer |
-
2014
- 2014-03-26 KR KR1020140035462A patent/KR101569191B1/en active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2019054716A1 (en) * | 2017-09-18 | 2019-03-21 | 주식회사 티지오테크 | Method for manufacturing frame integrated mask |
CN111406127A (en) * | 2017-09-18 | 2020-07-10 | 悟勞茂材料公司 | Method for manufacturing frame-integrated mask |
KR20200136215A (en) * | 2019-05-27 | 2020-12-07 | 주식회사 아이디피 | Wafer level packaging method with solderball for Cap wafer, and Cap wafer |
Also Published As
Publication number | Publication date |
---|---|
KR101569191B1 (en) | 2015-11-16 |
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