KR101613412B1 - Method for manufacturing wafer Level Packaging Device - Google Patents

Method for manufacturing wafer Level Packaging Device Download PDF

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Publication number
KR101613412B1
KR101613412B1 KR1020150052228A KR20150052228A KR101613412B1 KR 101613412 B1 KR101613412 B1 KR 101613412B1 KR 1020150052228 A KR1020150052228 A KR 1020150052228A KR 20150052228 A KR20150052228 A KR 20150052228A KR 101613412 B1 KR101613412 B1 KR 101613412B1
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South Korea
Prior art keywords
substrate
forming
layer
sensor
pattern
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KR1020150052228A
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Korean (ko)
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김형원
안미숙
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(주)유우일렉트로닉스
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A method of manufacturing a wafer level packaging device is provided.
The present invention provides a method of manufacturing a semiconductor device, comprising: forming a silicon nitride (SOG) substrate; forming a TSV pattern at a predetermined position of the silicon structure layer; Forming an insulating layer on a surface of the SOG substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer; Electroplating the surface of the SOG substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern; Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface; Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate; Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And a step of polishing and removing the glass carrier layer of the SOG substrate.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a wafer level packaging device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a manufacturing method of a wafer level packaging device, and more particularly, to a method of manufacturing a wafer level packaging device by forming an electrode using TSV (Through Silicon Via) Level packaging device.

In general, an infrared sensor is a sensor that detects infrared rays emitted by an object and measures the presence or absence of an object by using the magnitude of thermal energy of the infrared ray. Such an infrared sensor is applied to various fields. For example, it is possible to detect the presence of a person in the automatic door, automatically open / close the door, automatically turn on / off the light, and detect security devices or the presence of a human body in the middle of the night, An air conditioner or the like for controlling the air conditioner.

2. Description of the Related Art [0002] Conventionally, infrared sensing devices commonly used in such infrared sensors include heat absorbing sensing devices such as pyroelectric, thermopile, and bolometer. Among these infrared sensing elements, the most excellent and smallest volume is a bolometer. Such a bolometer detects an infrared ray by measuring a change in electric resistance due to a rise in temperature when the infrared ray is absorbed from the human body. Other sensing devices 10 7 -10 8 ㎝㎐ 1/2 W infrared sensitivity 10 of -1 degree, as seen in the meter, while showing a low infrared sensitivity of 8 ~ 10 9 ㎝㎐ 1/2 W - 1 , so the performance Is excellent. Bromomer materials require high TCR (Temperature Coefficient of Resistance) values, low device resistance, and interconnection with IC processes.

1, a MEMS sensor is electrically connected to an external terminal by wire bonding, and the inside of the element is maintained in a vacuum state. 1, reference numeral 130 denotes an IR window. Therefore, the infrared sensing element of Fig. 1 basically has a problem that the device manufacturing cost is high and the efficiency is low.

In order to solve the above problem, an infrared sensing device manufactured by wafer level packaging is shown in FIG. However, in the case of the infrared sensing device shown in FIG. 2, the MEMS sensor is electrically connected to the outside through wire bonding at an external electrode formed on the substrate. However, there is a problem of sensor handling because the bonded wire tends to be short-circuited electrically off the pad when handling the sensor. Generally, an epoxy molding agent is used to protect the bonded wire, but it is difficult to expose the cavity into which the infrared ray is incident. There is also a technical difficulty in maintaining the flatness of the epoxy molding agent during molding. 2, reference numeral 210 denotes a lower sensor substrate, and reference numeral 230 denotes an upper cap substrate.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a method of manufacturing a MEMS device using wafer level packaging, And it is an object of the present invention to provide a manufacturing method of a wafer level packaging device which can avoid bonding and is excellent in handleability of the device as a whole.

Further, the technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems which are not mentioned can be understood from the following description in order to clearly understand those skilled in the art to which the present invention belongs .

According to an aspect of the present invention,

A step of forming a TSV pattern on a predetermined position of the silicon structure layer after providing a SOG (Silicon on Glass) substrate;

Forming an insulating layer on a surface of the SOG substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer;

Electroplating the surface of the SOG substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern;

Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface;

Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate;

 Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And

And a step of polishing and removing the glass of the SOG substrate.

Further, according to the present invention,

Forming a silicon on insulator (SOI) substrate and then forming a TSV pattern at a predetermined position of the silicon structure layer;

Forming an insulating layer on the surface of the SOI substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer;

Electroplating the surface of the SOI substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern;

Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface;

Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate;

 Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And

And a step of polishing and removing the back side silicon of the SOI substrate.

The metal solder layer may be formed of at least one selected from Au, AuSn, Sn, Cu and Ag.

It is more preferable that the metal solder layer includes 80wt% of Au + 20wt% of Sn.

The sensor may be an infrared MEMS sensing sensor.

The present invention having the above-

First, since an external electrode is not formed in the infrared sensing element, it is not necessary to perform wire bonding for connection with an external terminal, and thus handling is very excellent.

Second, since the thickness of the sub-substrate can be easily lowered by applying the TSV process, the thickness of the sensing device as a whole can be lowered, which is advantageous for thinning the device.

1 is a schematic cross-sectional view of a conventional infrared ray detection sensor.
2 is a schematic cross-sectional view of a conventional wafer level packaging device.
3 (a) to 3 (m) are schematic views showing a manufacturing process of a wafer level packaging device according to an embodiment of the present invention.
4 is a product configuration diagram of a wafer level packaging device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a method of manufacturing a wafer level packaging device according to an embodiment of the present invention includes: a step of forming a TSV pattern on a predetermined position of a silicon structure layer after providing a SOG (Silicon on Glass) substrate; Forming an insulating layer on a surface of the SOG substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer; Electroplating the surface of the SOG substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern; Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface; Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate; Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And polishing the glass of the SOG substrate.

3 (a) to 3 (m) are schematic views showing a manufacturing process of a wafer level packaging device according to an embodiment of the present invention.

As shown in FIG. 3 (a-b), in the present invention, a silicon nitride on glass (SOG) substrate is first formed and then a TSV pattern is formed on a predetermined position of the silicon structure layer 330.

The SOG substrate has a structure in which a silicon structure layer 330 and a glass carrier layer 310 are laminated. In general, the glass carrier layer 310 exhibits a transparent property as a whole.

In the present invention, after the photoresist is applied to the surface of the silicon structure layer 330, the TSV pattern 311 can be formed using a conventional photolithography method.

3 (cd), an insulating layer 312 is formed on the surface of the SOG substrate on which the TSV pattern 311 is formed, and then a seed layer 313 is formed on the insulating layer 312 . That is, as shown in FIG. 3 (c), the insulating layer 312 is formed by thermal oxidation on the surface of the SOG substrate where the TSV pattern 311 is formed. In the present invention, the SiO2 layer may be used as the insulating layer.

3 (d), a seed layer 313 is formed on the insulating layer 312. The seed layer 313 is formed to facilitate plating in a subsequent electrolytic plating process Process. In the present invention, Ti, TiN, Au, or Cu may be used for forming the seed layer 313.

Subsequently, in the present invention, as shown in FIG. 3 (ef), the surface of the SOG substrate on which the seed layer 313 is formed is electroplated so that the formed TSV pattern 311 is filled, and then the plating layer The electrolytic plating layer 315 is removed by polishing. In the present invention, the electroplating layer 315 may be formed by electrolytic deposition of Au or Cu.

Next, in the present invention, as shown in FIG. 3 (gh), an electrode 316 for a sensor having a predetermined pattern is formed on the substrate, and then an insulating layer 317 is formed on the surface of the electrode 316. 3 (g), for example, Ti, Al, or TiN can be used for electrode production to form the sensor electrode 316 having a predetermined pattern on the substrate. Then, as shown in FIG. 3 (h), an insulating layer is formed by CVD TEOS or SiO 2 or the like, and subsequently the formed insulating layer is polished to flatten its surface.

3 (i-k), a sensor 318 is formed at a predetermined position on the surface of the substrate, and a metal solder layer 350 is formed on the TSV pattern. The metal solder layer 350 serves to bond the SOG substrate to an upper cap substrate 370 described later.

The metal solder layer 350 may be formed in a pattern using a lift-off process or the like to package the lower SOG substrate and the upper cap substrate 370 at the wafer level.

In the present invention, the metal solder layer 350 may be formed of one or more materials selected from Au, AuSn, Sn, Cu, and Ag. More preferably, a material containing Au and Sn is used. In an embodiment of the present invention, the metal solder layer 350 may include 80wt% of Au + 20wt% of Sn, and another example may be 10wt% of Au + 90wt% of Sn. Here, Au and Sn may be deposited in the form of a multilayer thin film, or an alloy of Au and Sn may be deposited in the form of a thin film.

In addition, the present invention is not limited to the type of the sensor 318, and the sensor may be a MEMS sensor, for example, an infrared sensor.

In the present invention, the formed sensor 318 removes the sacrificial layer as shown in FIG. 3 (k).

Next, in the present invention, a cap substrate 370 having a cavity 375 in which a sensor 318 can be received is formed on a substrate provided as described above with reference to FIG. 3 (l) . This bonding is performed through the metal solder layer 350, and the lower SOG substrate and the upper cap substrate 370 can be bonded at the wafer level to be packaged.

And the cavity 375 is required to have a predetermined height and length since wafer level packaging is required to accommodate the sensor 318 of the lower SOG substrate described below.

In the present invention, a getter 377 may be formed in the cavity 375. These getters function to absorb the gas released by the internal material after wafer level packaging and to maintain the degree of vacuum inside the package, and can be formed using a conventional shadow masking or lift-off process.

In the present invention, as shown in FIG. 3 (m), the infrared sensor may be manufactured by polishing and removing the glass carrier layer 310 of the SOG substrate.

4 is a schematic block diagram of a product including a wafer level packaging device according to an embodiment of the present invention. 4, it can be seen that the wafer level packaging device 430 manufactured according to the method of the present invention is ball bonded 420 to the lower substrate 410, and on the side of the packaging device, 450 are ball bonded (420) to the lower substrate (410). Unlike the prior art, external electrode pads are not formed on the left and right sides of the lower sensor substrate of the wafer level packaging device 430, and the sensing signals of the sensors are transmitted to the lower substrate 410 through the TSV through electrodes. A signal arriving at the lower substrate 410 is transmitted to the ROIC substrate 450 through a wiring not shown and the sensing signal of the packaging device 430 is analyzed by the control circuit of the substrate 450, can do.

According to another aspect of the present invention, there is provided a method of manufacturing a wafer level packaging device, including: forming a silicon on insulator (SOI) substrate and then forming a TSV pattern at a predetermined position of the silicon structure layer; Forming an insulating layer on the surface of the SOI substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer; Electroplating the surface of the SOI substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern; Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface; Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate; Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And polishing and removing the back side silicon carrier layer of the SOI substrate.

In the case of the present invention, the lower sensor substrate used is not an SOG substrate but an SOI substrate. The SOI wafer (substrate) is a structure in which a silicon structure layer / an insulator layer / a silicon carrier layer are laminated. Usually, the thickness of the silicon structure layer is 100 mu m, the thickness of the silicon carrier layer is 300 to 500 mu m, The thickness is in the range of 1 mu m. In the present invention, the insulator layer may be a SiO 2 oxide layer.

On the other hand, in the case of the present invention, after the wafer level bonding of the upper and lower substrates, when the back side silicon carrier layer of the SOI substrate is polished and removed, the inner insulating layer may also be removed at the same time.

311 ... TSV pattern 312 ............. Insulating layer
313 .............. Seed layer 315 .............. Electroplating layer
316 .............. Electrode for sensor 318 .............. Sensor

Claims (6)

A step of forming a TSV pattern on a predetermined position of the silicon structure layer after providing a SOG (Silicon on Glass) substrate;
Forming an insulating layer on a surface of the SOG substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer;
Electroplating the surface of the SOG substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern;
Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface;
Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate;
Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And
And polishing and removing the glass carrier layer of the SOG substrate.
The method of claim 1, wherein the sensor is an infrared MEMS sensing sensor.
The method according to claim 1, wherein the metal solder layer is formed of at least one selected from the group consisting of Au, AuSn, Sn, Cu, and Ag.
Forming a silicon on insulator (SOI) substrate and then forming a TSV pattern at a predetermined position of the silicon structure layer;
Forming an insulating layer on the surface of the SOI substrate on which the TSV pattern is formed, and then forming a seed layer on the insulating layer;
Electroplating the surface of the SOI substrate on which the seed layer is formed so that the formed TSV pattern is filled, and then polishing and removing the electrolytic plating layer excluding the plating layer filled in the pattern;
Forming an electrode for a sensor having a predetermined pattern on the substrate, and forming an insulating layer on the surface;
Forming a metal solder layer on the TSV pattern after forming a sensor at a predetermined position on the surface of the substrate;
Depositing a cap substrate on which a cavity capable of accommodating a sensor is formed, and adhering the cap substrate on the substrate; And
And polishing and removing the back side silicon of the SOI substrate.
5. The method of claim 4, wherein the sensor is an infrared MEMS sensing sensor.
5. The method of claim 4, wherein the metal solder layer is formed of at least one selected from Au, AuSn, Sn, Cu, and Ag.
KR1020150052228A 2015-04-14 2015-04-14 Method for manufacturing wafer Level Packaging Device KR101613412B1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021658A1 (en) * 2016-07-26 2018-02-01 주식회사 신성씨앤티 Mems sensor and method for manufacturing same
WO2019017539A1 (en) * 2017-07-21 2019-01-24 (주)에이엠티솔루션 Wireless passive surface acoustic wave wafer in wafer level packaging manner for semiconductor chamber temperature measurement
CN110349986A (en) * 2019-07-05 2019-10-18 中国电子科技集团公司第五十八研究所 A kind of image sensor wafer level packaging methods and encapsulating structure
US10951195B2 (en) 2019-04-08 2021-03-16 Samsung Electro-Mechanics Co., Ltd. Acoustic resonator filter package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070045780A1 (en) 2005-09-01 2007-03-01 Salman Akram Methods of forming blind wafer interconnects, and related structures and assemblies
US20120153498A1 (en) 2010-12-16 2012-06-21 Un-Byoung Kang Semiconductor Device and Method of Forming the Same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070045780A1 (en) 2005-09-01 2007-03-01 Salman Akram Methods of forming blind wafer interconnects, and related structures and assemblies
US20120153498A1 (en) 2010-12-16 2012-06-21 Un-Byoung Kang Semiconductor Device and Method of Forming the Same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021658A1 (en) * 2016-07-26 2018-02-01 주식회사 신성씨앤티 Mems sensor and method for manufacturing same
WO2019017539A1 (en) * 2017-07-21 2019-01-24 (주)에이엠티솔루션 Wireless passive surface acoustic wave wafer in wafer level packaging manner for semiconductor chamber temperature measurement
KR20190010796A (en) * 2017-07-21 2019-01-31 주식회사 에이엠티솔루션 Passive and wireless tc wafer using wlp surface acoustic wave
KR101972793B1 (en) * 2017-07-21 2019-04-29 (주)에이엠티솔루션 Passive and wireless tc wafer using wlp surface acoustic wave
US10951195B2 (en) 2019-04-08 2021-03-16 Samsung Electro-Mechanics Co., Ltd. Acoustic resonator filter package
CN110349986A (en) * 2019-07-05 2019-10-18 中国电子科技集团公司第五十八研究所 A kind of image sensor wafer level packaging methods and encapsulating structure

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