KR20130137058A - Array substrate and method of fabricating the same - Google Patents

Abstract

The present invention provides a liquid crystal display device including a gate wire; a gate electrode connected to the gate wire; a gate insulating film covering the gate wire and the gate electrode; a source electrode and a drain electrode positioned on the gate electrode and separated from each other by corresponding to the gate electrode; a pixel electrode placed on the gate insulating film and extended from the drain electrode; a data wire which is placed on the gate insulating film, is composed of a top layer of a low resistance metal material and a bottom layer extended from the source electrode, and intersects with the gate wire; and an oxide semiconductor layer placed on the drain electrode and the source electrode by corresponding to the gate electrode. The source electrode, the drain electrode, the pixel electrode, and the data wire are formed of indium-tin-oxide or indium-zinc-oxide.

Description

[0001] The present invention relates to an array substrate and a manufacturing method thereof,

The present invention relates to an array substrate, and more particularly, to an array substrate capable of improving the characteristics of a thin film transistor by using an oxide semiconductor layer excellent in stability of a device characteristic and reducing a parasitic capacitance caused by overlapping between a gate electrode and a source electrode, ≪ / RTI >

Recently, the display field for processing and displaying a large amount of information has been rapidly developed as society has entered into a full-fledged information age. Recently, flat panel display devices having excellent performance such as thinning, light weight, and low power consumption have been developed A liquid crystal display or an organic electroluminescent device has been developed to replace a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling voltage on and off for each pixel, The ability is excellent and is getting the most attention.

In such a liquid crystal display device, an array substrate including a thin film transistor, which is a switching element, is essentially constituted in order to turn on / off each pixel region.

1 is a cross-sectional view of a portion of a conventional array substrate constituting a liquid crystal display device in which one pixel region is cut including a thin film transistor.

As shown in the figure, in the switching region TrA in a plurality of pixel regions P in which a plurality of gate lines (not shown) and a plurality of data lines 33 are defined in the array substrate 11, gate electrodes 15 are formed. A gate insulating layer 18 is formed on the entire surface of the gate electrode 15 and sequentially formed thereon an active layer 22 of pure amorphous silicon and an ohmic contact layer 26 of impurity amorphous silicon. (28) are formed.

A source electrode 36 and a drain electrode 38 are formed on the ohmic contact layer 26 to correspond to the gate electrode 15. The gate electrode 15, the gate insulating film 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38, which are sequentially stacked in the switching region TrA, constitute a thin film transistor Tr.

A protective layer 42 is formed on the entire surface of the source and drain electrodes 36 and 38 and the exposed active layer 22 and includes a drain contact hole 45 exposing the drain electrode 38 And a pixel electrode 50 is formed on the passivation layer 42 and is independent of each pixel region P and is in contact with the drain electrode 38 through the drain contact hole 45. At this time, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 is formed under the data line 33 with the same material forming the ohmic contact layer 26 and the active layer 22 Is formed.

The active layer 22 of pure amorphous silicon is formed on the upper side of the semiconductor layer 28 of the thin film transistor Tr constituting the switching region TrA in the conventional array substrate 11 having the above- The first thickness t1 of the portion where the ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion where the ohmic contact layer 26 is removed are differently formed. The difference in thickness (t1? T2) of the active layer 22 is due to the manufacturing method, and the difference in thickness (t1? T2) of the active layer 22, more precisely the source and drain And the thickness of the exposed portion between the electrodes is reduced, thereby deteriorating the characteristics of the thin film transistor Tr.

Therefore, recently, as shown in Fig. 2 (sectional view of one pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer), a thin film using an oxide semiconductor material without requiring an ohmic contact layer Transistors have been developed.

The thin film transistor Tr using the oxide semiconductor material includes a gate electrode 73, a gate insulating film 75, an oxide semiconductor layer 77, a source electrode 81 and a drain electrode 83. In addition, a pixel electrode 89 connected to the drain electrode 83 may be provided, and a passivation layer 85 may be formed between the drain electrode 83 and the pixel electrode 89.

Since the oxide semiconductor layer 77 does not need to form an ohmic contact layer, the oxide semiconductor layer 77 may be formed on the oxide semiconductor layer 77 in order to form a spaced apart ohmic contact layer made of impurity amorphous silicon, which is similar in material to an array substrate having a semiconductor layer made of a conventional amorphous silicon It is not necessary to be exposed to the progressive dry etching, so that deterioration of the characteristics of the thin film transistor Tr can be prevented.

However, when the oxide semiconductor layer 77 is exposed to the etchant used for patterning the metal layer for forming the source electrode 81 and the drain electrode 83, the oxide semiconductor layer 77 is etched and removed without the selective ratio with respect to the metal layer, The characteristics of the thin film transistor Tr can be affected.

Therefore, when patterning for forming the source and drain electrodes 81 and 83, the oxide semiconductor layer 77 located under the oxide semiconductor layer 77 is exposed to the etching solution reacting with the metal material forming the source and drain electrodes 81 and 83 The etch stopper 79 is formed corresponding to the central portion of the oxide semiconductor layer 77. [

However, in order to manufacture the conventional array substrate 71 including the oxide semiconductor layer 77 and the thin film transistor Tr having the etch stopper 79 on the oxide semiconductor layer 77, An additional mask masking process is required.

Since the mask process is performed including a coating process of a photoresist, an exposure process using an exposure mask, a development process of an exposed photoresist, an etching process, and a strip process, the process is complicated and many chemical solutions are used. The longer the manufacturing time is, the higher the productivity per unit time, the higher the occurrence frequency of defects, and the higher the manufacturing cost.

Therefore, in the case of the conventional array substrate 71 having the oxide semiconductor layer 77 and the etch stopper 79 shown in FIG. 2, it is required to reduce the masking process and reduce the manufacturing cost.

The source and drain electrodes 81 and 83 are etched to prevent the oxide semiconductor layer 77 located outside the etch stopper 79 from being exposed to the etchant for patterning the source and drain electrodes 81 and 83 The overlapping area between the source and drain electrodes 81 and 83 and the gate electrode 73 increases and the parasitic capacitance Cgs increases to adversely affect the characteristics of the thin film transistor Tr It is the present situation.

The conventional array substrate 71 provided with the oxide semiconductor layer 77 and the etch stopper 79 can be manufactured by using the etch stopper 79 process margin and the etch stopper 79, And the drain misalignment margin in patterning between the drain electrodes 81 and 83, the channel length of the thin film transistor Tr is increasing. As a result, the size of the thin film transistor Tr increases and the aperture ratio decreases.

As the size of the thin film transistor formed in the gate pad portion also increases with the increase of the size of the thin film transistor Tr, the width of the bezel which is a non-display region increases, so that it is difficult to realize the narrow bezel.

The present invention relates to a thin film transistor formed using an oxide semiconductor material to prevent an increase in mask process due to an etch stopper formed for preventing damage to an oxide semiconductor layer.

It is also intended to prevent the problem of deterioration of the characteristics of the thin film transistor and lowering of the aperture ratio due to an increase in channel length and an increase in parasitic capacitance caused by the etch stopper.

In order to solve the above problems, the present invention provides a semiconductor device comprising: a gate wiring; A gate electrode connected to the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; A source electrode and a drain electrode located on the gate insulating film and spaced apart from each other corresponding to the gate electrode; A pixel electrode located on the gate insulating film and extending from the drain electrode; A data line disposed on the gate insulating film, the data line comprising a lower layer extending from the source electrode and an upper layer of a low-resistance metal material intersecting the gate wiring; And an oxide semiconductor layer disposed on the source electrode and the drain electrode in correspondence with the gate electrode, wherein each of the source electrode, the drain electrode, and the lower layer of the pixel electrode and the data line includes indium-tin-oxide Or indium-zinc-oxide. The present invention also provides an array substrate for a liquid crystal display device.

In another aspect, the present invention provides a semiconductor device comprising: a gate wiring; A gate electrode connected to the gate wiring; A gate insulating film covering the gate wiring and the gate electrode; A source electrode and a drain electrode located on the gate insulating film and spaced apart from each other corresponding to the gate electrode; A pixel electrode located on the gate insulating film and extending from the drain electrode; An oxide semiconductor layer located on the source electrode and the drain electrode corresponding to the gate electrode; A first passivation layer covering the oxide semiconductor layer and having a source contact hole exposing the source electrode; And a data line which is located on the first passivation layer and is connected to the source electrode through the source contact hole and crosses the gate line, the source electrode, the drain electrode, and the pixel electrode are formed of indium tin -Oxide or indium-zinc-oxide. The present invention also provides an array substrate for a liquid crystal display.

The oxide semiconductor layer may include at least one of indium-gallium-zinc-oxide (IGZO), zinc-tin-oxide (ZTO), or zinc- , And ZIO).

And a protective layer covering the oxide semiconductor layer.

And a common electrode located on the protective layer.

And a second protective layer covering the data line and the first protective layer.

And a common electrode located on the second protective layer.

Each of the pixel electrode and the common electrode has a plate shape, and any one of the pixel electrode and the common electrode has an opening.

The pixel electrodes and the common electrodes are bar-shaped and are alternately arranged.

In another aspect, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate wiring and a gate electrode connected to the gate wiring; Forming a gate insulating film covering the gate wiring and the gate electrode; Forming a lower data wiring layer extending from the source electrode and the drain electrode, the pixel electrode extending from the drain electrode, and the source electrode, the source electrode and the drain electrode being spaced apart from each other in correspondence to the gate electrode; Forming an upper data wiring layer made of a low-resistance metal material on the lower data wiring layer; And forming an oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode, wherein each of the source electrode, the drain electrode, the pixel electrode, and the lower data wiring layer includes an indium-tin- Oxide or indium-zinc-oxide. The present invention also provides a method of manufacturing an array substrate for a liquid crystal display device.

In another aspect, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a gate wiring and a gate electrode connected to the gate wiring; Forming a gate insulating film covering the gate wiring and the gate electrode; Forming a source electrode and a drain electrode corresponding to the gate electrode and spaced apart from each other on the gate insulating film and a pixel electrode extending from the drain electrode; Forming an oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode; Forming a first passivation layer covering the oxide semiconductor layer and having a source contact hole exposing the source electrode; And forming a data line on the first passivation layer, the data line being connected to the source electrode through the source contact hole and intersecting the gate line, wherein the source electrode, the drain electrode, The present invention provides a method for manufacturing an array substrate for a liquid crystal display, the method comprising the steps of:

Forming a lower data wiring layer extending from the source electrode and the drain electrode corresponding to the gate electrode, pixel electrodes extending from the drain electrode and the source electrode, on the gate insulating film; The step of forming the upper data wiring layer made of the low resistance metal material is characterized by being performed by a halftone mask process.

The halftone mask process may include: depositing a layer of a transparent conductive material on the gate insulating layer; Depositing a metal material layer on the transparent conductive material layer; A first photoresist layer having a first thickness corresponding to the source electrode, the drain electrode, and the pixel electrode on the metal material layer; and a second photoresist layer having a second thickness corresponding to the data line, Forming a photoresist layer and exposing the metal material layer in a region corresponding to the semiconductor layer; Etching the exposed metal material layer and the underlying transparent conductive material layer using the first and second photoresist patterns as an etching mask; Forming a third photoresist pattern smaller than the second thickness from the second photoresist pattern by performing an ashing process to remove the first photoresist pattern and forming a third photoresist pattern of the source electrode and the drain electrode, Exposing a layer of metal material; Removing the exposed metal material layer using the third photoresist pattern as an etching mask; And removing the third photoresist pattern.

Wherein the step of laminating the metal material layer on the transparent conductive material layer is performed at room temperature or at a temperature of 200 DEG C or less.

And a step of heat-treating the source electrode and the drain electrode before forming the oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode.

The heat treatment process is performed at a temperature of 200 to 500 ° C.

And forming a protective layer on the oxide semiconductor layer.

And forming a common electrode on the protective layer.

And forming a second passivation layer on the data line and the first passivation layer.

And forming a common electrode on the second passivation layer.

Since the present invention does not require an etch stopper while using the oxide semiconductor layer, it is possible to prevent an increase in the mask process. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.

Further, by preventing the increase of the channel length and the increase of the parasitic capacitance occurring in the structure including the conventional etch stopper, it is possible to suppress the vertical crosstalk and the residual image due to the characteristic deterioration of the thin film transistor and the parasitic capacitance, And it is possible to prevent a decrease in the aperture ratio.

Further, since the oxide semiconductor layer is made of a transparent conductive metal material rather than a low-resistance metal material while the data line is formed of a low-resistance metal material, the contact resistance increase due to the contact between the oxide semiconductor layer and the low- .

In addition, it is possible to prevent the problem of disconnection of the oxide semiconductor layer, which may occur when the oxide semiconductor layer is formed on the source electrode and the drain electrode to prevent damage to the oxide semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a conventional array substrate constituting a liquid crystal display device, in which one pixel region is cut including a thin film transistor; Fig.
2 is a cross-sectional view of a pixel region of an array substrate including a conventional thin film transistor having an oxide semiconductor layer.
3 is a cross-sectional view of a part of an array substrate for a liquid crystal display according to the first embodiment of the present invention.
4 is a plan view of a part of an array substrate for a liquid crystal display according to a second embodiment of the present invention.
5 is a sectional view taken along line VV in Fig.
6A to 6G are cross-sectional views showing a manufacturing process of the array substrate for a liquid crystal display shown in FIG. 5;
7 is a plan view of a part of an array substrate for a liquid crystal display according to a third embodiment of the present invention.
8 is a cross-sectional view taken along line VIII-VIII in Fig. 7;
9A to 9G are cross-sectional views showing a manufacturing process of the array substrate for a liquid crystal display shown in FIG. 8;

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

3 is a cross-sectional view of a part of an array substrate for a liquid crystal display according to the first embodiment of the present invention.

As shown, the array substrate for a liquid crystal display according to the first embodiment of the present invention includes a substrate 101, gate wirings (not shown) formed on the substrate 101, data wirings 120, A thin film transistor Tr, a common electrode 150, and a pixel electrode 170. [

The gate line and the data line 120 intersect with each other to define a pixel region P and the thin film transistor Tr is connected to the gate line and the data line 120, And is located in the switching region TrA.

The thin film transistor Tr includes a gate electrode 114 on the substrate 101, a gate insulating film 116 covering the gate electrode 114, a source electrode 124 spaced apart from the gate insulating film 116 on the gate insulating film 116, And a drain electrode 126 and an oxide semiconductor layer 130 overlapping the gate electrode 114 on the source and drain electrodes 124 and 126. At this time, the gate electrode 114 is connected to the gate line, and the source electrode 124 is connected to the data line 120.

A first passivation layer 140 is formed to cover the thin film transistor Tr and a common electrode 150 is formed on the first passivation layer 140. A second passivation layer 160 is formed to cover the common electrode 150 and a pixel electrode 170 is formed on the second passivation layer 160.

A drain contact hole exposing the drain electrode 126 of the thin film transistor Tr is formed in the first and second passivation layers 140 and 160. The pixel electrode 170 is electrically connected to the drain contact hole And is connected to the drain electrode 126. In addition, the pixel electrode 170 has an opening 172 and forms a fringe field together with the common electrode 160.

In the array substrate having such a structure, since the oxide semiconductor material is used, the characteristics of the thin film transistor Tr are improved and the oxide semiconductor layer 130 is formed after the pattern of the source electrode 124 and the drain electrode 126. Therefore, It is possible to prevent the oxide semiconductor layer 130 from being damaged. Therefore, it is possible to prevent an increase in the number of mask processes by the etch stopper, an increase in channel length, and an increase in parasitic capacitance.

The source electrode 124 extending from the data line 120 and the drain electrode 126 spaced apart from the data line 120 are made of a low resistance metal material such as aluminum or molybdenum and the oxide semiconductor layer 130 is made of such low resistance metal The contact resistance with the material is very high, so that the thin film transistor Tr having good characteristics can not be obtained.

The source electrode 124 and the drain electrode 126 are formed to a thickness of several thousand angstroms and when the oxide semiconductor layer 130 having a thickness of several hundred angstroms is formed on the source electrode 124 and the drain electrode 126, The problem of disconnection of the oxide semiconductor layer 130 occurs.

Hereinafter, an array substrate for a liquid crystal display device capable of preventing the above problems will be described.

Fig. 4 is a plan view of a part of an array substrate for a liquid crystal display according to a second embodiment of the present invention, and Fig. 5 is a sectional view taken along the line V-V in Fig.

4 and 5, an array substrate for a liquid crystal display according to a second embodiment of the present invention includes a substrate 201, a gate wiring 212 formed on the substrate 201, A wiring 220, a thin film transistor Tr, a pixel electrode 230, and a common electrode 270.

The gate line 212 and the data line 220 intersect with each other to define a pixel region P. That is, the gate line 212 extends in a first direction, and the data line 220 extends in a second direction different from the first direction. The thin film transistor Tr is connected to the gate line 212 and the data line 220 and is located in the switching region TrA in the pixel region P. [

The thin film transistor Tr includes a gate electrode 214 on the substrate 201, a gate insulating film 216 covering the gate electrode 214, a source electrode 224 spaced from the gate insulating film 216 on the gate insulating film 216, And a drain electrode 226 and an oxide semiconductor layer 240 overlapping the gate electrode 214 on the source and drain electrodes 224 and 226. The source electrode 224 and the drain electrode 226 may be formed of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) And the oxide semiconductor layer 240 may be formed of indium-gallium-zinc-oxide (IGZO), zinc-tin-oxide (ZTO) Oxide semiconductor material such as zinc-indium-oxide (ZIO). The gate electrode 214 is connected to the gate line 212 and the source electrode 224 is connected to the data line 220.

In the pixel region P, a plate-shaped pixel electrode 230 connected to the drain electrode 226 is formed. The pixel electrode 230 is formed of the same material as the drain electrode 226 and is located on the same layer. That is, the pixel electrode 230 is made of a transparent conductive material such as ITO or IZO and extends from the drain electrode 226.

A first passivation layer 250 is formed to cover the thin film transistor Tr and the pixel electrode 230. At this time, the thin film transistor Tr includes a source contact hole 252 exposing a part of the source electrode 224. The first passivation layer 250 covers the pixel electrode 230 but may alternatively cover only the thin film transistor Tr to expose the pixel electrode 230.

The data line 220 is formed on the first passivation layer 250 in contact with the source electrode 224 through the source contact hole 252. The data line 220 may be formed of a low resistance material such as copper (Cu), a copper alloy (AlNd), aluminum (Al), an aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti), or molybdenum- Metal material.

5, the source electrode 224 is formed only in the switching region Tr, and the data wiring 220 has a single-layer structure. Alternatively, the source electrode 224 may extend below the data line 220 to form the data line 220 of the dual layer.

A second protective layer 260 is formed to cover the data line 220 and a common electrode 270 is formed on the second protective layer 260. The common electrode 270 has an opening 272 corresponding to the pixel electrode 230 to form a fringe field with the pixel electrode 230. 5, the common electrode 270 is removed corresponding to the thin film transistor Tr in order to minimize the influence of the common electrode 270 on the thin film transistor Tr. However, It is possible.

4 and 5, the pixel electrode 230 has a plate shape and the common electrode 270 has an opening. In contrast, the pixel electrode 230 has an opening and the common electrode 270 has an opening It is possible to cover the whole pixel range station P. In addition, a lateral electric field structure in which the pixel electrode 230 and the common electrode 270 have a bar shape and is alternately arranged may be formed. 4 and 5 show a structure in which the pixel electrode 230 and the common electrode 270 are all formed on one substrate 201 to form a transverse electric field or a fringe field, 270 may be formed on a separate substrate to form a vertical electric field.

In the above-described array substrate for a liquid crystal display, the characteristics of the thin film transistor Tr can be improved by using the oxide semiconductor layer 240, and since the ohmic contact layer is not required, The problem of non-uniformity of the thickness of the semiconductor layer can be prevented.

Since the data line 220 is patterned in a state in which the oxide semiconductor layer 240 is formed after patterning the source and drain electrodes 224 and 226 and covered with the first protective layer 250, It is possible to prevent the oxide semiconductor layer 240 from being removed or damaged by the etchant for patterning the data line 220 without using the oxide semiconductor layer 240.

In addition, it is possible to prevent the problem of the decrease of the aperture ratio and the characteristic deterioration of the thin film transistor Tr due to the increase of the channel length and the parasitic capacitance by the etch stopper. The size of the thin film transistor is reduced due to the reduction of the channel length, thereby realizing the narrow bezel.

Since the source electrode 224 and the drain electrode 226 which are in contact with the oxide semiconductor layer 240 are made of a material such as ITO or IZO having characteristics similar to those of the oxide semiconductor material, an increase in contact resistance can be prevented .

Since the source electrode 224 and the drain electrode 226 made of ITO or IZO have a thickness of several hundred angstroms, disconnection of the oxide semiconductor layer 240 does not occur at the stepped portion. 3, since the oxide semiconductor layer 240 is formed on the source electrode 124 and the drain electrode 126 made of a low-resistance metal material having a thickness of several thousand angstroms, Although disconnection of the layer 240 may occur, this problem can be solved by forming the source and drain electrodes 224 and 226 with ITO and IZO having a thickness of several hundred angstroms in the array substrate of the second embodiment.

Hereinafter, referring to Figs. 6A to 6G, which are cross-sectional views showing a manufacturing process of the array substrate for a liquid crystal display shown in Fig. 5,

Will be described. A switching region TrA in which the thin film transistor Tr is located in the pixel region P and the pixel region P is defined on the substrate 201 for convenience of explanation.

(Al), aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti), or molybdenum-titanium alloy (FIG. 4) 212 and the gate electrode 214 are formed by depositing a low-resistance metal material such as MoTi to form a first metal material layer (not shown), and performing a masking process and patterning. Extends along the boundary of the pixel region P of the gate wiring 212 and the gate electrode 214 extends from the gate wiring 212 and is located in the switching region TrA.

Next, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the gate wiring 212 and the gate electrode 214 to form a gate insulating film 216.

Next, as shown in FIG. 6B, a transparent conductive material such as ITO or IZO is deposited to deposit a first layer of a transparent conductive material (not shown) on the gate insulating layer 216, and then patterned by a mask process And a source electrode 224 and a drain electrode 226 are formed. The source electrode 224 and the drain electrode 226 are located in the switching region TrA and are spaced apart from each other. At the same time, a plate-shaped pixel electrode 230 extending to the drain electrode 226 is formed. On the other hand, in the case of an array substrate for a transverse electric field type liquid crystal display, the pixel electrodes 230 are formed to have a plurality of bar shapes spaced apart from each other. Also, the source electrode 224 may extend beyond the switching region TrA and extend below the data line (220 in FIG. 4).

Next, as shown in FIG. 6C, an indium-gallium-zinc-oxide (IGZO), a zinc-tin-oxide (ZTO) or a zinc- corresponding to the gate electrode 214 is formed in the switching region TrA by depositing an oxide semiconductor material such as zinc-indium-oxide (ZIO) to form an oxide semiconductor material layer (not shown) An oxide semiconductor layer 240 is formed.

The gate electrode 214, the gate insulating film 216, the source electrode 324, the drain electrode 326 and the oxide semiconductor layer 340 constitute a thin film transistor Tr.

At this time, since the source electrode 224, the drain electrode 226 and the pixel electrode 230 made of a transparent conductive material such as ITO or IZO have a thickness of several hundred angstroms, the oxide semiconductor layer 240 ) Does not occur. That is, when the oxide semiconductor layer 240 having a thickness of several hundred angstroms, for example, 500 angstroms, is formed on a conventional source electrode of several thousand angstroms in thickness, disconnection occurs. In the present invention, the source electrode 224 and the drain electrode 226 ) Has a thickness of several hundreds of angstroms, such a problem does not occur.

In addition, since the etch stopper is not formed, an increase in the channel length due to the etch stopper can be prevented. An increase in the parasitic capacitance caused by an increase in the area of the source electrode and the drain electrode in order to cover the etch stopper is also provided.

The etching of the oxide semiconductor material layer uses oxalic acid. At this time, since the oxide semiconductor material layer is deposited on the source electrode 224, the drain electrode 226 and the pixel electrode 230 made of a transparent conductive material such as ITO or IZO, The source electrode 224, the drain electrode 226 and the pixel electrode 230 may also be etched and removed by oxalic acid.

In order to prevent such a problem, a heat treatment process for crystallizing the source electrode 224, the drain electrode 226 and the pixel electrode 230 is performed before the etching process using oxalic acid. When a transparent conductive material such as ITO or IZO is crystallized, it has a selectivity to oxalic acid, and damage to the oxide semiconductor material layer in the etching process can be prevented. After the source electrode 224, the drain electrode 226 and the pixel electrode 230 are formed, the heat treatment process may be performed before the oxide semiconductor material layer is deposited, or before the oxide semiconductor material layer is deposited and then patterned Can proceed. For example, the heat treatment may be performed at about 200 to 500 ° C.

Next, as shown in FIG. 6D, an inorganic insulating material such as silicon oxide or silicon nitride is deposited to form the first passivation layer 250, and the masking process is performed to pattern the first passivation layer 250 A source contact hole 252 exposing the source electrode 252 is formed. That is, the first passivation layer 250 has a source contact hole 252 covering the oxide semiconductor layer 240 and exposing the source electrode 224. The first passivation layer 250 covers the pixel electrode 230 but patterns the first passivation layer 250 to expose the pixel electrode 230 in the process of forming the source contact hole 252 It is possible.

Next, as shown in FIG. 6E, a layer of copper (Cu), a copper alloy (AlNd), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti) or molybdenum- A second metal material layer (not shown) is formed on the first passivation layer 250 by depositing the same low resistance metal material, and patterned by a mask process to form the data interconnection 220. The data line 220 is connected to the source electrode 224 through the source contact hole 252 and intersects with the gate line 212 to define the pixel region P. [

At this time, since the oxide semiconductor layer 240 is covered with the first passivation layer 250, the oxide semiconductor layer 240 is not exposed to the etching solution for patterning the second metal material layer. That is, the oxide semiconductor layer 240 can be prevented from being damaged by the wet etching process even if a separate etch stopper is not formed.

In the case of the TN mode using a vertical electric field, an array substrate is obtained in the process of forming the data lines 220. [

Next, as shown in FIG. 6F, a second passivation layer 260 is formed on the substrate 201 on which the data lines 220 are formed. The second passivation layer 260 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride, or an organic insulating material such as photo-acrylic or benzocyclobutene.

Next, as shown in FIG. 6G, a second transparent conductive material layer (not shown) such as ITO or IZO is deposited on the second passivation layer 260 and patterned by a mask process to form the pixel electrode 230 , A common electrode 270 having an opening 272 is formed to obtain an array substrate for a fringe field mode liquid crystal display device. On the other hand, in the case of the array substrate for a transverse electric field type liquid crystal display device, the pixel electrode 230 and the common electrode 270 have a bar shape and are alternately positioned.

As described above, in the case of the array substrate for a liquid crystal display according to the second embodiment of the present invention, the characteristics of the thin film transistor are improved by using the oxide semiconductor layer, and the oxide semiconductor layer is used in the etching process of the metal layer It is possible to prevent damage from being caused. Therefore, it is advantageous in that the aperture ratio is increased and the characteristics of the thin film transistor are improved by preventing the problem of the channel length increase and the parasitic capacitance increase by the etch stopper.

Hereinafter, an array substrate for a liquid crystal display device capable of reducing the mask process while having the above-described advantages will be described.

FIG. 7 is a plan view of a part of an array substrate for a liquid crystal display according to a third embodiment of the present invention, and FIG. 8 is a sectional view taken along a line VIII-VIII in FIG.

7 and 8, the array substrate for a liquid crystal display according to the second embodiment of the present invention includes a substrate 301, a gate wiring 312 formed on the substrate 301, A wiring 320, a thin film transistor Tr, a pixel electrode 330, and a common electrode 370. [

The gate line 312 and the data line 320 intersect with each other to define a pixel region P and the thin film transistor Tr is connected to the gate line 312 and the data line 320, And is located in the switching region TrA in the pixel region P. [

The thin film transistor Tr includes a gate electrode 314 on the substrate 301, a gate insulating film 316 covering the gate electrode 314, a source electrode 324 spaced from the gate insulating film 316 on the gate insulating film 316, A drain electrode 326 and an oxide semiconductor layer 340 overlapping the gate electrode 314 on the source and drain electrodes 324 and 326. The source electrode 324 and the drain electrode 326 may be formed of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) And the oxide semiconductor layer 340 is made of indium-gallium-zinc-oxide (IGZO), zinc-tin-oxide (ZTO) Oxide semiconductor material such as zinc-indium-oxide (ZIO). The gate electrode 314 is connected to the gate line 312 and the source electrode 324 is connected to the data line 320.

The data line 320 has a double layer structure of a lower layer 320a extending from the source electrode 324 and an upper layer 320b formed of a low-resistance metal material. That is, the source electrode 324 and the drain electrode 326 are formed of a single layer of a transparent conductive material such as ITO or IZO, while the data line 320 is formed of a lower layer 320a of a transparent conductive material such as ITO or IZO And an upper layer 320b of a low-resistance metal material.

In the pixel region P, a plate-shaped pixel electrode 330 connected to the drain electrode 326 is formed. The pixel electrode 330 is formed of the same material as the drain electrode 326 and is located on the same layer. That is, the pixel electrode 330 is made of a transparent conductive material such as ITO or IZO and extends from the drain electrode 326.

A passivation layer 250 is formed to cover the thin film transistor Tr and the pixel electrode 330 and a common electrode 270 is formed on the passivation layer 270. The common electrode 370 has an opening 372 corresponding to the pixel electrode 330 to form a fringe field with the pixel electrode 330.

7 and 8 show a configuration in which the pixel electrode 330 has a plate shape and the common electrode 370 has an opening. Alternatively, the pixel electrode 330 has an opening, and the common electrode 370 is connected to the pixel region (P). In addition, a lateral electric field structure in which the pixel electrode 330 and the common electrode 370 are bar-shaped and alternately arranged may be formed. 7 and 8 show a structure in which the pixel electrode 330 and the common electrode 370 are all formed on one substrate 301 to form a transverse electric field or a fringe field, 370 may be formed on a separate substrate to form a vertical electric field.

In the above-described array substrate for a liquid crystal display device, the characteristics of the thin film transistor Tr can be improved by using the oxide semiconductor layer 340, and since the ohmic contact layer is not required, The problem of non-uniformity of the thickness of the semiconductor layer can be prevented.

In addition, since the oxide semiconductor layer 340 is formed after patterning the source and drain electrodes 324 and 326 and the data line 320, the oxide semiconductor layer 240 is removed or damaged by the etchant without using an etch stopper The problem can be prevented.

In addition, it is possible to prevent the problem of the decrease of the aperture ratio and the characteristic deterioration of the thin film transistor Tr due to the increase of the channel length and the parasitic capacitance by the etch stopper.

Since the source electrode 324 and the drain electrode 326 which are in contact with the oxide semiconductor layer 340 are made of a material such as ITO or IZO having characteristics similar to those of the oxide semiconductor material, it is possible to prevent an increase in contact resistance .

Since the source electrode 324 and the drain electrode 326 made of ITO or IZO have a thickness of several hundred angstroms, disconnection of the oxide semiconductor layer 340 does not occur at the stepped portion.

Hereinafter, a manufacturing process of the array substrate will be described with reference to FIGS. 9A to 9G, which are cross-sectional views showing the manufacturing steps of the array substrate for a liquid crystal display shown in FIG. The switching region TrA in which the thin film transistor Tr is located in the pixel region P and the pixel region P is defined on the substrate 301 for convenience of explanation.

(Al), an aluminum alloy (AlNd), molybdenum (Mo), titanium (Ti), or a molybdenum-titanium alloy (FIG. 7) 312 and the gate electrode 314 are formed by depositing a low resistance metal material such as MoTi to form a first metal material layer (not shown), and performing a masking process and patterning. Extends along the boundary of the pixel region P of the gate wiring 312 and the gate electrode 314 extends from the gate wiring 312 and is located in the switching region TrA.

Next, an inorganic insulating material such as silicon oxide or silicon nitride is deposited on the gate wiring 312 and the gate electrode 314 to form a gate insulating film 316. [

Next, as shown in FIG. 9B, a first transparent conductive material layer 317 and a second metal material layer 318 are stacked on the gate insulating layer 216. The first transparent conductive material layer 317 may be made of ITO or IZO and the second metal material layer 318 may be formed of copper (Cu), copper alloy (AlNd), aluminum (Al), aluminum alloy (AlNd) Resistant metal material such as molybdenum (Mo), titanium (Ti) or molybdenum-titanium alloy (MoTi).

At this time, the second metal material layer 318 is deposited at a temperature of about 200-500 ° C., so that the first transparent conductive material layer 317 at the bottom can be crystallized. However, if the first transparent conductive material layer 317 is crystallized before the patterning process, the etching process of the first transparent conductive material layer 317 may be difficult. That is, the selection of the etchant may be difficult or the etching rate may be slowed, which may reduce the process efficiency. In order to prevent such a problem, it is preferable that the second metal material layer 318 is deposited at a room temperature or a temperature condition of 200 ° C or lower, and then a heat treatment process is performed. The first transparent conductive material layer 317 has a thickness of several hundred angstroms, for example, 400-600 angstroms, and the second metal material layer 318 has a thickness of several thousand angstroms.

Next, a photoresist is applied on the second metal material layer 318 to form a photoresist layer (not shown), and an exposed portion having a transmissive portion TA, a blocking portion BA, and a transflective portion HTA The mask M is placed. The transmissive portion TA corresponds to a space between the source electrode 324 of FIG. 8 and the drain electrode 326 of FIG. 8 and the transflective portion HTA includes a source electrode 324 and a drain electrode 326, (330 in Fig. 8).

Thereafter, the photoresist layer is exposed and developed using the exposure mask M to completely remove the photoresist layer corresponding to the transmissive portion TA to expose the second metal material layer 318, A first photoresist pattern 191 having a first thickness corresponding to the transflective portion HTA and a second photoresist pattern 192 having a second thickness greater than the first thickness corresponding to the blocking portion BA, .

Next, as shown in FIG. 9C, the exposed second metal material layer 318 and the second metal material layer 313 are etched using the first photoresist pattern (191 in FIG. 9B) and the second photoresist pattern (FIG. And the first transparent conductive material layer 317 (317 in FIG. 9B) is etched. A source electrode 324 and a drain electrode 326 are formed in the switching region TrA and a pixel electrode 330 is formed in the pixel region P on the gate insulating layer 316. [ The pixel electrode 330 extends from the drain electrode 326.

Next, an ashing process is performed to remove the first photoresist pattern (191 in FIG. 9B), thereby forming the source electrode 324, the drain electrode 326, and the second metal material layer (318) is exposed. At this time, the thickness of the second photoresist pattern 192 (FIG. 9B) decreases to form the photoresist pattern 193 having the third thickness.

Next, by etching the exposed second metal material layer 318 (FIG. 9C) using the third photoresist pattern 193 as an etching mask, the source electrode 324, the drain electrode 326, (Not shown). At this time, a second metal material layer (317 in FIG. 9C) is left under the third photoresist pattern (193 in FIG. 9C), and the data wiring 320 having the double layer structure of the lower layer 320a and the upper layer 320b Respectively.

Next, the third photoresist pattern (193 in FIG. 9C) is removed by an ashing or stripping process.

9B to 9D, a halftone mask process for patterning the first transparent conductive material layer 317 and the second metal material layer 318 by a single mask process is shown. The first transparent conductive material layer 317 is patterned by one mask process to form the source electrode 324 and the lower layer 320a of the drain electrode 326 and the pixel electrode 330 and the data line 320, The second metal material layer 318 may be stacked and patterned by another mask process to form the upper layer 320b of the data wiring 320. [

Next, as shown in FIG. 9E, an indium-gallium-zinc-oxide (IGZO), a zinc-tin-oxide (ZTO) or a zinc- corresponding to the gate electrode 314 in the switching region TrA by depositing an oxide semiconductor material such as zinc-indium-oxide (ZIO) to form an oxide semiconductor material layer (not shown) An oxide semiconductor layer 340 is formed. One end of the oxide semiconductor layer 340 is in contact with the source electrode 324 and the other end is in contact with the drain electrode 326.

The gate electrode 214, the gate insulating film 216, the source electrode 324, the drain electrode 326 and the oxide semiconductor layer 340 constitute a thin film transistor Tr.

As described above, since the source electrode 324, the drain electrode 326, and the pixel electrode 330, which are made of a transparent conductive material such as ITO or IZO, have a thickness of several hundreds of angstroms, The disconnection of the layer 340 does not occur.

In addition, since the etch stopper is not formed, an increase in the channel length due to the etch stopper can be prevented. An increase in the parasitic capacitance caused by an increase in the area of the source electrode and the drain electrode in order to cover the etch stopper is also provided.

The etching of the oxide semiconductor material layer uses oxalic acid. At this time, the oxide semiconductor material layer may include a source electrode 324, a drain electrode 326, and a pixel electrode 330 formed of a transparent conductive material such as ITO or IZO and an upper layer (not shown) of the data line 320 made of a low- The source electrode 324, the drain electrode 326, the pixel electrode 330 and the upper layer 320b of the data line 320 may be damaged in the etchant for etching the oxide semiconductor material layer have. In particular, the source electrode 324, the drain electrode 326, and the pixel electrode 330 are formed of ITO or IZO having properties similar to those of an oxide semiconductor material, and thus have no etching selectivity.

Accordingly, in the present invention, a heat treatment process for crystallizing the source electrode 224, the drain electrode 226, and the pixel electrode 230 is performed before the oxide semiconductor material layer is etched, and the oxide semiconductor material layer is etched using oxalic acid do. When a transparent conductive material such as ITO or IZO is crystallized, it has a selection ratio with respect to oxalic acid, and oxalic acid has a selection ratio with respect to a low-resistance metal material constituting the upper layer 320b of the data wiring 320. Thus, damage to the oxide semiconductor material layer in the etching process can be prevented. After the source electrode 224, the drain electrode 226, the pixel electrode 230, and the data line 320 are formed, the heat treatment process may be performed before the oxide semiconductor material layer is deposited, And may be carried out after deposition and before patterning. For example, the heat treatment may be performed at about 200 to 500 ° C.

Next, as shown in FIG. 9F, a protective layer 350 is formed on the substrate 301 on which the oxide semiconductor layer 340 is formed. The passivation layer 350 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride.

In the case of a TN mode using a vertical electric field, an array substrate is obtained by a process of forming the protective layer 350. An array substrate for a TN mode liquid crystal display device can be obtained without the protective layer 350 for protecting the oxide semiconductor layer 340. [

Next, as shown in FIG. 9G, a second transparent conductive material layer (not shown) such as ITO or IZO is deposited on the passivation layer 350 and patterned by a mask process so as to expose the pixel electrode 330 A common electrode 370 having an opening 372 is formed correspondingly to obtain an array substrate for a fringe field mode liquid crystal display. On the other hand, in the case of the array substrate for a transverse electric field type liquid crystal display device, the pixel electrode 330 and the common electrode 370 have a bar shape and are alternately arranged.

As described above, in the case of the array substrate for a liquid crystal display according to the third embodiment of the present invention, the characteristics of the thin film transistor are improved by using the oxide semiconductor layer and the oxide semiconductor layer is used for the etching process of the metal layer It is possible to prevent damage from being caused. Therefore, it is advantageous in that the aperture ratio is increased and the characteristics of the thin film transistor are improved by preventing the problem of the channel length increase and the parasitic capacitance increase by the etch stopper.

Further, since the step of forming the etch stopper is not required, the array substrate for the fringe field mode liquid crystal display can be manufactured by the 5-mask process.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

201, 301: substrate 212, 312: gate wiring
214, 314: gate electrode 220, 320: data wiring
224, 324: source electrode 226, 326: drain electrode
230, 330: pixel electrode 240, 340: oxide semiconductor layer
270, 370: common electrode

Claims (20)

A gate wiring;
A gate electrode connected to the gate wiring;
A gate insulating film covering the gate wiring and the gate electrode;
A source electrode and a drain electrode located on the gate insulating film and spaced apart from each other corresponding to the gate electrode;
A pixel electrode located on the gate insulating film and extending from the drain electrode;
A data line disposed on the gate insulating film, the data line comprising a lower layer extending from the source electrode and an upper layer of a low-resistance metal material intersecting the gate wiring;
And an oxide semiconductor layer disposed on the source electrode and the drain electrode in correspondence with the gate electrode,
Wherein each of the source electrode, the drain electrode, the pixel electrode, and the lower layer of the data line is made of indium-tin-oxide or indium-zinc-oxide.
A gate wiring;
A gate electrode connected to the gate wiring;
A gate insulating film covering the gate wiring and the gate electrode;
A source electrode and a drain electrode located on the gate insulating film and spaced apart from each other corresponding to the gate electrode;
A pixel electrode located on the gate insulating film and extending from the drain electrode;
An oxide semiconductor layer located on the source electrode and the drain electrode corresponding to the gate electrode;
A first passivation layer covering the oxide semiconductor layer and having a source contact hole exposing the source electrode;
And a data line that is located on the first passivation layer and is connected to the source electrode through the source contact hole and crosses the gate line,
Wherein the source electrode, the drain electrode, and the pixel electrode are made of indium-tin-oxide or indium-zinc-oxide.
3. The method according to claim 1 or 2,
The oxide semiconductor layer may include at least one of indium-gallium-zinc-oxide (IGZO), zinc-tin-oxide (ZTO), or zinc- , ZIO) formed on the substrate (10).
The method according to claim 1,
And a protective layer covering the oxide semiconductor layer.
5. The method of claim 4,
And a common electrode located on the protective layer.
3. The method of claim 2,
And a second protective layer covering the data line and the first protective layer.
The method according to claim 6,
And a common electrode located on the second passivation layer.
The method according to claim 5 or 7,
Wherein each of the pixel electrode and the common electrode has a plate shape, and any one of the pixel electrode and the common electrode has an opening.
The method according to claim 5 or 7,
Wherein each of the pixel electrode and the common electrode has a bar shape and is alternately arranged.
Forming a gate wiring and a gate electrode connected to the gate wiring;
Forming a gate insulating film covering the gate wiring and the gate electrode;
Forming a lower data wiring layer extending from the source electrode and the drain electrode, the pixel electrode extending from the drain electrode, and the source electrode, the source electrode and the drain electrode being spaced apart from each other in correspondence to the gate electrode;
Forming an upper data wiring layer made of a low-resistance metal material on the lower data wiring layer;
And forming an oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode,
Wherein each of the source electrode, the drain electrode, the pixel electrode, and the lower data wiring layer is made of indium-tin-oxide or indium-zinc-oxide.
Forming a gate wiring and a gate electrode connected to the gate wiring;
Forming a gate insulating film covering the gate wiring and the gate electrode;
Forming a source electrode and a drain electrode corresponding to the gate electrode and spaced apart from each other on the gate insulating film and a pixel electrode extending from the drain electrode;
Forming an oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode;
Forming a first passivation layer covering the oxide semiconductor layer and having a source contact hole exposing the source electrode;
Forming a data line on the first passivation layer, the data line being connected to the source electrode through the source contact hole and intersecting the gate line,
Wherein the source electrode, the drain electrode, and the pixel electrode are made of indium-tin-oxide or indium-zinc-oxide.
11. The method of claim 10,
Forming a lower data wiring layer extending from the source electrode and the drain electrode corresponding to the gate electrode, pixel electrodes extending from the drain electrode and the source electrode, on the gate insulating film; Wherein a step of forming an upper data wiring layer made of a low resistance metal material is performed by a halftone mask process.
13. The method of claim 12,
In the halftone mask process,
Depositing a layer of a transparent conductive material on the gate insulating layer;
Depositing a metal material layer on the transparent conductive material layer;
A first photoresist layer having a first thickness corresponding to the source electrode, the drain electrode, and the pixel electrode on the metal material layer; and a second photoresist layer having a second thickness corresponding to the data line, Forming a photoresist layer and exposing the metal material layer in a region corresponding to the semiconductor layer;
Etching the exposed metal material layer and the underlying transparent conductive material layer using the first and second photoresist patterns as an etching mask;
Forming a third photoresist pattern smaller than the second thickness from the second photoresist pattern by performing an ashing process to remove the first photoresist pattern and forming a third photoresist pattern of the source electrode and the drain electrode, Exposing a layer of metal material;
Removing the exposed metal material layer using the third photoresist pattern as an etching mask;
And removing the third photoresist pattern. A method of manufacturing an array substrate for a liquid crystal display device,
14. The method of claim 13,
Wherein the step of laminating the metal material layer on the transparent conductive material layer is performed at room temperature or at a temperature of 200 DEG C or less.
The method according to any one of claims 10, 11, and 14,
Before forming the oxide semiconductor layer corresponding to the gate electrode on the source electrode and the drain electrode,
And a step of heat-treating the source electrode and the drain electrode.
16. The method of claim 15,
Wherein the heat treatment step is performed at a temperature of 200 to 500 占 폚.
11. The method of claim 10,
And forming a protective layer on the oxide semiconductor layer. The method of manufacturing an array substrate for a liquid crystal display according to claim 1,
18. The method of claim 17,
And forming a common electrode on the protective layer. A method of manufacturing an array substrate for a liquid crystal display device,
12. The method of claim 11,
And forming a second protective layer on the data line and the first protective layer. The method of manufacturing an array substrate for a liquid crystal display according to claim 1,
20. The method of claim 19,
And forming a common electrode on the second protective layer. The method of manufacturing an array substrate for a liquid crystal display according to claim 1,

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