KR20130017157A - Array substrate and liquid crystal display device including thereof - Google Patents

Abstract

PURPOSE: An array substrate and a liquid crystal display device including the same are provided to reduce the number of a common line by forming a common line per N gate lines. CONSTITUTION: A gate line(207) is parallel to a common line(270a). A pixel electrode(212) is formed in a pixel region. A common electrode(260) is formed between passivation layers and vertically separated from the pixel electrode. The common electrode includes opening parts. One common line corresponds to N gate lines.

Description

ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate and a liquid crystal display device including the same. More particularly, the present invention relates to an array substrate and a liquid crystal display device including the same to reduce the number of common wirings and improve an aperture ratio.

Recently, as the information society develops, the demand for the display field is increasing in various forms, and in response, various flat panel display devices, for example, liquid crystal, which have features such as thinning, light weight, and low power consumption Liquid crystal display devices, plasma display panel devices, electroluminescent display devices, and the like have been studied.

Among these, the liquid crystal display is one of the most widely used flat panel display devices, and includes two substrates on which pixel electrodes, a common electrode, and the like are formed, and a liquid crystal layer between the two substrates.

Such a liquid crystal display determines an orientation of liquid crystal molecules of a liquid crystal layer according to an electric field generated by a voltage applied to an electrode, and controls polarization of incident light to display an image.

TN (Twisted Nematic) mode in which the liquid crystal molecules are arranged so that the liquid crystal molecules are twisted by 90 degrees according to the arrangement of the liquid crystals and the arrangement of electrodes that apply an electric field to the liquid crystals, and then the voltage is applied to control the liquid crystal molecules. In-Plane Switching (IPS) mode, in which two electrodes are formed in a plane parallel to the alignment layer to change the orientation of the liquid crystal molecules by a horizontal electric field. The initial orientation of the liquid crystal molecules is arranged parallel to the substrate, and the electrodes It is formed in each of the two substrates and is divided into a VA (Vertical Alignment) mode for applying a vertical electric field to the liquid crystal.

Among them, an IPS type liquid crystal display device generally includes a first substrate and a second substrate that are disposed to face each other and have a liquid crystal layer therebetween, and the viewing angle is reduced because the liquid crystal molecules of the liquid crystal layer are driven horizontally by a transverse electric field. great.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown in FIG. 1, the array substrate 10 and the color filter substrate 20 are spaced apart from each other, and the liquid crystal layer 30 is interposed between the array substrate 10 and the color filter substrate 20. have.

The common electrode 60 and the pixel electrode 12 are formed on the same plane on the array substrate 10. In this case, as the voltage is applied to the common electrode 60 and the pixel electrode 12, the common electrode 60 is formed. A horizontal electric field L may be formed between the pixel electrode 12 and the pixel electrode 12.

The orientation of the liquid crystal molecules of the liquid crystal layer 30 is determined by the horizontal electric field L, and an image may be displayed using the same.

However, the transverse electric field type liquid crystal display device having such a configuration has an advantage of improving the viewing angle, but also has disadvantages of low aperture ratio and low transmittance.

Accordingly, in order to improve the disadvantage of the transverse electric field type liquid crystal display, a fringe field switching mode LCD, in which a liquid crystal is operated by a fringe field, has been proposed.

2 is a plan view showing a portion of a conventional fringe field switched mode array substrate.

First, a first metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), or copper alloy having low resistance on the first substrate is deposited and patterned through a mask process to form a gate wiring 107. And the gate electrode 108 is formed.

Then, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating film (not shown) on the entire surface of the substrate.

Further, a pure amorphous silicon layer, an impurity amorphous silicon layer, and a second metal layer made of materials such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), and copper alloy are deposited on the gate insulating layer, and patterned through a mask process. The semiconductor layer 120, the data line 230, the source electrode 133, and the drain electrode 136 are formed.

In this case, the semiconductor layer 120 may be formed of an active layer (not shown) and an ohmic contact layer (not shown), and the gate line 107 and the data line 230 may cross each other to define a pixel area.

Next, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited to form the pixel electrode 112.

In this case, the pixel electrode 112 may be formed to overlap one end of the drain electrode 136 with the gate insulating layer and the semiconductor layer 120 interposed therebetween.

Accordingly, the thin film transistor Tr including the gate electrode 108, the gate insulating layer, the semiconductor layer 120, and the source electrode 133 and the drain electrode 136 spaced apart from each other is formed in each pixel region.

Although not shown, a protective layer (not shown) is formed by coating an inorganic insulating material such as silicon oxide (SiO ₂ ) or an organic insulating material such as benzocyclobutene (BCB) or photo acryl on the entire surface of the substrate.

Then, a second transparent conductive material layer (not shown) is deposited by depositing a transparent conductive material such as indium tin oxide (ITO) on the protective layer, and patterned through a mask process, as shown in FIG. 2D, A common electrode having a plurality of openings (oa) spaced at predetermined intervals in a bar shape is formed in each pixel area.

The pixel drain connection pattern 167 corresponding to the drain contact hole 143 may be formed to connect the pixel electrode 112 and the drain electrode 136.

As described above, a fringe field switching mode liquid crystal display (FFS mode LCD) generally eliminates a separate metal common wiring, and arranges pixel electrodes at a lower portion to improve an aperture ratio, and a common electrode is formed on the entire surface of the substrate above the protective layer. .

However, due to the common electrode resistance, as described above, there is a limit to forming a common electrode having a plurality of openings (oa) spaced at regular intervals in a bar shape on the protective layer as one on the front of the liquid crystal display.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an array substrate and a liquid crystal display device including the array substrate for improving the aperture ratio by reducing the number of common wirings.

An array substrate for achieving the above object includes: a gate wiring and a data wiring crossing each other to define a plurality of pixel regions; A common wiring formed in parallel with the gate wiring; A pixel electrode formed in the pixel region; A common electrode having a plurality of openings and spaced vertically from the pixel electrode with a protective layer interposed therebetween, wherein the common wiring is formed one per gate wiring N (N is a natural number of two or more), and a negative voltage And a first common wiring to be applied and a second common wiring to which a positive voltage is applied.

The common electrode may contact the common wire through a common contact hole exposing the common wire.

The common contact hole may include a first common contact hole formed on the first common wire and a second common contact hole formed on the second common wire.

On the other hand, the common electrode is connected to the neighboring common electrode diagonally through the first connection pattern, the common electrode neighboring in the vertical direction through the second connection pattern, or neighboring in the horizontal direction through the third connection pattern It can be connected to the common electrode.

In order to achieve the above object, a liquid crystal display device includes a first substrate on which a plurality of gate lines and a plurality of data lines are formed crossing each other and a second substrate facing and bonding to the first substrate. The first substrate includes a common wiring formed in parallel with the gate wiring, a pixel electrode formed in the pixel region, and a plurality of openings spaced apart from the pixel electrode with a protective layer interposed therebetween. And a common electrode having one common electrode for each of the gate lines N (N is a natural number of two or more), the first common wiring to which a negative voltage is applied, and the second common wiring to which a positive voltage is applied. It is characterized in that the configuration.

The common electrode may contact the common wire through a common contact hole exposing the common wire.

The common contact hole may include a first common contact hole formed on the first common wire and a second common contact hole formed on the second common wire.

On the other hand, the common electrode is connected to the neighboring common electrode diagonally through the first connection pattern, the common electrode neighboring in the vertical direction through the second connection pattern, or neighboring in the horizontal direction through the third connection pattern It is preferable to be connected to the common electrode.

As described above, in the array substrate and the liquid crystal display including the same according to the present invention, the number of common wirings can be reduced by forming one common wiring per gate wiring N (N is a natural number of two or more).

As a result, the aperture ratio and transmittance of the liquid crystal display device can be improved.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.
2 is a plan view showing a portion of a conventional array substrate.
3 is a plan view showing a portion of an array substrate according to a first embodiment of the present invention.
4 is a schematic cross-sectional view of a portion cut along the cutting line IV-IV 'of FIG.
FIG. 5 is a schematic cross-sectional view of a portion cut along the cutting line VV ′ of FIG. 3.
6 is a view referred to for explaining the application of a common voltage in the liquid crystal display according to the first embodiment of the present invention.
7 is a plan view showing a portion of an array substrate according to a second embodiment of the present invention.
8 is a view referred to for explaining the application of a common voltage in the liquid crystal display according to the second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a plan view showing a portion of an array substrate according to a first embodiment of the present invention, FIG. 4 is a schematic cross-sectional view of a portion cut along the cutting line IV-IV 'of FIG. FIG. 5 is a schematic cross-sectional view of a portion cut along the cutting line VV ′ of FIG. 3. The thin film transistor Tr is illustrated as an example in which a region forming a channel forms a 'U' shape, but is not limited thereto and may be modified in various forms.

3 and 4, a plurality of gate lines 207 extending in a first direction are formed in the array substrate according to the first embodiment of the present invention at regular intervals.

The first common wiring 270a and the second common wiring 270b are formed in the same layer as the gate wiring 207 in parallel with the gate wiring 207.

In this case, a voltage of negative polarity (−) may be applied to the first common wiring 270a, and a voltage of positive polarity may be applied to the second common wiring 270b.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating film 215 on the entire surface of the substrate.

The pixel electrode 212 having a plate shape over the gate insulating layer 215 and the plurality of data lines 230 extending in the second direction and crossing the plurality of gate lines 207 to define a plurality of pixel regions are formed. Form.

In this case, each pixel region includes a gate electrode 208, a gate insulating film 215, a semiconductor layer 220 including an active layer 220a of pure amorphous silicon and an ohmic contact layer 220b of impurity amorphous silicon. The thin film transistor Tr including the source electrode 233 and the drain electrode 236 spaced apart from each other is formed.

The thin film transistor Tr is connected to the gate line 207 and the data line 230.

The protective layer 240 is formed on the entire surface of the substrate including the thin film transistor Tr and the pixel electrode 212.

The protective layer 240 may be made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

In addition, each pixel area may contact the first common line 270a or the second common line 270b through the first common contact hole 272a or the second common contact hole 272b on the passivation layer 240. The common electrode 260 may be formed.

That is, the common electrode 260 is not formed as one on the entire surface of the substrate on the protective layer 240 as in the prior art, but may be formed in a plate shape for each pixel region.

Accordingly, in the high resolution large area liquid crystal display, the common electrode is formed in each pixel region, thereby reducing the influence of the common electrode resistance.

The common electrode 260 is formed to be vertically spaced apart from the pixel electrode 212 with the protective layer 240 interposed therebetween.

In this case, the common electrode 260 includes a plurality of openings symmetrically formed with respect to an imaginary line extending in the direction in which the gate wiring 207 extends.

Meanwhile, the common electrode 260 may be connected to neighboring common electrodes through first to third connection patterns, and common electrodes to be connected have the same polarity through the first common line 270a and the second common line 270b. The common voltage of can be applied.

For example, the common electrode 260 may be connected to the neighboring common electrode in a diagonal direction through the first connection pattern 262 or may be connected to the common electrode neighboring in the vertical direction through the second connection pattern 264. .

In addition, it may be connected to the common electrode neighboring in the horizontal direction through the third connection pattern (not shown).

The connection patterns may be appropriately disposed to connect common electrodes to which a common voltage of the same polarity is applied through the first common line 270a and the second common line 270b.

In a liquid crystal display (not shown) having an array substrate having a common electrode 260 having such a structure, the movement of liquid crystal molecules positioned in different domains in one pixel area may vary.

As a result, the arrangement of the long axes of the liquid crystal molecules may be finally changed, thereby reducing color shift at a specific azimuth angle.

As shown in FIG. 5, the pixel electrode 212 and the common electrode 260 are formed on the array substrate according to the first embodiment of the present invention with a protective layer 240 therebetween.

An auxiliary common electrode (not shown) may be formed below the pixel electrode 212 to shield the transverse electric field generated between the data line 230 and the pixel electrode 212.

The auxiliary common electrode may be formed to correspond to the common electrode 260 in a vertical direction.

In addition, since the common electrode 260 and the auxiliary common electrode are made of a transparent conductive material such as indium tin oxide, the aperture ratio becomes narrow even if the common electrode 260 and the auxiliary common electrode deviate from a region corresponding to the black matrix BM. The problem does not occur.

Thus, as shown, the common electrode 260 may be formed to be out of both ends of the black matrix (BM).

6 is a view referred to for explaining the application of a common voltage in the liquid crystal display according to the first embodiment of the present invention. Hereinafter, a case of driving in the vertical 2-dot Z inversion method will be described as an example.

As shown in FIG. 6, in the array substrate according to the first embodiment of the present invention, the common electrodes 260 of two pixel regions are connected through the first connection pattern 262 of FIG. 3, and the first common wiring 270a is connected. Through), a common voltage of negative polarity (-) is applied.

The common electrodes 260 of the two pixel regions are connected through the second connection pattern 264 of FIG. 3, and a common voltage of positive polarity is applied through the second common wiring 270b.

In other words, in a portion where the first common wiring 270a is formed, a diagonal common electrode is connected through the first connection pattern, and a negative common voltage is applied to the common electrode to be connected.

In the portion where the second common wiring 270b is formed, the common electrode in the vertical direction is connected through the second connection pattern, and a common voltage of positive polarity is applied to the common electrode to be connected.

Thus, the liquid crystal display according to the first exemplary embodiment of the present invention transfers the data voltage through the data wiring in the column inversion method, and converts the common voltage into the common voltage of negative polarity and the common voltage of positive polarity (+). By dividing and applying through each common wiring, it can be driven by the vertical 2-dot Z inversion method.

As described above, in the array substrate according to the first embodiment of the present invention, a common electrode is not formed on the entire surface of the substrate as in the related art, but a plurality of common electrodes are formed through common wiring and common contact holes by forming a common electrode for each pixel region. Connect.

As a result, it is possible to reduce the influence of the common electrode resistance compared to the conventional one formed on the front of the common electrode.

However, the array substrate according to the first embodiment of the present invention requires a common wiring and a common contact hole to connect a common electrode, and a problem arises in that the aperture ratio and transmittance are reduced by the common wiring and the common contact hole. A method for solving this problem will be described with reference to the drawings.

FIG. 7 is a plan view of a portion of an array substrate according to a second exemplary embodiment of the present invention, and FIG. 8 is a view referred to for explaining common voltage application in the liquid crystal display according to the second exemplary embodiment of the present invention.

As shown in FIG. 7, a plurality of gate lines 307 extending in the first direction are formed on the array substrate according to the second embodiment of the present invention at regular intervals.

The first common line 370a and the second common line 370b are formed on the same layer as the gate line 307 in parallel with the gate line 307.

In this case, a voltage of negative polarity (−) may be applied to the first common wiring 370a, and a voltage of positive polarity may be applied to the second common wiring 370b.

The common wirings 370a and 370b may be formed one per N of the gate wirings 307 (N is a natural number of two or more), and as a result, the number of common wirings formed on the entire substrate can be reduced.

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating film (215 of FIG. 3) on the entire surface of the substrate.

The pixel electrode 312 having a plate shape over the gate insulating film 215 and a plurality of data wires extending in a second direction and crossing the plurality of gate wires 307 to define a plurality of pixel regions ( 330 is formed.

At this time, each pixel region includes a gate electrode 308, a gate insulating film, a semiconductor layer made of pure amorphous silicon active layer (220a of FIG. 3) and an ohmic contact layer of impurity amorphous silicon (220b of FIG. 3). , And a thin film transistor Tr including a source electrode 333 and a drain electrode 336 spaced apart from each other.

The thin film transistor Tr is connected to the gate line 307 and the data line 330.

A protective layer (240 in FIG. 3) is formed on the entire surface of the substrate including the thin film transistor Tr and the pixel electrode 312.

The protective layer 240 may be made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

In addition, each pixel area may contact the first common line 370a or the second common line 370b through the first common contact hole 372a or the second common contact hole 372b on the passivation layer 240. The common electrode 360 may be formed.

That is, the common electrode 360 may be formed in each pixel region instead of being formed as one on the entire surface of the liquid crystal display on the protective layer as in the prior art.

Accordingly, in the case of a high resolution large area liquid crystal display, the influence of the common electrode resistance can be reduced.

The common electrode 360 is vertically spaced apart from the pixel electrode 312 with a protective layer interposed therebetween.

In this case, the common electrode 360 includes a plurality of openings symmetrically formed with respect to an imaginary line extending in the direction in which the gate wiring 307 extends.

Meanwhile, the common electrode 360 may be connected to neighboring common electrodes through first to third connection patterns, and the common electrodes connected to each other have the same polarity through the first common line 370a and the second common line 370b. The common voltage of can be applied.

For example, the common electrode 360 may be connected to the neighboring common electrode diagonally through the first connection pattern 362 or to the common electrode neighboring in the vertical direction through the second connection pattern 364. .

In addition, it may be connected to the common electrode neighboring in the horizontal direction through the third connection pattern (not shown).

Such connection patterns may be appropriately disposed to connect common electrodes to which a common voltage having the same polarity is applied through the first common line 370a and the second common line 370b.

As shown in FIG. 8, in the array substrate according to the second exemplary embodiment of the present invention, four common electrodes 360 of pixel regions are connected through a first connection pattern 362 and a second connection pattern 364. 1 A common voltage of negative polarity (−) is applied through the common wiring 270a.

Four common electrodes 360 of the pixel region are connected through the first connection pattern 362 and the second connection pattern 364, and a common voltage of positive polarity (+) is applied through the second common line 370b. .

In this case, the common electrode 360 is illustrated only when the first and second connection patterns 362 and 364 are connected in a diagonal direction and a vertical direction, but the present invention is not limited thereto. Through the third connection pattern may be connected in various forms.

Thus, the liquid crystal display according to the second exemplary embodiment of the present invention transfers the data voltage through the data wiring in the column inversion method, and converts the common voltage into the common voltage of negative polarity and the common voltage of positive polarity (+). It can be driven by dividing and applying through each common wiring.

As described above, in the array substrate according to the second embodiment of the present invention, the common wirings 370a and 370b are formed for each of the gate wirings 307 N (N is a natural number of two or more), thereby reducing the number of common wirings as a whole. have.

If the number of common wirings is reduced, the number of common contact holes can also be reduced. As a result, the aperture ratio and transmittance can be improved.

On the other hand, the size of the pixel region may be adjusted to reduce the aperture ratio difference caused by removing the common wiring by resizing.

The embodiments of the present invention as described above are merely illustrative, and those skilled in the art can make modifications without departing from the gist of the present invention. Accordingly, the protection scope of the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereof.

207: gate wiring 208: gate electrode
212: pixel electrode 220: semiconductor layer
230: data wiring 233: source electrode
236: drain electrode 260: common electrode
262: first connection pattern 264: second connection pattern

Claims (12)

Gate wiring and data wiring crossing each other to define a plurality of pixel regions;
A common wiring formed in parallel with the gate wiring;
A pixel electrode formed in the pixel region;
A common electrode having a plurality of openings and vertically spaced apart from the pixel electrode with a protective layer interposed therebetween,
The common wiring is formed one by one for each gate wiring N (N is a natural number of 2 or more), and the array includes a first common wiring to which a negative voltage is applied and a second common wiring to which a positive voltage is applied. Board.
The method of claim 1,
And the common electrode contacts the common wiring through a common contact hole exposing the common wiring.
The method of claim 2,
And the common contact hole includes a first common contact hole formed on the first common wiring, and a second common contact hole formed on the second common wiring.
The method of claim 1,
And the common electrode is connected to a common electrode neighboring in a diagonal direction through a first connection pattern.
The method of claim 1,
And the common electrode is connected to a common electrode neighboring in a vertical direction through a second connection pattern.
The method of claim 1,
And the common electrode is connected to a common electrode neighboring in a horizontal direction through a third connection pattern.
A first substrate having a plurality of gate lines and a plurality of data lines crossing each other and defining a plurality of pixel regions, and a second substrate facing and bonding to the first substrate,
The first substrate includes a common wiring formed parallel to the gate wiring, a pixel electrode formed in the pixel region, a common electrode having a plurality of openings spaced apart from the pixel electrode vertically with a protective layer therebetween. Lose,
The common wiring is formed one by one for the gate wiring N (N is a natural number of two or more), and the first wiring includes a first common wiring to which a negative voltage is applied, and a second common wiring to which a positive voltage is applied. LCD display device.
The method of claim 7, wherein
And the common electrode contacts the common wiring through a common contact hole exposing the common wiring.
9. The method of claim 8,
And the common contact hole includes a first common contact hole formed on the first common wire and a second common contact hole formed on the second common wire.
The method of claim 7, wherein
And the common electrode is connected to a neighboring common electrode in a diagonal direction through a first connection pattern.
The method of claim 7, wherein
And the common electrode is connected to a common electrode neighboring in a vertical direction through a second connection pattern.
The method of claim 7, wherein
And the common electrode is connected to a common electrode neighboring in a horizontal direction through a third connection pattern.

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