KR20110075410A - Liquid crystal display device and manufacturing method the same - Google Patents
Liquid crystal display device and manufacturing method the same Download PDFInfo
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- KR20110075410A KR20110075410A KR1020090131856A KR20090131856A KR20110075410A KR 20110075410 A KR20110075410 A KR 20110075410A KR 1020090131856 A KR1020090131856 A KR 1020090131856A KR 20090131856 A KR20090131856 A KR 20090131856A KR 20110075410 A KR20110075410 A KR 20110075410A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
Abstract
The present invention relates to a liquid crystal display device and a method of manufacturing the same, which reduce power consumption and improve an aperture ratio, the liquid crystal display device comprising: a plurality of gate lines formed in a first direction to have a predetermined distance on a substrate; A plurality of data lines formed in a second direction crossing the first direction to have a predetermined distance on the substrate; A reference common electrode formed to be electrically connected to each other in an intersection area of the plurality of gate lines and the plurality of data lines; A plurality of first common voltage lines at regular intervals on the substrate; A second common voltage line between each of the plurality of first common voltage lines to have a predetermined spacing on the substrate; A plurality of first liquid crystal cells connected to the gate line, i (where i is an odd or even number) data line, the reference common voltage line, and the first common voltage line; And a plurality of second liquid crystal cells connected to the gate line, the i + 1th data line, the reference common voltage line, and the second common voltage line.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a manufacturing method thereof capable of reducing power consumption and improving aperture ratio.
In general, a liquid crystal display includes a liquid crystal layer formed between two substrates including a pixel electrode and a common electrode.
In such a liquid crystal display, a voltage is applied to two electrodes to form an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust a transmittance of light passing through the liquid crystal layer to display a desired image.
Such liquid crystal display devices have been developed in various ways, such as twisted nematic (TN), in plane switching (IPS), and vertical alignment (VA) methods, depending on the arrangement of the liquid crystal layer.
The IPS method is a method of controlling the arrangement of the liquid crystal layer through a horizontal electric field by arranging the pixel electrode and the common electrode forming the electric field in parallel to the same substrate. Also called the liquid crystal display device.
On the other hand, in the liquid crystal display device, in order to prevent the deterioration of the liquid crystal caused by long-term electric field applied to the liquid crystal cell for a long time, a frame inversion method and a line inverting the polarity of the data voltage based on the common voltage. (Column) Inversion driving methods such as the Line (Column) Inversion method and the Dot Inversion method are used.
The frame inversion scheme reverses the polarity of the data voltage supplied to the liquid crystal cells whenever the frame is changed. The line inversion method inverts the polarity of the data voltage supplied to the liquid crystal cells in line (low line or column line) units and in frame units. The dot inversion method inverts the data voltage supplied to the liquid crystal cells in dot units and inverts them in frame units.
In the inversion driving method, power consumption can be reduced by reversing the polarity of the data voltage on a line-by-line basis. However, as the cross talk occurs between the liquid crystal cells in the horizontal direction, a stripe pattern is formed between the horizontal lines. There is a problem in which flicker occurs.
On the other hand, in order to increase the luminance of the liquid crystal display device, the aperture ratio must be increased by increasing the gap between the common electrode and the pixel electrode. However, when the interval is widened, a high-voltage data driver must be used to increase the aperture ratio. There is a problem that there is a limit.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is a technical object of the present invention to provide a liquid crystal display and a method of manufacturing the same, which reduce power consumption and improve aperture ratio.
According to an aspect of the present invention, a liquid crystal display device includes: a plurality of gate lines formed in a first direction to have a predetermined distance on a substrate; A plurality of data lines formed in a second direction crossing the first direction to have a predetermined distance on the substrate; A reference common electrode formed to be electrically connected to each other in an intersection area of the plurality of gate lines and the plurality of data lines; A plurality of first common voltage lines at regular intervals on the substrate; A second common voltage line between each of the plurality of first common voltage lines to have a predetermined spacing on the substrate; A plurality of first liquid crystal cells connected to the gate line, i (where i is an odd or even number) data line, the reference common voltage line, and the first common voltage line; And a plurality of second liquid crystal cells connected to the gate line, the i + 1th data line, the reference common voltage line, and the second common voltage line.
Each of the first and second common voltage lines may be formed in a step shape along each of the plurality of data lines in units of the at least one gate line.
According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, the plurality of gate lines having a predetermined interval along a first direction on a substrate and a plurality of gate lines formed therebetween to be electrically connected to each other. Forming a plurality of reference common electrodes disposed between the gate lines; Comprising a semiconductor layer and a source / drain material layer to form a plurality of data lines electrically insulated from the gate line and the plurality of reference common electrodes, spaced apart at regular intervals along a second direction crossing the first direction. Simultaneously with forming the thin film transistor; And a plurality of first common voltage lines electrically insulated from the data lines and spaced at regular intervals, second common voltage lines disposed between the plurality of first common voltage lines, and the first and second common voltage lines, respectively. A plurality of first and second common electrodes connected to the plurality of first and second common electrodes, the plurality of first and second pixels electrically connected to the thin film transistor so as to overlap the reference common electrode, and disposed between the plurality of first and second common electrodes; And forming a storage capacitor between the electrode and each of the first and second pixel electrodes and the reference common electrode.
Each of the first and second common voltage lines may be formed in a step shape along each of the plurality of data lines in units of the at least one gate line.
As described above, the liquid crystal display and the method of manufacturing the same according to the present invention form the steps of forming the first and second common voltage lines along the data lines and inverting each other in each of the first and second common voltage lines. By supplying the first and second common voltages having the level, the following effects are obtained.
First, by reducing the swing width of the data voltage supplied to the data line by half, the driving voltage can be reduced to reduce power consumption.
Second, as the driving voltage decreases, the gap between the common electrode and the pixel electrode can be widened, thereby increasing the aperture ratio of each pixel.
Third, since the voltage supplied to the common electrode and the pixel electrode can be increased due to the reduction of the driving voltage, the response speed of the liquid crystal can be improved.
Fourth, it is possible to reduce the unit cost of the data driving integrated circuit generating the data voltage due to the reduction of the driving voltage.
Fifth, by implementing the column inversion method in the vertical two-dot inversion method or the dot inversion method on the liquid crystal display panel, image quality can be improved by minimizing flicker such as a stripe pattern between horizontal lines.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a circuit diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a diagram schematically illustrating a pixel layout of a portion A shown in FIG. 1, and FIG. 3 is FIG. 1. 4 is a diagram schematically illustrating a pixel layout of a portion B shown in FIG.
1 to 3, a liquid crystal display according to an exemplary embodiment of the present invention may include a plurality of gate lines GL; A plurality of data lines; A reference common electrode RCE; A plurality of first and second common voltage lines CVL1 and CVL2; The first and second liquid crystal cells P1 and P2 are configured to be included.
The plurality of gate lines GL is formed in the first direction to have a predetermined interval on the substrate (not shown). Here, the first direction may be a long side direction of the substrate. Each of the plurality of gate lines GL is supplied with a gate signal from which a predetermined pulse width is sequentially shifted for each horizontal section.
The plurality of data lines DL are formed in a second direction crossing the first direction to have a predetermined distance on the substrate. Here, the second direction may be a short side direction of the substrate perpendicular to the first direction. The data voltages of the column inversion schemes (+,-, +,-, ...) in which polarities are inverted for each of the data lines DL are supplied to the plurality of data lines DL.
The reference common electrode RCE is formed to be electrically connected to each other in an intersection area of the plurality of gate lines GL and the plurality of data lines DL. In this case, the reference common electrode RCE is formed to have a “U” shape so as to be adjacent to two data lines DL adjacent to the second direction and adjacent to the gate line GL. The reference common electrode RCE is supplied with a reference common voltage of a direct current type having a predetermined voltage level from the outside.
The plurality of first common voltage lines CVL1 are formed in a step shape along each of the plurality of data lines DL in units of two gate lines GL so as to have a predetermined interval. The plurality of first common voltage lines CVL1 are supplied with a first common voltage from which the high voltage level and the low voltage level are inverted in units of at least one frame from the outside.
The plurality of second common voltage lines CVL1 are formed between the plurality of first common voltage lines CVL1 to have a predetermined interval, and each of the plurality of data lines DL in units of two gate lines GL. It is formed in the form of a staircase. The plurality of second common voltage lines CVL2 are supplied with a second common voltage having a voltage level inverted to the first common voltage supplied from the outside to the first common voltage line CVL1.
The plurality of first liquid crystal cells P1 are connected to a gate line GL, an i (where i is an odd or even number) data line DL, a reference common electrode RCE, and a first common voltage line CVL1. The light transmittance of the liquid crystal is adjusted according to the data voltage supplied to the data line DL in response to the gate signal supplied to the gate line GL. To this end, the plurality of first liquid crystal cells P1 may include the first thin film transistor T1, the first pixel electrode line PEL1, the plurality of first common electrodes CE1, the plurality of first pixel electrodes PE1, And a first storage capacitor Cst1.
The first thin film transistor T1 protrudes from the gate electrode GE protruding from the gate line GL, the semiconductor layer SL formed to be insulated from the gate electrode GE, and protrudes from the data line DL. And a drain electrode DE formed in the “U” shaped source electrode SE while overlapping the source electrode SE, the reference common electrode RCE, and the gate line GL.
The first thin film transistor T1 is switched according to a gate signal supplied to the gate line GL to supply a data voltage supplied from the i-th data line DL to the first pixel electrode line PEL1.
Meanwhile, the first thin film transistor T1 is formed in a zigzag pattern in the left and right direction along the data line DL in units of two gate lines GL between two adjacent data lines DL. That is, the first thin film transistor T1 connected to the gate lines GL of the 4j-3 th and 4j-2 th horizontal lines is connected to the i th data line DL adjacent to the left side, and the 4j-1 th and 4j. The first thin film transistor T1 connected to the gate line GL of the first horizontal line is connected to the i-th data line DL adjacent to the right side.
The first pixel electrode line PEL1 is electrically connected to the drain electrode DE through the contact hole CTH and overlapped with the reference common electrode RCE.
Each of the plurality of first common electrodes CE1 protrudes at a predetermined distance from the first common voltage line CVL1 to be parallel to the data line DL and is formed between two adjacent data lines DL. Each of the plurality of first common electrodes CE1 is supplied with a first common voltage in which the high voltage level and the low voltage level are inverted in at least one frame unit from the first common voltage line CVL1. do. Here, each of the plurality of first common electrodes CE1 may be formed in a straight shape, a comb teeth shape, or a zigzag shape.
Each of the plurality of first pixel electrodes PE1 protrudes from the first pixel electrode line PEL1 at regular intervals and is spaced apart from each of the plurality of first common electrodes CE1 at predetermined intervals. It is formed every CE1). Each of the plurality of first pixel electrodes PE1 is supplied with a data voltage from the first pixel electrode line PEL1. Here, each of the plurality of first pixel electrodes PE1 is formed in the same shape to be parallel to each of the plurality of first common electrodes CE1.
A liquid crystal layer (not shown) is formed on the plurality of first common electrodes CE1 and the plurality of first pixel electrodes PE1, and thus, the plurality of first common electrodes CE1 and the plurality of first common electrodes CE1 formed with the liquid crystal layer interposed therebetween. One pixel electrode PE1 forms the first liquid crystal capacitor Clc1. Here, the first liquid crystal capacitor Clc1 is supplied with a positive data voltage and a first common voltage having a low voltage level or a first common voltage having a negative data voltage and a high voltage level according to a frame. Voltage is supplied. Accordingly, the first liquid crystal capacitor Clc1 may have positive polarity (+) in the liquid crystal layer according to the data voltage and the first common voltage supplied to each of the plurality of first common electrodes CE1 and the plurality of first pixel electrodes PE1. ) Or by forming a horizontal electric field in the negative (-) direction to adjust the light transmittance of the liquid crystal layer to display an image.
The first storage capacitor Cst1 is formed between the first pixel electrode line PEL1 and the reference common electrode RCE. The first storage capacitor Cst1 is disposed between the data voltage supplied to the first pixel electrode line PEL1 and the reference common voltage supplied to the reference common electrode RCE according to the turn-on of the first thin film transistor T1. The difference voltage is stored, and the driving of the first liquid crystal capacitor Clc1 is maintained for one frame by using the stored voltage as the first thin film transistor T1 is turned off.
The plurality of second liquid crystal cells P2 are connected to the gate line GL, the i + 1th data line DL, the reference common electrode RCE, and the second common voltage line CVL2 to connect to the gate line GL. The liquid crystal light transmittance is adjusted according to the data voltage supplied to the data line DL in response to the supplied gate signal. To this end, the plurality of second liquid crystal cells P2 may include the second thin film transistor T2, the second pixel electrode line PEL2, the plurality of second common electrodes CE2, the plurality of second pixel electrodes PE2, And a second storage capacitor Cst2.
The second thin film transistor T2 protrudes from the gate electrode GE protruding from the gate line GL, the semiconductor layer SL formed to be insulated from the gate electrode GE, and the i + 1 th data line DL. A source electrode SE formed in a U shape, overlapping the reference common electrode RCE and a gate line GL, and including a drain electrode DE formed so as to be spaced apart from the “U” shaped source electrode SE. It is configured by.
The second thin film transistor T2 is switched according to the gate signal supplied to the gate line GL to supply the data voltage supplied from the i + 1 th data line DL to the second pixel electrode line PEL2. .
Meanwhile, the second thin film transistor T2 is formed in a zigzag pattern in the left and right direction along the data line DL in units of two gate lines GL between two adjacent data lines DL. That is, the second thin film transistor T2 connected to the gate lines GL of the 4j-3 th and 4j-2 th horizontal lines is connected to the i + 1 th data line DL adjacent to the left, and the 4j-1 th And the second thin film transistor T2 connected to the gate line GL of the 4jth horizontal line is connected to the i + 1th data line DL adjacent to the right side.
The second pixel electrode line PEL2 is electrically connected to the drain electrode DE through the contact hole CTH and overlapped with the reference common electrode RCE.
Each of the plurality of second common electrodes CE2 protrudes at a predetermined distance from the second common voltage line CVL2 to be parallel to the data line DL and is formed between two adjacent data lines DL. Each of the plurality of second common electrodes CE2 is supplied with a second common voltage whose voltage level is inverted in at least one frame unit from the second common voltage line CVL2. Here, each of the plurality of second common electrodes CE2 is formed in the same shape as the plurality of first common electrodes CE1.
Each of the plurality of second pixel electrodes PE2 protrudes from the second pixel electrode line PEL2 at regular intervals and is spaced apart from each of the plurality of second common electrodes CE2 at predetermined intervals. It is formed between CE2). Each of the plurality of second pixel electrodes PE2 is supplied with a data voltage from the second pixel electrode line PEL2. Here, each of the plurality of second pixel electrodes PE2 is formed in the same shape to be parallel to each of the plurality of second common electrodes CE2.
A liquid crystal layer (not shown) is formed on the plurality of second common electrodes CE2 and the plurality of second pixel electrodes PE2, and thus, the plurality of second common electrodes CE2 and the plurality of second common electrodes CE2 formed therebetween are formed. The second pixel electrode PE2 forms the second liquid crystal capacitor Clc2. Here, the second liquid crystal capacitor Clc2 is supplied with a negative data voltage and a second common voltage having a high voltage level or a second data voltage having a positive data voltage and a low voltage level according to a frame. 2 Common voltage is supplied. Accordingly, the second liquid crystal capacitor Clc2 has a positive polarity (+) in the liquid crystal layer according to the data voltage and the second common voltage supplied to each of the plurality of second common electrodes CE2 and the plurality of second pixel electrodes PE2. ) Or by forming a horizontal electric field in the negative (-) direction to adjust the light transmittance of the liquid crystal layer to display an image.
The second storage capacitor Cst2 is formed between the pixel electrode line PEL and the reference common electrode RCE. The second storage capacitor Cst2 has a difference voltage between a data voltage supplied to the pixel electrode line PEL and a reference common voltage supplied to the reference common electrode RCE according to the turn-on of the second thin film transistor T2. The second liquid crystal capacitor Clc2 is driven for one frame by using the stored voltage according to the turn-off of the second thin film transistor T2.
As described above, the liquid crystal display according to the exemplary embodiment of the present invention forms the first and second common voltage lines CVL1 and CVL2 in the form of steps along the data lines DL and also the first and second common voltage lines. By supplying the first and second common voltages having voltage levels inverted to each of the CVL1 and CVL2, the swing width of the data voltage supplied to the data line DL can be reduced by half, thereby reducing power consumption. As a result, the gap between the common electrode and the pixel electrode can be widened, thereby increasing the aperture ratio of each pixel P. FIG.
In addition, the present invention is a horizontal line by inverting the data voltage of the column inversion method for each liquid crystal cell (P) in the first direction of the liquid
Meanwhile, in the liquid crystal display according to the exemplary embodiment of the present invention, each of the first and second common voltage lines CVL1 and CVL2 is formed in a step shape along the data lines DL in units of two gate lines GL. As illustrated in FIG. 4, each of the first and second common voltage lines CVL1 and CVL2 is formed in a stepped shape along the data lines DL in units of one gate line GL, thereby providing a column. By displaying the inversion data voltage on the liquid
5A through 5E are plan views illustrating step-by-step methods of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.
A manufacturing method of the liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5E as follows.
First, as illustrated in FIG. 5A, a gate material layer is formed on a front surface of a substrate (not shown), and the gate material layer is selectively patterned so that the plurality of gate lines GL are spaced at regular intervals along the first direction. And the gate electrodes GE protruding from the gate lines GL, and the plurality of “U” shaped reference common electrodes RCE electrically connected to each other so as to be adjacent to each gate line GL. Form.
Subsequently, a gate insulating film (not shown) is formed on the entire surface of the substrate including the plurality of gate lines GL, the gate electrode GE, and the plurality of reference common electrodes RCE.
Next, as illustrated in FIG. 5B, a semiconductor material layer is formed on the entire surface of the gate insulating film, and the semiconductor material layer is selectively patterned to form the semiconductor layer SL in a region corresponding to the gate electrode GE. Here, the process of selectively patterning the semiconductor material layer to form the semiconductor layer SL may be omitted to reduce the number of mask processes, and it will be assumed below.
Then, as illustrated in FIG. 5C, a source / drain material layer is formed on the entire surface of the semiconductor material layer, and the source / drain material layer and the semiconductor material layer are selectively simultaneously patterned to cross the first direction. A plurality of data lines DL spaced apart from each other at regular intervals are formed, and a plurality of thin film transistors T are formed on each gate electrode GE.
Each of the thin film transistors T includes a semiconductor layer SL formed to be insulated from the gate electrode GE, a source electrode SE protruding from the data line DL, and formed in a “U” shape, and a reference common electrode RCE. ) And a gate electrode GL and a drain electrode DE formed in the source electrode SE having a “U” shape.
Each of the plurality of thin film transistors T is formed to be disposed in a zigzag form along the data line DL in two gate line units GL between two adjacent data lines DL.
Then, a protective film (not shown) and a planarization layer (not shown) are sequentially formed on the entire surface of the gate insulating film including the plurality of data lines DL and the plurality of thin film transistors T. Here, the planarization layer may be an inorganic material or an organic material having a low dielectric constant, and may be made of, for example, a PAC or SiNx material.
Then, as shown in FIG. 5D, the protective film and the planarization layer formed on the drain electrode DE are partially removed to form a contact hole CTH for exposing a predetermined portion of the drain electrode DE.
Then, as shown in 5e, the first conductive material layer and the second conductive material layer are sequentially formed on the front surface of the planarization layer including the contact hole CTH.
Thereafter, by selectively patterning the first conductive material layer and the second conductive material layer, a plurality of first common voltage lines CVL1 spaced at regular intervals may be disposed between the plurality of first common voltage lines CVL1. The thin film so as to overlap the plurality of first and second common electrodes CE1 and CE2 and the reference common electrode RCE connected to the second common voltage line CVL2 and the first and second common voltage lines CVL1 and CVL2, respectively. A plurality of first and second pixel electrodes PE1 and PE2, which are electrically connected to the transistor T and disposed between the plurality of first and second common electrodes CE1 and CE2, and the pixel electrode PE and the reference The storage capacitor Cst is simultaneously formed between the common electrodes RCE.
Each of the first and second common voltage lines CVL1 and CVL2 is formed in a step shape along each of the plurality of data lines DL in units of two gate lines GL.
Each of the pixel electrodes PE1 and PE2, the first common voltage line CVL1, and the plurality of first common electrodes CE1 is formed of a first conductive material layer, whereas the second common voltage line CVL2 and the plurality of first electrodes Each of the two common electrodes CE2 includes first and second conductive material layers.
Accordingly, the gate line GL, the i-th data line DL, and the reference common voltage line are in units of two gate lines GL and i (where i is an odd or even number) on the substrate. A plurality of first liquid crystal cells P1 connected to the RCE and the first common voltage line CVL1 are provided. In addition, the gate line GL, the i + 1th data line DL, the reference common voltage line RCE, and the second gate line GL and the i + 1th data line DL are disposed on the substrate. A plurality of second liquid crystal cells P2 connected to the common voltage line CVL2 are provided.
6A to 6F are cross-sectional views illustrating a manufacturing process corresponding to FIG. 5E in detail by cutting C-C ′ illustrated in FIG. 5E.
First, as illustrated in FIG. 6A, a substrate on which a reference common electrode RCE, a
Then, as illustrated in FIG. 6B, the first to third mask patterns MP1 and MP2 are formed in predetermined regions on the second
Next, as shown in FIG. 6C, the second
Then, as illustrated in FIG. 6D, the first and third mask patterns MP1 and MP3 are removed through an ashing process.
Next, as shown in FIG. 6E, the second
Accordingly, the pixel electrode PE, the first common voltage line CVL1, and the plurality of first common electrodes CE1 formed of the first
6F, the second common voltage line CVL2 including the first and second conductive material layers 140 and 150 and the plurality of second common electrodes are removed by removing the second mask pattern MP2. (CE2) is formed. In this case, the width of the second common voltage line CVL2 including the first and second conductive material layers 140 and 150 is patterned to be wider than that of the first common voltage line CVL1.
As such, the process time is shortened by forming the first and second common voltage lines CVL1 and CVL2, the plurality of first and second common electrodes CE1 and CE2, and the pixel electrode PE by using the halftone photo mask. You can.
Meanwhile, in the method of manufacturing the liquid crystal display according to the exemplary embodiment described above, each of the first and second common voltage lines CVL1 and CVL2 is a step along the data lines DL in units of two gate lines GL. As illustrated in FIG. 4, each of the first and second common voltage lines CVL1 and CVL2 has a step shape along the data lines DL in the unit of one gate line GL. Can be formed.
Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.
1 is a circuit diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for schematically describing a pixel layout of a portion A shown in FIG. 1.
FIG. 3 is a diagram for schematically describing a pixel layout of a portion B illustrated in FIG. 1.
4 is a circuit diagram illustrating another embodiment of a liquid crystal display according to an exemplary embodiment of the present invention.
5A through 5E are plan views illustrating step-by-step methods of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.
6A to 6F are cross-sectional views illustrating a manufacturing process corresponding to FIG. 5E in detail by cutting C-C ′ illustrated in FIG. 5E.
Claims (12)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090131856A KR20110075410A (en) | 2009-12-28 | 2009-12-28 | Liquid crystal display device and manufacturing method the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020090131856A KR20110075410A (en) | 2009-12-28 | 2009-12-28 | Liquid crystal display device and manufacturing method the same |
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| Publication Number | Publication Date |
|---|---|
| KR20110075410A true KR20110075410A (en) | 2011-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020090131856A KR20110075410A (en) | 2009-12-28 | 2009-12-28 | Liquid crystal display device and manufacturing method the same |
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| Country | Link |
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| KR (1) | KR20110075410A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130017157A (en) * | 2011-08-10 | 2013-02-20 | 엘지디스플레이 주식회사 | Array substrate and liquid crystal display device including thereof |
| KR20150076418A (en) * | 2013-12-26 | 2015-07-07 | 삼성디스플레이 주식회사 | Display device |
-
2009
- 2009-12-28 KR KR1020090131856A patent/KR20110075410A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130017157A (en) * | 2011-08-10 | 2013-02-20 | 엘지디스플레이 주식회사 | Array substrate and liquid crystal display device including thereof |
| KR20150076418A (en) * | 2013-12-26 | 2015-07-07 | 삼성디스플레이 주식회사 | Display device |
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