KR20070080143A - A liquid crystal display device - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to make it possible to form an auxiliary capacitor without reduction of an aperture ratio, by forming a common voltage line for the auxiliary capacitor in a non-pixel region. First gate lines(GL1) and second gate lines(GL2) are disposed across a plurality of data lines(DL). A plurality of common voltage lines(CL) are disposed alternately with the data lines. A pixel electrode(PE) is formed between each of the data lines and each of the common voltage lines. The pixel electrode overlaps a portion of the common voltage line. First switching elements(TFT1) are formed at crossing portions of the first gate lines and the data lines. Second switching elements(TFT2) are formed at crossing portions of the second gate lines and the data lines.

Description

Liquid crystal display device

1 is a view illustrating several pixel cells included in a conventional DLS type liquid crystal display device.

2 is a view showing a liquid crystal display device according to an embodiment of the present invention.

3 is a diagram illustrating two arbitrary adjacent pixel cells of FIG. 2;

4 is a cross-sectional view taken along the line of I-I of FIG. 3 and the line of II-II.

FIG. 5 is a diagram illustrating each pixel cell of FIG. 3 as an electrical equivalent circuit. FIG.

* Explanation of symbols on the main parts of the drawings

GL1: first gate line GL2: second gate line

DL: Data line PE: Pixel electrode

HL1: first pixel row HL2: second pixel row

SC1: first auxiliary capacitor SC2: second auxiliary capacitor

TFT1: first thin film transistor TFT2: second thin film transistor

CL: common voltage line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of increasing an aperture ratio by forming a common voltage line between data lines in a DLS structure.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a scan pulse applied to a gate terminal via the gate line, so that the data signal of the data line is charged to the pixel voltage.

Recently, in order to reduce the number of data lines, a data line sharing (DLS) technique in which one adjacent data line is shared by two adjacent pixel cells has been proposed.

Hereinafter, a conventional DLS type liquid crystal display device will be described in detail with reference to the accompanying drawings.

1 is a view showing several pixel cells included in a conventional DLS type liquid crystal display device.

In the conventional DLS type liquid crystal display, as shown in FIG. 1, a plurality of gate lines GL, a plurality of data lines DL positioned to intersect the gate lines GL, The pixel electrode PE formed in each pixel area defined by each of the gate lines GL and the data lines DL, and near the intersection of the gate lines GL and the data lines DL. The thin film transistor TFT includes a thin film transistor TFT and a common voltage line CL crossing the pixel regions so as to overlap all of the pixel electrodes PE.

Here, the data lines DL are positioned one per two pixel areas adjacent to each other. Accordingly, the pixel electrodes PE positioned on both sides of the one data line DL sequentially receive data signals from the data line DL to display an image.

Therefore, when defining the pixel electrodes PE shown in FIG. 1 as the first, second, third, and fourth pixel electrodes PE in order from left to right, the second pixel electrode PE and the first pixel electrode PE are defined. The data line DL is not formed between the three pixel electrodes PE. Accordingly, the number of data lines DL can be reduced.

1 illustrates a configuration of a lower substrate of a liquid crystal display, and the liquid crystal display further includes an upper substrate facing the lower substrate.

The upper substrate includes a plurality of color filter layers and a black matrix layer. The color filter layer is formed in each pixel region of the upper substrate, and the black matrix layer is formed on the entire surface of the upper substrate except for the pixel regions.

However, the conventional liquid crystal display device has a problem that the aperture ratio decreases because the common voltage line CL is formed to cross the pixel areas.

The common voltage line CL is designed to overlap the center of each pixel electrode PE to form a storage capacitor in each pixel area.

That is, each of the storage capacitors is formed at a portion where the common voltage line CL and the pixel electrode PE overlap each other. In this case, the first electrode of each storage capacitor is composed of the pixel electrode PE. The second electrode consists of a common voltage line CL.

This storage capacitor allows each pixel cell to stably maintain the data signal of one frame supplied to it until the next frame.

As described above, the conventional DLS type liquid crystal display has a problem in that the aperture ratio can be reduced to form the storage capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and alternately positions data lines and common voltage lines, and forms a pixel electrode between each data line and each common voltage line, wherein the pixel electrode It is an object of the present invention to provide a liquid crystal display device in which a part of the common electrode is overlapped to form a storage capacitor without reducing the aperture ratio.

A liquid crystal display according to the present invention for achieving the above object, a plurality of data lines; First and second gate lines positioned to intersect the plurality of data lines; A plurality of common voltage lines alternately located with the plurality of data lines; And a pixel electrode formed between each data line and each common voltage line and overlapping a part of the common line.

The data lines may be formed between the common voltage lines.

Each common voltage line is formed between each data line.

The pixel electrode positioned on one side of an arbitrary common line overlaps the upper side of the arbitrary common line, and the pixel electrode positioned on the other side of the arbitrary common line overlaps the lower side of the arbitrary common line.

Each pixel electrode positioned at both sides of an arbitrary data line is sequentially supplied with a data signal through the arbitrary data line.

A first switching element formed near the intersection between the first gate line and each data line; And a second switching element formed in the vicinity of the intersection between the second gate line and each data line.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view showing a liquid crystal display device according to an exemplary embodiment of the present invention. Specifically, FIG. 2 shows a configuration of a lower substrate.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 2, a plurality of data lines DL arranged in one direction and a plurality of data lines DL arranged alternately with the data lines DL are arranged. And a plurality of first and second gate lines GL1 and GL2 arranged to intersect common voltage lines CL and the plurality of data lines DL and the plurality of common voltage lines CL. .

Although not shown, the liquid crystal display according to the exemplary embodiment of the present invention further includes an upper substrate corresponding to the lower substrate. A color filter layer, a common electrode, and a black matrix layer are formed on the upper substrate.

The color filter layer is formed on each pixel area PED of the upper substrate, the black matrix layer is formed on the entire surface of the upper substrate except for the pixel area PED, and the common electrode is the pixel area PED. And a front surface of the upper substrate including the black matrix layer. The liquid crystal layer is formed between the upper substrate and the lower substrate configured as described above.

The data lines DL and the common voltage lines CL are arranged in parallel to each other, and each data line DL is positioned between each common voltage line CL. Although not shown in the drawings, the common voltage lines CL may be positioned between the data lines DL.

2 illustrates an arbitrary two pixel rows, in which one pixel row includes a plurality of data lines DL, a plurality of common voltage lines CL, a plurality of pixel electrodes PE, A first gate line GL1 for driving the first thin film transistors TFT1 and a second gate line GL2 for driving the second thin film transistors TFT2 are included.

Here, all the pixel rows HL1, HL2,... HLn share the data lines DL and the common voltage line CL.

The pixel rows HL1, HL2, ... HLn will be described in more detail as follows.

On the other hand, since the structures of all the pixel rows HL1, HL2, ..., HLn are the same, the first pixel row HL1 will be representatively described.

Each of the first thin film transistors TFT1 is formed near the intersection of the first gate line GL1 and each data line DL. The first thin film transistor TFT1 is turned on according to the gate signal from the first gate line GL1 to supply the data signal from the data line DL to the pixel electrode PE.

Each of the second thin film transistors TFT2 is formed near the intersection of the second gate line GL2 and each data line DL. The second thin film transistor TFT2 is turned on according to the gate signal from the second gate line GL2 to supply the data signal from the data line DL to the pixel electrode PE.

In this case, since the gate signal is sequentially supplied to the first gate line GL1 and the second gate line GL2, the first gate line GL1 is driven first, and then the second gate line GL2 is driven. .

Therefore, first thin film transistors TFT1 connected to the first gate line GL1 are first turned on, and second thin film transistors TFT2 connected to the second gate line GL2 are turned on.

The first thin film transistor TFT1 and the second thin film transistor TFT2 are commonly connected to one data line DL, and data signals are sequentially supplied to the data line DL.

That is, when the first gate signal is supplied to the first gate line GL1, a first data signal is supplied to the data line DL, and a second gate signal is supplied to the second gate line GL2. At the point of time, a second data signal is supplied to the data line DL.

For example, a pixel cell provided on the leftmost of the pixel cells included in the first pixel row HL1 is defined as a first pixel cell, and a pixel cell immediately adjacent to the first pixel cell is defined as a second pixel cell. When the pixel cell is defined, the first data signal of the data line DL is supplied to the pixel electrode PE of the first pixel cell through a first thin film transistor TFT1 when the first gate signal is turned on. When the second gate signal is turned on, the second data signal of the data line DL is supplied to the pixel electrode PE of the second pixel cell through the second thin film transistor TFT2.

Here, the pixel cells provided in the first pixel row HL1 will be described in more detail as follows.

First, with this structure, one pixel region PED in the present invention is connected to the common voltage line CL, the data line DL, the first gate line GL1, and the second gate line GL2. It is defined as the area surrounded by. In this case, the pixel area PED does not include an area where the thin film transistors TFT1 and TFT2 are formed.

Each pixel cell includes a pixel area PED, a pixel electrode PE, a common electrode, a liquid crystal capacitor, and an auxiliary capacitor SC1 or SC2. The even-numbered pixel cells of the pixel cells include a first gate line. A first thin film transistor TFT1 and a first auxiliary capacitor SC1 connected to the GL1 and the odd pixel cells are connected to the second thin film transistor TFT2 and the second connected to the second gate line GL2. A storage capacitor capacitor (SC2) is included.

The liquid crystal capacitor is a capacitor having a first electrode made of the pixel electrode PE, a second electrode made of the common electrode, and a liquid crystal layer formed between the pixel electrode PE and the common electrode.

The first and second storage capacitors SC1 and SC2 may include a first electrode made of the pixel electrode PE, a second electrode made of the common voltage line CL, and a common voltage with the pixel electrode PE. It is a capacitor having an insulating film formed between the lines CL.

In this case, the first and second storage capacitors SC1 and SC2 located between the data lines DL share one common voltage line CL. That is, the first and second storage capacitors SC1 and SC2 commonly use one common voltage line CL as the second electrode.

To this end, each pixel electrode PE provided in two adjacent pixel cells has a structure as follows.

FIG. 3 is a diagram illustrating two arbitrary adjacent pixel cells of FIG. 2, and FIG. 4 is a cross-sectional view taken along lines I to I and lines II to II of FIG. 3.

That is, as shown in FIG. 3, the first pixel electrode PE1 of the first pixel cell is formed in the first pixel region PED1 so as to overlap the lower side of the common voltage line CL, The second pixel electrode PE2 is formed in the second pixel region PED2 so as to overlap the upper side of the common voltage line CL. As shown in FIG. 4B, the first storage capacitor SC1 includes the first pixel electrode PE1, the common voltage line CL, and an insulating film (a gate insulating film GI and a protective film 335). ))

A first storage capacitor SC1 is formed at a portion 301 (hatched portion 301 of FIG. 3) where the first pixel electrode PE1 and the lower side of the common voltage line CL overlap each other. The second storage capacitor SC2 is formed in the portion 302 (hatched portion 302 of FIG. 3) where the two pixel electrodes PE2 and the upper side of the common voltage line CL overlap. As shown in FIG. 4A, the second storage capacitor SC2 includes the second pixel electrode PE2, the common voltage line CL, and an insulating film (a gate insulating film GI and a protective film 335). ))

As described above, in the present invention, since the common voltage line CL for forming the storage capacitors SC1 and SC2 does not cross the pixel region PED but is formed in the non-pixel region, the aperture ratio of the pixel region PED is reduced. Can be prevented.

In addition, since a black matrix layer is formed on a portion of the upper substrate except for the pixel region PED (ie, the non-pixel region), light leakage may be prevented in a portion where the storage capacitors SC1 and SC2 are formed.

3 and 4, the first thin film transistor TFT1 includes the gate electrode GE protruding from the first gate line GL1 and the source electrode SE protruding from the data line DL. The drain electrode DE is electrically connected to the first pixel electrode PE1, the semiconductor layer 333, and the ohmic contact layer 334.

The second thin film transistor TFT2 is electrically connected to the gate electrode GE protruding from the second gate line GL2, the source electrode SE protruding from the data line DL, and the second pixel electrode PE2. The drain electrode DE, the semiconductor layer 333, and the ohmic contact layer 334 are connected to each other.

Here, the non-described '400' of FIG. 4 represents the lower substrate.

5 is an electrical equivalent circuit of each pixel cell of FIG. 3. As shown in the drawing, the first pixel cell includes a first thin film transistor TFT1 and a first liquid crystal capacitor 501. And a first storage capacitor (SC1), and the second pixel cell includes a second thin film transistor (TFT2), a second liquid crystal capacitor (502), and a second storage capacitor (SC2). Here, the non-described '555' in FIG. 5 represents the common electrode.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The liquid crystal display according to the present invention as described above has the following effects.

The liquid crystal display according to the present invention includes a plurality of alternating data lines and a plurality of common voltage lines, and pixel electrodes formed between the data lines and each common voltage line. In this case, each pixel electrode overlaps a part of each common voltage line, and the storage capacitor is formed in the overlapped part.

As described above, in the present invention, as the common voltage line for forming the storage capacitor is formed in the non-pixel region rather than the pixel region, the aperture ratio of the pixel region is prevented from decreasing.

Claims (6)

Multiple data lines; First and second gate lines positioned to intersect the plurality of data lines; A plurality of common voltage lines alternately located with the plurality of data lines; And, And a pixel electrode formed between each data line and each common voltage line and overlapping a part of the common line. The method of claim 1, And each data line is formed between each common voltage line. The method of claim 1, And each common voltage line is formed between each data line. The method of claim 1, The pixel electrode positioned on one side of an arbitrary common line overlaps the upper side of the arbitrary common line, and the pixel electrode positioned on the other side of the arbitrary common line overlaps the lower side of the arbitrary common line. Display. The method of claim 1, And each pixel electrode positioned at both sides of an arbitrary data line is sequentially supplied with a data signal through the arbitrary data line. The method of claim 1, A first switching element formed near the intersection between the first gate line and each data line; And, And a second switching element formed near the intersection between the second gate line and each data line.

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