KR20110071036A - Display device - Google Patents

Abstract

PURPOSE: A display device is provided to prevent the brightness difference between pixel areas due to a misalignment of a black matrix pattern. CONSTITUTION: A display device comprises a first gate line(GL1) which is extended to a first direction, a second gate line(GL2) which is arranged in parallel with the first gate line, data lines(DL1,DL2) which are crossing the first and the second gate lines, a first sub common line(101) which is arranged in parallel with the data line, and a second sub common line(102) which is placed adjacent to the data line and electrically connected with the first common line.

Description

Display device {DISPLAY DEVICE}

An embodiment relates to a display device.

Currently, an active matrix liquid crystal display device having a thin film transistor (Thin-Film-Transistor) and pixel electrodes connected to the thin film transistor in a matrix manner is attracting the most attention due to its excellent resolution and ability to implement video.

In particular, in-plane switching (IPS) liquid crystal display devices in which a common electrode and a pixel electrode are disposed together on an array substrate are widely used.

Light leakage to the driving region of the liquid crystal display according to the prior art is blocked by the black matrix provided on the upper substrate, if the unevenness between the light leakage or the pixel due to misalignment that may occur when the upper substrate and the lower substrate is bonded. Will occur.

In addition, in order to prevent light leakage that may be generated in this way, when the width of the black matrix is widened, there is a problem that the aperture ratio is reduced.

Embodiments provide a display device that prevents a phenomenon in which luminance differences between pixel regions are generated due to misalignment of a black matrix pattern.

In an exemplary embodiment, a display device includes: a first gate wire extending in a first direction; A second gate line arranged in parallel with the first gate line; A data line crossing the first gate line and the second gate line; First common wiring adjacent to the data wiring and arranged in parallel with the data wiring; A second common line electrically connected to the first common line and adjacent to the data line and disposed in parallel with the data line; A first thin film transistor disposed in an area crossing the first gate line and the data line; A first main pixel electrode connected to the first thin film transistor and overlapping the first common line; And a second main common electrode overlapping the second common wiring and connected to the second common wiring, wherein the data wiring is disposed between the first common wiring and the second common wiring.

In an exemplary embodiment, a display device includes: a first gate line and a second gate line extending in parallel with each other; First and second data wires crossing the first gate wire and the second gate wire; A first common line adjacent to the first data line and arranged in parallel with the first data line; A second common wiring adjacent to the second data wiring and arranged in parallel with the second data wiring; Interposed between the first common line and the second common line, connected to the first common line and the second common line, define the first common line and the first pixel area, and define the second common line. A third common wiring defining a wiring and a second pixel region; A first thin film transistor disposed in a region where the first gate line and the first data line cross each other; A first main pixel electrode connected to the first thin film transistor and partially overlapping the third common electrode; And a second main common electrode connected to the third common electrode, spaced apart from the first main pixel electrode, and partially overlapping with the third common electrode.

In the display device according to the exemplary embodiment, the main pixel electrode and the main common electrode are disposed on both sides of the data line. In particular, the display device according to the embodiment arranges the main pixel electrode on one side and the main common electrode on the other side of the data line.

That is, the display device according to the exemplary embodiment may configure the plurality of pixel areas by repeating such an arrangement structure.

Therefore, the display device according to the exemplary embodiment may regularly arrange the plurality of main common electrodes and the plurality of main pixel electrodes in the above structure, and thus the sub common electrodes and the sub pixel electrodes may extend in a desired direction.

Therefore, the display device according to the embodiment includes pixel areas having the same shape. Accordingly, even if the black matrix pattern is misaligned, the luminance of each pixel area is equally reduced.

Accordingly, the display device according to the exemplary embodiment may prevent the luminance difference from occurring between the pixel areas and implement an improved image quality.

In the description of the embodiment, each panel, member, plate, sheet, cover, or layer is formed on or under the "on" of each panel, member, plate, sheet, cover, or layer, or the like. When described as being "in" and "under" includes both those that are formed "directly" or "indirectly" through other components. In addition, the upper or lower reference of each component is described with reference to the drawings. The size of each component in the drawings may be exaggerated for the sake of explanation and does not mean the size actually applied.

1 is a plan view showing a TFT array substrate. FIG. 2 is a cross-sectional view taken along line AA ′ in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB ′ in FIG. 1. 4 is a cross-sectional view taken along line CC ′ in FIG. 1. 5 is a plan view showing a state in which a TFT array substrate and a black matrix pattern are normally aligned. FIG. 6 is a plan view illustrating a state in which a TFT array substrate and a black matrix pattern are misaligned.

1 to 6, the liquid crystal display according to the embodiment includes a TFT array substrate 10, a color filter substrate 20, and a liquid crystal layer 30.

The TFT array substrate 10 faces the color filter substrate 20. The TFT array substrate 10 includes a plurality of driving elements for driving the liquid crystal layer 30.

The TFT array substrate 10 includes a transparent substrate 100, a plurality of gate lines GL1, GL2..., A plurality of data lines DL1, DL2 .., and a plurality of common lines CL. , A plurality of thin film transistors TR1, TR2..., A plurality of pixel electrodes 210, 220..., And a plurality of common electrodes 310, 320.

The gate lines GL1, GL2... Extend in the first direction. The gate lines GL1, GL2... Are arranged next to each other. The gate lines GL1, GL2... Are disposed on the transparent substrate 100. The gate lines GL1 and GL2... Are spaced apart from each other at regular intervals.

For example, the TFT array substrate 10 may include a first gate line GL1 and a second gate line GL2.

The first gate line GL1 and the second gate line GL2 are arranged side by side with each other. The first gate line GL1 and the second gate line GL2 are spaced apart from each other and extend in the first direction.

Examples of the material used for the first gate line GL1 and the second gate line GL2 include molybdenum, titanium, aluminum, tungsten, and the like.

The data lines DL1, DL2... Intersect the gate lines GL1, GL2. The data lines DL1, DL2... Are spaced apart from each other. The data lines DL1, DL2... Extend in parallel with each other in a second direction.

The data lines DL1, DL2... Are disposed on the gate insulating layer 140 covering the gate lines GL1, GL2. That is, the gate insulating layer 140 is interposed between the gate lines GL1 and GL2... And the data lines DL1 and DL2.

The data lines DL1, DL2... And the gate lines GL1, GL2... Define two pixel areas P1, P2. That is, two pixel areas are disposed in an area defined by the data lines DL1, DL2... And the gate lines GL1, GL2.

Examples of the material used for the data wires DL1, DL2... May include a metal such as molybdenum, titanium, aluminum, tungsten, or the like.

For example, the TFT array substrate 10 includes a first data line DL1, a second data line DL2, and a third data line DL3.

The first data line DL1, the second data line DL2, and the third data line DL3 are arranged in parallel with each other, and the first gate line GL1 and the second gate line GL2 are disposed in parallel with each other. To cross. The first data line DL1, the second data line DL2, and the third data line DL3 extend in the second direction.

The common lines CL are interposed between the gate lines GL1 and GL2... The common lines CL are electrically connected to each other. The common lines CL may be disposed on the same layer as the gate lines GL1 and GL2. That is, the common lines CL are disposed on the transparent substrate 100 and covered by the gate insulating layer 140.

The common lines CL extend and define a plurality of pixel regions P1, P2... That is, examples of the material used as the common lines CL may include a metal such as molybdenum, titanium, aluminum, or tungsten.

In addition, the common lines CL are opaque and surround the pixel areas P1, P2... The common wires CL are electrically connected to the common electrodes 310, 320. A common voltage is applied to the common electrodes 310, 320... Through the common lines CL.

The common electrode CL interposed between the first gate line GL1 and the second gate line GL2 includes a plurality of sub common lines 101, 102... And a plurality of connection common lines 111. , 112 ...).

The sub common lines 101, 102... Extend in parallel with the first data line DL1, the second data line DL2, and the third data line DL3. The connection common lines 111 and 112... Respectively connect the sub common lines 101 and 102. The sub common wires 101, 102... And the connection common wires 111, 112... May be integrally formed with each other.

The first sub common wiring 101 and the second sub common wiring 102 define a first pixel region P1. In addition, the third sub common wiring 103 and the fourth sub common wiring 104 define a second pixel region P2. Similarly, the fourth sub common wiring 104 and the fifth sub common wiring 105 define a third pixel region P3.

In the same manner, the sixth sub common wiring 106 and the seventh sub common wiring 107 define the fourth pixel region P4, and the seventh sub common wiring 107 and the eighth sub common wiring 108. Defines a fifth pixel area P5. Similarly, the ninth sub common wiring 109 and the tenth sub common wiring 110 define a sixth pixel region P6.

In addition, the second sub common wiring 102 and the third sub common wiring 103 are disposed adjacent to the first data wiring DL1. In addition, the first data line DL1 is disposed between the second sub common line 102 and the third sub common line 103.

Similarly, the fifth sub common wiring 105 and the sixth sub common wiring 106 are disposed adjacent to the second data wiring DL2. In addition, the second data line DL2 is disposed between the fifth sub common line 105 and the sixth sub common line 106.

Similarly, the eighth sub common wiring 108 and the ninth sub common wiring 109 are disposed adjacent to the third data wiring DL3. The third data line DL3 is disposed between the eighth sub common line 108 and the ninth sub common line 109.

The thin film transistors TR1, TR2... Are disposed in an area where the gate lines GL1, GL2... And the data lines DL1, DL2. The thin film transistors TR1, TR2... Are driven by a gate signal applied from the gate lines GL1, GL2..., And are applied from the data lines DL1, DL2. A data signal is selectively applied to the pixel electrodes 210, 220, ..., respectively.

As illustrated in FIG. 2, the thin film transistors TR1 and TR2... Include the gate electrode 130, the semiconductor layer 150, the source electrode 160, and the drain electrode 170.

The gate electrode 130 is integrally formed with the gate lines GL1, GL2... That is, some of the gate lines GL1 and GL2... Correspond to the gate electrode 130. In more detail, a portion of the gate lines GL1 and GL2... Corresponding to the channel of the thin film transistors TR1 and TR2... Corresponds to the gate electrode 130.

The semiconductor layer 150 is disposed on the gate insulating layer 140. The semiconductor layer 150 corresponds to the gate electrode 130. The semiconductor layer 150 may include an active layer made of amorphous silicon and an ohmic contact layer made of amorphous silicon implanted with a high concentration of impurities.

The source electrode 160 extends from the data lines DL1, DL2... And is integrally formed with the data lines DL1, DL2. The source electrode 160 is disposed on the gate insulating layer 140.

The source electrode 160 is connected to the semiconductor layer 150. The source electrode 160 may be spaced apart from the drain electrode 170 and may have a shape surrounding the drain electrode 170.

The drain electrode 170 is connected to the semiconductor layer 150 and spaced apart from the source electrode 160. The drain electrode 170 is disposed on the gate insulating layer 140. The drain electrode 170 has an island shape. The drain electrode 170 is formed of the same material as the source electrode 160 and the data lines DL1, DL2.

The drain electrode 170 is connected to the pixel electrodes 210, 220. That is, the drain electrode 170 is electrically connected to the pixel electrodes 210, 220.

The TFT array substrate 10 may include a first thin film transistor TR1, a second thin film transistor TR2, a third thin film transistor TR3, a fourth thin film transistor TR4, a fifth thin film transistor TR5, and a sixth thin film transistor TR5. The thin film transistor TR6 may be included.

The first thin film transistor TR1 is disposed in a region where the first gate line GL1 and the first data line DL1 cross each other. In addition, the second thin film transistor TR2 is disposed in a region where the second gate line GL2 and the first data line DL1 cross each other.

The third thin film transistor TR3 is disposed in a region where the second gate line GL2 and the first data line DL1 cross each other. The fourth thin film transistor TR4 is disposed in a region where the first gate line GL1 and the second data line DL2 cross each other.

In addition, the fifth thin film transistor TR5 is disposed in an area where the second gate line GL2 and the third data line DL3 cross each other. The sixth thin film transistor TR6 is disposed in a region where the first gate line GL1 and the third data line DL3 cross each other.

The pixel electrodes 210, 220... Are disposed on the passivation layer 180 covering the data lines DL1, Dl2..., The source electrode 160, and the drain electrode 170.

The pixel electrodes 210, 220... Are connected to the thin film transistors TR1, TR2. In more detail, the pixel electrodes 210, 220... Are connected to the drain electrode 170 through the first contact hole 181 formed in the passivation layer 180. The pixel electrodes 210 and 220... Receive the data signal from the data lines DL1 and DL2... By driving the thin film transistors TR1 and TR2.

The pixel electrodes 210, 220... May be transparent or opaque. Examples of the material used as the pixel electrodes 210 and 220 may include indium tin oxide (ITO) or indium zinc oxide (IZO).

For example, the TFT array substrate 10 may include a first pixel electrode 210, a second pixel electrode 220, a third pixel electrode 230, a fourth pixel electrode 240, and a fifth pixel electrode 250. And a sixth pixel electrode 260.

The first pixel electrode 210 is connected to the first thin film transistor TR1. The first pixel electrode 210 includes a first main pixel electrode 211 and a plurality of first sub pixel electrodes 212.

As shown in FIGS. 2 and 3, the first main pixel electrode 211 is connected to the drain electrode 170 of the first thin film transistor TR1. The first main pixel electrode 211 overlaps the second sub common wiring 102. Accordingly, the first main pixel electrode 211 and the second sub common wiring 102 form a storage capacitance CST.

The first sub pixel electrodes 212 extend from the first main pixel electrode 211 to the first pixel region P1. Some of the first sub pixel electrodes 212 extend in a third direction, and other portions of the first sub pixel electrodes 212 extend in a fourth direction.

The second pixel electrode 220 is connected to the second thin film transistor TR2. The second pixel electrode 220 includes a second main pixel electrode 221 and a plurality of second sub pixel electrodes 222.

As shown in FIG. 4, the second main pixel electrode 221 is connected to the drain electrode 170 of the second thin film transistor TR2. The second main pixel electrode 221 partially overlaps the fourth sub common wiring 104. Accordingly, the second main pixel electrode 221 and the fourth sub common wiring 104 form a storage capacitance CST.

The second sub pixel electrodes 222 extend from the second main pixel electrode 221 to the second pixel area P2. A portion of the second sub pixel electrodes 222 extends in a third direction, and another portion of the second sub pixel electrodes 222 extends in the fourth direction.

The third pixel electrode 230 is connected to the third thin film transistor TR3. The third pixel electrode 230 includes a third main pixel electrode 231 and a plurality of third sub pixel electrodes 232.

The third main pixel electrode 231 is connected to the drain electrode 170 of the third thin film transistor TR3. The third main pixel electrode 231 overlaps the fifth sub common line 105. Accordingly, the third main pixel electrode 231 and the fifth sub common wiring 105 form a storage capacitance CST.

The third sub pixel electrodes 232 extend from the third main pixel electrode 231 to the third pixel region P3. A portion of the third sub pixel electrodes 232 extends in a third direction, and another portion of the third sub pixel electrodes 232 extends in the fourth direction.

The fourth pixel electrode 240, the fifth pixel electrode 250, and the sixth pixel electrode 260 are also disposed in a similar manner to the above.

The common electrodes 310, 320... Are disposed on the passivation layer 180. The common electrodes 310, 320... Are connected to the common wires CL. In more detail, the common electrodes 310, 320... Are connected to the common lines CL through second contact holes 182 formed in the passivation layer 180. The common electrodes 310, 320... Receive a common voltage through the common lines CL.

The common electrodes 310, 320... May be transparent or opaque. Examples of the material used as the common electrodes 310 and 320 may include indium tin oxide (ITO) or indium zinc oxide (IZO).

The TFT array substrate 10 includes a first common electrode 310, a second common electrode 320, a third common electrode 330, a fourth common electrode 340, a fifth common electrode 350, and a sixth. It may include a common electrode 360.

The first common electrode 310 is connected to the first sub common wiring 101. The first common electrode 310 includes a first main common electrode 311 and a plurality of first sub common electrodes 312.

The first main common electrode 311 overlaps the first sub common wiring 101 and is connected to the first sub common wiring 101.

The first sub common electrodes 312 extend from the first main common electrode 311 to the first pixel area P1. The first sub common electrodes 312 are alternately disposed with the first sub pixel electrodes 212. That is, the first sub common electrodes 312 are disposed between the first sub pixel electrodes 212, respectively.

A portion of the first sub common electrodes 312 extends in the third direction, and another portion of the first sub common electrodes 312 extends in the fourth direction.

The second common electrode 320 is connected to the third sub common wiring 103. The second common electrode 320 includes a second main common electrode 321 and a plurality of second sub common electrodes 322.

As illustrated in FIG. 3, the second main common electrode 321 overlaps the third sub common wiring 103 and is connected to the third sub common wiring 103.

The second sub common electrodes 322 extend from the second main common electrode 321 to the second pixel region P2. The second sub common electrodes 322 are alternately disposed with the second sub pixel electrodes 222. That is, the second sub common electrodes 322 are disposed between the second sub pixel electrodes 222, respectively.

A portion of the second sub common electrodes 322 extends in the third direction, and another portion extends in the fourth direction.

As shown in FIG. 4, the third common electrode 330 is connected to the fourth sub common wiring 104. The third common electrode 330 includes a third main common electrode 331 and a plurality of third sub common electrodes 332.

The third main common electrode 331 partially overlaps the fourth sub common wiring 104 and is connected to the fourth sub common wiring 104.

The third sub common electrodes 332 extend from the third main common electrode 331 to the third pixel region P3. The third sub common electrodes 332 are alternately disposed with the third sub pixel electrodes 232. That is, the third sub common electrodes 332 are disposed between the third sub pixel electrodes 232, respectively.

Some of the third sub common electrodes 332 extend in the third direction, and other portions extend in the fourth direction.

The fourth common electrode 340, the fifth common electrode 350, and the sixth common electrode 360 are also disposed similarly to the above.

The color filter substrate 20 faces the TFT array substrate 10. The color filter substrate 20 is disposed on the TFT array substrate 10. The color filter substrate 20 includes a black matrix pattern 21. In addition, the color filter substrate 20 may include a plurality of color filters.

The black matrix pattern 21 blocks light passing through the black matrix pattern 21. In addition, the black matrix pattern 21 includes a plurality of opening regions corresponding to the pixel regions P1, P2...

The liquid crystal layer 30 is interposed between the color filter substrate 20 and the TFT array substrate 10. The liquid crystal layer 30 is driven by an electric field formed between the pixel electrodes 210, 220... And the common electrodes 310, 320.

As described above, the pixel electrodes 210, 220... And the common electrodes 310, 320..., Based on the data lines DL1, DL2... Is placed. For example, the pixel electrodes 210, 220... May be disposed on the left side with respect to the data lines DL1, DL2... And the common electrodes 310, 320. ) May be placed on the right.

Accordingly, in the liquid crystal display according to the exemplary embodiment, the shape of the sub pixel electrodes 212, 222... And the sub common electrodes 312, 322. ) Can be designed identically. That is, since the main pixel electrodes 211, 221... And the main common electrodes 311, 321. The direction in which the electrodes 212, 222... And the sub common electrodes 312, 322... Can also be adjusted as desired.

Therefore, the liquid crystal display according to the exemplary embodiment has the same shape for each pixel region P1, P2...

Accordingly, as shown in FIGS. 5 and 6, even when the black matrix pattern is misaligned, the shapes of the pixel areas P1, P2..., Exposed through the opening areas are the same.

Therefore, the liquid crystal display according to the embodiment can reduce the deviation of each pixel area (P1, P2 ...), and can implement an improved image quality.

In addition, the features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

Although the above description has been made based on the embodiments, these are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains may not have been exemplified above without departing from the essential characteristics of the present embodiments. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a plan view showing a TFT array substrate.

FIG. 2 is a cross-sectional view taken along line AA ′ in FIG. 1.

FIG. 3 is a cross-sectional view taken along line BB ′ in FIG. 1.

4 is a cross-sectional view taken along line CC ′ in FIG. 1.

5 is a plan view showing a state in which a TFT array substrate and a black matrix pattern are normally aligned.

FIG. 6 is a plan view illustrating a state in which a TFT array substrate and a black matrix pattern are misaligned.

Claims (10)

A first gate wire extending in a first direction; A second gate line arranged in parallel with the first gate line; A data line crossing the first gate line and the second gate line; A first sub common wiring disposed adjacent to the data wiring and arranged in parallel with the data wiring; A second sub common wiring electrically connected to the first common wiring and adjacent to the data wiring and disposed in parallel with the data wiring; A first thin film transistor disposed in an area crossing the first gate line and the data line; A first main pixel electrode connected to the first thin film transistor and overlapping the first sub common line; And A second main common electrode overlapping the second common wiring and connected to the second sub common wiring; And the data line is disposed between the first sub common line and the second sub common line. The semiconductor device of claim 1, further comprising: third sub common wires extending from the first sub common wires and arranged in parallel with the first sub common wires to define the first sub common wires and a first pixel area; And And a first main common electrode overlapping the third sub common wiring and connected to the third sub common wiring. 3. The display device of claim 2, further comprising: a plurality of first sub pixel electrodes extending from the first main pixel electrode to the first pixel area; And And a plurality of first sub common electrodes extending from the first main common electrode to the first pixel area and disposed between the first sub pixel electrodes. 4. The display device of claim 3, wherein some of the first sub pixel electrodes and some of the first sub common electrodes extend in a third direction. The other portion of the first sub pixel electrodes and the other portion of the first sub common electrodes extend in a fourth direction. The semiconductor device of claim 1, further comprising: a fourth sub common wire extending from the second sub common wire and disposed in parallel with the second sub common wire to define the second sub common wire and a second pixel area; A second thin film transistor disposed in an area where the second gate line and the data line cross each other; And And a second main pixel electrode connected to the second thin film transistor and overlapping the fourth sub common line. The display device of claim 5, further comprising: a plurality of second sub pixel electrodes extending from the second main pixel electrode to the second pixel area; And And a plurality of second sub common electrodes extending from the second main common electrode to the second pixel area and disposed between the second sub pixel electrodes. The method of claim 6, wherein some of the second sub pixel electrodes and some of the second sub common electrodes extend in a third direction, The other part of the second sub pixel electrodes and the other part of the second sub common electrodes extend in a fourth direction. A first gate line and a second gate line extending in parallel with each other; First and second data wires crossing the first gate wire and the second gate wire; A first sub common line adjacent to the first data line and arranged in parallel with the first data line; A second sub common wiring disposed adjacent to the second data wiring and arranged in parallel with the second data wiring; Interposed between the first sub common wiring and the second sub common wiring, connected to the first sub common wiring and the second sub common wiring, and defining the first sub common wiring and a first pixel area, A third sub common wire defining the second sub common wire and a second pixel area; A first thin film transistor disposed in a region where the first gate line and the first data line cross each other; A first main pixel electrode connected to the first thin film transistor and partially overlapping the third common electrode; And And a second main common electrode connected to the third common electrode, spaced apart from the first main pixel electrode, and partially overlapping the third common electrode. The display device of claim 8, further comprising: a first main common electrode connected to the first sub common line and overlapping the first sub common line; A plurality of first sub common electrodes extending from the first main common electrode to the first pixel area; And And a plurality of first sub pixel electrodes extending from the first main pixel electrode to the first pixel area. 10. The display device of claim 8, further comprising a black matrix pattern including a first opening region corresponding to the first pixel region and a second opening region corresponding to the second pixel region, and disposed on the first main pixel electrode. Display.

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