KR20120133256A - Back junction solar cell and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A back junction solar cell and a manufacturing method thereof are provided to improve efficiency by minimizing damage to a wafer backside. CONSTITUTION: An oxide layer is formed on a rear surface of a wafer(S100). A first doped region is formed by removing a part of the oxide layer(S110). A first conductivity type semiconductor layer is doped on the formed first doped region(S120). A second doped region is formed by removing the rest of the oxide layer(S130). The second conductivity type semiconductor layer is doped on the formed second doped region(S140). [Reference numerals] (S100) Forming an oxide layer on a rear surface of a wafer; (S110) Forming a first doped region; (S120) Doping a first conductivity type semiconductor layer; (S130) Forming a second doped region; (S140) Doping a second conductivity type semiconductor layer

Description

BACK JUNCTION SOLAR CELL AND MANUFACTURING METHOD THEREOF}

The disclosed technology relates to a back-junction solar cell and a method of manufacturing the same, and more particularly, to a back-junction solar cell and a method of manufacturing the same that can improve efficiency by minimizing damage to a wafer.

Electrodes of the solar cell are generally formed on the front and rear of the wafer, respectively, but the electrodes provided on the front of the wafer interfere with the absorption of sunlight and cause a decrease in the efficiency of the solar cell. Thus, in order to improve the efficiency of the solar cell, a solar cell having a back junction structure has been developed in which the area of the electrode formed on the front surface of the wafer is narrowed to a fine pattern as much as possible or all the electrodes are positioned on the rear side of the wafer. A back junction solar cell refers to a structure in which both a base junction collecting p-type (or n-type) charges and an emitter junction collecting n-type (or p-type) charges are located on the back side of the wafer.

However, the conventional back junction solar cell is a part of the wafer in order to deposit the impurities of n + or p +, which causes a decrease in the efficiency of the solar cell.

Among the embodiments, the back-junction solar cell manufacturing method comprises the steps of forming an oxide layer on the back of the wafer and by sequentially doping the first conductive semiconductor layer and the second conductive semiconductor layer while removing a portion of the oxide layer And forming a back junction layer on the wafer. In another embodiment, the forming of the back junction layer may include forming a first doped region by removing a portion of the oxide layer, and doping the first conductive semiconductor layer in the formed first doped region; Removing the remainder of the oxide layer to form a second doped region and doping the second conductive semiconductor layer to the formed second doped region. In addition, the back-junction solar cell is doped to a portion other than a portion where the first conductive semiconductor layer and the first conductive semiconductor layer doped to a specific portion of the wafer and the back surface of the wafer and the first conductive semiconductor layer And a back junction layer comprising a second conductivity-type semiconductor layer doped on the same plane.

1 is a view showing a back-junction solar cell manufacturing method according to the disclosed technology.
Figure 2 is a view showing the configuration of each step of the back-junction solar cell manufacturing method shown in FIG.

Description of the present application is only an embodiment for structural or functional description, the scope of the disclosed technology should not be construed as limited by the embodiments described in the text. That is, the embodiments may be variously modified and may have various forms, and thus, the scope of the disclosed technology should be understood to include equivalents capable of realizing the technical idea.

Meanwhile, the meaning of the terms described in the present application should be understood as follows.

The terms "first "," second ", and the like are intended to distinguish one element from another, and the scope of the right should not be limited by these terms. For example, a first component may be named a second component, and similarly, a second component may also be named a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that the other component does not exist. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosed technology belongs, unless otherwise defined. Generally, the terms defined in the dictionary used are to be interpreted as being consistent with the meaning in the context of the related art, and should not be interpreted as having ideal or excessively formal meanings unless clearly defined in the present application.

1 is a view showing a back-junction solar cell manufacturing method according to the disclosed technology, Figure 2 is a view showing the configuration of each step of the back-junction solar cell manufacturing method shown in FIG.

Referring to FIGS. 1 and 2, in the method of manufacturing a back junction solar cell, a step of forming an oxide layer 20 on a rear surface of a wafer 10 (S100) and removing a portion of the oxide layer 20 may be performed. And sequentially doping the conductive semiconductor layer 30 and the second conductive semiconductor layer 40 to form a back junction layer on the wafer.

The forming of the oxide layer 20 on the back of the wafer 10 is performed by mounting the textured wafer 10 inside the diffusion path and depositing an oxide film on the surface of the wafer 10. Can be. Since the back junction solar cell diffuses p-type and n-type impurities onto the back surface of the silicon wafer to form a back junction layer, the oxide layer 20 is deposited in advance on the region to which the impurities are to be doped (Fig. 2 (b)). Reference).

The step of forming the back junction layer is a step of depositing and depositing p-type and n-type impurities on the back surface of the silicon wafer. The conductive semiconductor layer is sequentially doped. In more detail, forming the back junction layer may include forming a first doped region 35 by removing a portion of the oxide layer 20 (S110), and forming a first conductive type in the first doped region 35. Doping the semiconductor layer 30 (S120), removing the remainder of the oxide layer 10 to form the second doped region 45 (S130) and the second conductive region in the second doped region 45 It may be configured to include a step (S140) doping the type semiconductor layer 40.

Forming the first doped region 35 (S110) is an oxide layer of a portion where the first conductivity-type semiconductor layer 30 is to be deposited as a portion of the oxide layer 20 deposited on the backside of the wafer 10 described above. Is selectively removed (see FIG. 2 (c)). The oxide layer 20 may be removed using a liquid obtained by mixing hydrofluoric acid (HF) or hydrofluoric acid with nitric acid (HNO ₃ ) in a predetermined ratio. The first conductive semiconductor 30 is doped into the first doped region 35 formed as described above (see FIG. 2 (d)).

Doping the first conductive semiconductor layer 30 (S110) refers to doping n + or p + into the formed first doped region 35. The deposition of the first conductive semiconductor layer 30 on the wafer 10 may be performed in a high temperature diffusion furnace, such as ion shower doping or plasma ion implantation (PIII). Various known methods can be used.

Forming the second doped region 45 (S130) refers to removing the oxide layer 20 of the remaining portion except for the portion doped with the first conductivity type semiconductor layer. When the step S130 of forming the second doped region is completed, the first conductive semiconductor layer 30 is deposited on the back surface of the wafer, and the above-described oxide film layer (3) is interposed between the first conductive semiconductor layer 30. The part from which 20) has been removed remains a space (see Fig. 2 (e)). Since the method of removing the oxide layer to form the second doped region has been described above, it will be omitted.

Doping the second conductive semiconductor layer 40 (S140) refers to doping the second conductive semiconductor layer 40 in the formed second doped region 45. The second conductivity-type semiconductor layer 40 becomes p + when the first conductivity-type semiconductor layer 30 is n + and n + when the first conductivity-type semiconductor layer 30 is p +.

As described above, when the oxide layer 10 formed on the rear surface of the wafer is sequentially removed, the doped first conductive semiconductor layer 30 and the second conductive semiconductor layer 40 are sequentially doped. As shown in FIG. 1, the first conductive semiconductor layer 30 and the second conductive semiconductor layer 40 are doped on the rear surface of the wafer in the same plane. Therefore, by etching the wafer 10 as in the prior art it is possible to prevent or minimize the damage to the wafer.

The disclosed technique may have the following effects. It is to be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, as it is not meant to imply that a particular embodiment should include all of the following effects or only the following effects.

A back junction solar cell and a method of manufacturing the same according to an embodiment may deposit a conductive semiconductor layer with minimal damage to the back surface of the wafer.

Although described above with reference to the preferred embodiment of the present application, those skilled in the art will be variously modified and changed within the scope of the present application without departing from the spirit and scope of the present application described in the claims below I can understand that you can.

10: wafer
20: oxide layer
30: first conductivity type semiconductor layer
35: first doped region
40: second conductivity type semiconductor layer
45: second doped region

Claims (3)

Forming an oxide layer on the back side of the wafer; And
And sequentially doping the first conductive semiconductor layer and the second conductive semiconductor layer while removing a portion of the oxide layer to form a back junction layer on the wafer. The method of claim 1, wherein the forming of the back junction layer is performed.
Removing a portion of the oxide layer to form a first doped region;
Doping the first conductive semiconductor layer into the formed first doped region;
Removing the remainder of the oxide layer to form a second doped region; And
And doping the second conductive semiconductor layer in the formed second doped region. wafer; And
A second doped portion except for the first conductive semiconductor layer doped to a specific portion of the back surface of the wafer and the portion where the first conductive semiconductor layer is formed and doped on the same plane as the first conductive semiconductor layer A back junction solar cell comprising a back junction layer comprising a conductive semiconductor layer.

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