KR101093114B1 - Back junction solar cells - Google Patents

Abstract

The present invention relates to a solar cell of the back junction structure. According to the present invention, when a doping of the impurity is performed by plasma doping on the back surface of the silicon wafer 100 in which the saw damage process is completed, a p + layer 102 having a shallower junction depth than the conventional method is formed. The diffusion barrier layer 104 is formed on the p + layer 102. Then, when etching is performed on the portion where the diffusion barrier layer 104 is not formed (that is, the portion where the n + layer is to be formed), the surface of the silicon wafer 100 is etched to a predetermined depth. The n + layer 106 is formed by doping impurities on the surface of the etched silicon wafer 100 by the plasma doping method. Thereafter, the diffusion barrier layer 104 is removed, the surface thereof is cleaned, and a thermal oxide layer 108 is formed on the front and rear surfaces of the silicon wafer 100 to manufacture a rear surface of the solar cell. According to the present invention, the p + layer and the n + layer is formed using two plasma doping techniques, thereby reducing the manufacturing process and cost.

Back Junction, Solar Cell, Plasma Doping, Emitter Junction, Base Junction

Description

Back junction solar cells

The present invention relates to a solar cell, and in particular, to manufacture a solar cell having a back junction structure, to reduce the number of manufacturing process and to lower the process temperature.

The electrodes of the solar cell are formed on the front and rear surfaces of the solar cell, respectively, but the electrodes formed on the front face reduce the shadowing loss to sunlight.

Therefore, in order to improve the efficiency of solar cells, the general trend is to narrow the area of the electrode formed on the front surface to have a fine pattern as much as possible. However, even in this case, sunlight does not absorb as much as the electrode area formed on the front surface.

Therefore, in order to fundamentally eliminate the reduction of absorption by the electrode at the front of the solar cell, a solar cell having a back junction structure in which both electrodes are installed at the rear has been developed. That is, the solar cell of the back junction structure includes a base junction and an n-type (or p-type) that collects p-type (or n-type) charges on the back surface opposite to the front surface where light is incident on the p-type (or n-type) silicon substrate. ) Is the structure where all the emitter junctions that collect charges are located.

Such a back junction solar cell is expected to improve efficiency by improving the absorption of solar light, but the manufacturing process was complicated and costly disadvantages. This can be said to be the cause of limiting the commercialization of the solar cell of the back junction structure.

Therefore, a solar cell having a back junction structure has been proposed to simplify the process and reduce the manufacturing cost. An example thereof is disclosed in US Patent No. US 07339110 (a solar cell and its manufacturing method, hereinafter referred to as a prior patent).

Here, the process of forming the base region and the emitter region on the back surface of the p-type silicon wafer in the manufacturing process of the prior patent will be described.

First, a p + layer is formed on one side (i.e., the opposite side to which sunlight is incident) of the p-type silicon wafer where the saw damage etching process is completed (step 1), and a thermal oxide film is formed thereon (step 2). .

Then, an etch resist is printed on a portion of the thermal oxide film, that is, a portion except for the portion where the n + layer is to be formed in a subsequent process (step 3).

Thereafter, the thermal oxide film formed on the portion where the etch resist is not printed is etched (step 4), the etch resist is removed (step 5), and the surface of the silicon wafer is etched to a predetermined depth (step 6). In this case, the etching depth may be larger than the junction depth of the p + layer. In the above patent, it is illustrated as 3㎛.

When the etching process is completed, the back surface of the silicon wafer is cleaned with a cleaning liquid (step 7).

Then, an n + layer is formed on the surface of the etched silicon wafer by using a liquid dopant source such as' POCl ₃ (phosphorus oxychloride), a doping element of the p-type silicon wafer (step 8). Of course, when the n-type silicon wafer and p + layer to form a liquid dopant source such as 'BB _r3 ' is used.

As such, in the prior patent, the process of jointly forming a base region for collecting charges of the same conductivity type as that of the silicon wafer and an emitter region for collecting charges of another conductivity type on the rear surface of the silicon wafer in eight steps. It is done.

In addition, the process of doping the p-type and n-type impurities in the prior patent and the process of forming a thermal oxide film is carried out in a high temperature diffusion furnace, it is carried out at a high temperature of about 900 ℃. In other words, two diffusion processes and one thermal oxide film formation step were necessary at high temperatures.

In general, if the process temperature can be lowered while maintaining the efficiency in the solar cell process, this can help to reduce costs and simplify the process.

However, as described above, when the base region and the emitter region are formed on the back surface of the silicon wafer, the process is performed at a high temperature of 900 ° C. or higher, and the situation is not lowered to a process temperature below that. In addition, since the process is performed at a high temperature of more than 900 ℃ it was difficult to reduce the current number of processes.

As a result, the prior patent has a substantial problem that it is difficult to sufficiently reduce the manufacturing cost of the solar cell because the energy input amount is increased and the process time is long when manufacturing the solar cell of the back junction structure.

Accordingly, an object of the present invention is to solve the above problems, and when the base region and the emitter region are formed on the solar cell rear surface of the back junction structure, it is to lower the manufacturing process temperature.

Another object of the present invention is to form a base region and an emitter region on a solar cell rear surface of a back junction structure according to a more simplified manufacturing process.

According to a feature of the present invention for achieving the above object, a first doped region formed on a portion of the back surface of the semiconductor substrate; And a second doped region formed on a portion of the back surface of the semiconductor substrate where the first doped region is not formed, the second doped region being different from the first doped region, and the height of the first doped region and the second doped region. The difference is formed smaller than the junction depth of the first doped region or the junction depth of the second doped region to be finally formed.

The first doped region and the second doped region are formed by implanting impurity ions into a surface of the semiconductor substrate while the semiconductor substrate is exposed to a plasma containing impurity ions.

The first doped region and the second doped region are formed by an 'ion shower doping' or a 'plasmon ion implantation (PIII)' method.

Activation and diffusion of the impurity ions are performed simultaneously in the process of forming a thermal oxide film on the first doped region and the second doped region, and the junction depth of the first doped region and the second doped region is the impurity ion. It is formed larger than the injected depth.

In the present invention, in the case of forming the emitter region and the base region by diffusing p-type and n-type impurities on the back surface of the silicon wafer in the solar cell of the back junction structure, plasma such as ion shower doping or plasma ion implantation (PIII) method Since it is formed by applying the doping technique, the conventional high temperature process of about 900 ℃ does not need to be performed.

Therefore, the present invention does not require time to raise and lower the temperature and can reduce the energy input during the manufacturing process.

In addition, the number of processes for forming the emitter region and the base region on the back surface of the silicon wafer is reduced compared with the prior art. That is, the conventional eight-step process is reduced to six steps, such as p + layer formation, diffusion barrier formation, silicon wafer etching, n + layer formation, diffusion barrier removal, and cleaning.

In addition, when impurities are diffused on the back surface of the silicon wafer by a plasma doping technique, a thin junction may be formed, so that the etching depth may be etched thinner than in the conventional etching process.

As such, the present invention simplifies the overall manufacturing process, and can reduce the cost required for this, and thus can expect a competitive advantage.

Hereinafter, a preferred embodiment of the solar cell of the back junction structure of the present invention will be described in detail with reference to the accompanying drawings.

In the embodiment of the present invention, for convenience of description, a solar cell having a back junction structure is manufactured using a p-type silicon wafer. In addition, the silicon wafer has a specific resistance of about 1 Ωcm and a thickness of about 150 to 200 μm. However, the specific resistance and thickness do not have to be limited as described above.

1 is a flowchart of a method for manufacturing a solar cell of a back junction structure according to a preferred embodiment of the present invention.

Referring to FIG. 1, first, an etching process for improving the mechanical strength of a silicon wafer is performed by removing saw damage of a silicon surface damaged during the cutting of the silicon wafer (S100). The etching process is to remove the cutting damage by etching the surface of the silicon wafer about 10㎛ with an acid solution containing hydrofluoric acid and nitric acid or an alkaline solution containing potassium hydroxide, sodium hydroxide and the like. When the etching process is completed, the metal or organic material that may be on the surface of the silicon wafer is cleaned using hydrochloric acid or the like.

When the etching process is completed, a p + layer is formed on the back surface of the silicon wafer (ie, the opposite surface to which sunlight is incident) (S102). The p + layer is formed by 'ion shower doping' or 'Plasma Immersion Ion Implantation' (PIII). This is a method of forming a p + layer on only one side of the silicon wafer. 'Ion shower doping' and 'PIII' expose the silicon wafer to a plasma containing impurity ions so that impurity ions are implanted on the surface of the silicon wafer. Is using. Therefore, the high temperature process, which is conventionally performed when doping impurities into a silicon wafer, is not necessary. Accordingly, the present embodiment can form a p + layer without heating the silicon wafer. In particular, by using the method, a thin junction can be formed on the surface of the silicon wafer. The junction thickness is formed to be thinner than the p + layer thickness formed when conventionally formed by doping with impurities at high temperature. Therefore, the etching depth can be further reduced in the subsequent etching process, thereby reducing the process time and cost.

After the p + layer is formed, a diffusion mask is formed on a portion of the p + layer 101, that is, a portion except for the portion where the n + layer is to be formed (s104). The diffusion barrier is coated with a diffusion barrier paste by screen printing.

When the diffusion barrier is formed, the surface of the silicon wafer in the portion where the diffusion barrier is not formed is etched to a predetermined depth (s106). In this case, the etching depth may be larger than the junction depth of the p + layer. For reference, the impurity implantation depth generally does not exceed 0.1 μm when the 'PIII' is used. Here, the etching method is a wet etching and dry etching. The wet etching uses an alkaline solution so that the diffusion barrier can be used as an etch barrier. If the p + layer is formed of boron (B), a thin oxide film (BSG, Boro-Silicate Glass) may be formed on the surface of the silicon wafer so that the oxide film (BSG) is removed by a hydrofluoric acid solution of a certain concentration. After etching. Dry etching, another etching method, is appropriately applied to process variables such as the type and flow rate of the gas used in the etching process and the pressure of the reaction chamber within the range of the general dry etching process technology used for the manufacture of semiconductors or display devices. To perform.

When the etch process is complete, and using the (POCl ₃₎ phosphorus oxychloride to the surface of the etched silicon wafer form an n + layer (s108). The n + layer is also formed by 'ion shower doping' and 'PIII'.

After the n + layer is formed, the diffusion barrier layer is removed (s110), and the back surface of the silicon wafer is cleaned with a cleaning solution (s112).

Thereafter, a thermal oxide film is formed on the back and front surfaces of the silicon wafer using a dry or wet oxidation process used in a semiconductor manufacturing process (s114). Then, dopant ions doped on the back surface of the silicon wafer are activated and diffusion is simultaneously performed to form n + and p + type junctions on the back surface of the silicon wafer. In this case, the junction depth becomes larger than the impurity implantation depth.

The above process will be described in detail with reference to FIG. 2. 2 is a cross-sectional view illustrating a process of manufacturing a solar cell of a back junction structure according to an embodiment of the present invention.

FIG. 2 (a) shows the silicon wafer 100 having a saw damage etching process and a surface of which has been cleaned with a cleaning liquid.

The p + layer 102 is formed on the rear surface of the silicon aper 100 as shown in FIG. At this time, the p + layer 102 is formed by the 'ion shower doping' or 'plasma ion implantation (PIII) method, so the p + layer 102 is a junction formed by a diffusion process in a conventional high temperature diffusion furnace It is formed in the form of a shallow junction (thinner junction) than the thickness.

When the p + layer 102 is formed, a diffusion mask 104 is formed as shown in FIG.

When the diffusion barrier layer 104 is formed, the surface A of the silicon wafer 100 on which the n + layer is to be formed is etched to a predetermined depth. This is shown in Figure 2 (d). In this case, since the junction of the p + layer 102 is formed as a shallow junction, the depth of etching the surface of the silicon wafer 100 can be reduced compared to the prior art.

In FIG. 2E, the n + layer 106 is formed on the surface A of the etched silicon wafer 100. In this case, the n + layer 106 is also formed by 'ion shower doping' and 'PIII'.

Thereafter, when the n + layer 106 is formed, the diffusion barrier film 104 is removed and the surface of the silicon wafer 100 is cleaned with a cleaning liquid. The silicon wafer in the cleaned state is shown in FIG. 2 (f). In this case, the thicknesses of the p + layer 102 and the n + layer 106 are indicated as 'd' in the drawing.

Then, the thermal oxide film 108 is formed on the rear and front surfaces of the silicon wafer 100 in the subsequent thermal oxide film forming process of FIG. At this time, activation and diffusion of the impurity ions doped in the silicon wafer 100 are performed. If so, the p + layer 102 and n + layer 106 will have a larger junction depth. That is, in FIG. 2 (f), the junction depth of the p + layer 102 and the n + layer 106 is 'd', but when the thermal oxide film 108 forming process of FIG. 2 (g) is completed, the p + layer 102 and n + The junction depth of layer 104 becomes larger, such as d '.

When such a thermal oxide film 108 is formed, a general process for manufacturing a solar cell is sequentially performed to complete the solar cell.

As described above, the present invention forms a base region and an emitter on the rear surface of the silicon wafer by applying two plasma doping techniques without heating the silicon wafer.

The rights of the present invention are not limited to the embodiments described above, but are defined by the claims, and those skilled in the art can make various modifications and adaptations within the scope of the claims. It is self-evident.

That is, in the present embodiment, a p-type silicon wafer is described as an example, but the present invention can be applied to an n-type silicon wafer.

1 is a flow chart of a solar cell manufacturing method of the back junction structure according to an embodiment of the present invention.

2 is a cross-sectional view showing a solar cell manufacturing process of FIG.

Explanation of symbols on the main parts of the drawings

100: etched p-type silicon wafer 102: p + layer

104: diffusion barrier 106: n + layer

108: thermal oxide film

Claims (4)

A first doped region formed on a portion of the back surface of the semiconductor substrate; And, A second doped region formed on a portion of the back surface of the semiconductor substrate where the first doped region is not formed, the second doped region being different from the first doped region; The height difference between the first doped region and the second doped region is a solar cell of the back junction structure, characterized in that formed less than the junction depth of the first doped region or the second doped region formed. The method of claim 1, The first doped region and the second doped region, A solar cell having a back junction structure, wherein the semiconductor substrate is formed by implanting impurity ions into a surface of the semiconductor substrate when the semiconductor substrate is exposed to a plasma including impurity ions. 3. The method of claim 2, The first doped region and the second doped region, the solar cell of the back junction structure, characterized in that formed by the 'ion shower doping (ion shower doping) or' plasmon ion implantation (PIII) method. 3. The method of claim 2, Activation and diffusion for the impurity ions, In the process of forming a thermal oxide film on the first doped region and the second doped region at the same time, the junction depth of the first doped region and the second doped region is characterized in that formed larger than the depth implanted with the impurity ions Solar cell with back junction structure.

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