KR20120111364A - Light emitting device and light emitting device package - Google Patents

Abstract

PURPOSE: A light emitting device and a light emitting device package are provided to prevent defects due to lattice mismatch by arranging a dislocation blocking layer between a first semiconductor layer and a second conductive semiconductor layer. CONSTITUTION: A first AlInN layer and a second AlInN layer are alternatively laminated on a dislocation blocking layer(130). The second AlInN layer has compressive stress. A second conductive semiconductor layer(140) is formed on the dislocation blocking layer. An active layer(150) is formed on the second conductive semiconductor layer. A third conductive semiconductor layer(160) is formed on the active layer.

Description

LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE}

Embodiments relate to a light emitting device and a light emitting device package.

LIGHT EMITTING DEVICE (LED) is a kind of semiconductor device that converts electrical energy into light. The light emitting device has advantages of low power consumption, semi-permanent life, fast response speed, safety, and environmental friendliness compared to conventional light sources such as fluorescent lamps and incandescent lamps.

Accordingly, many researches are being conducted to replace the existing light sources with light emitting devices, and the use of light emitting devices as light sources for lighting devices such as lamps, liquid crystal displays, electronic signs, and street lamps, which are used indoors and outdoors, is increasing. to be.

In general, the light emitting device has a structure in which a nitride semiconductor is grown on a sapphire substrate to emit light. Sapphire, SiC, Si, GaN and the like are used as the substrate, and a method of giving a pattern to the substrate is generally used to improve light extraction efficiency.

In the case of using a substrate on which such a pattern is formed, the light extraction effect can be improved, but a problem arises in that dislocations are concentrated on top of the pattern. These dislocations proceed to the active layer as they are, and the defects generated thereby adversely affect the electrostatic dischage (ESD) characteristics. Therefore, it is necessary to block the electric potentials rising to the top of the substrate.

The embodiment provides a light emitting device and a light emitting device package having a new structure.

In addition, the embodiment provides a light emitting device and a light emitting device package for improving the crystallinity of the nitride semiconductor formed on a substrate having a plurality of patterns.

An embodiment includes a first semiconductor layer; A potential blocking layer in which a first AlInN layer having a tensile stress and a second AlInN layer having a compressive stress are alternately stacked on the first semiconductor layer; A second conductivity type semiconductor layer on the potential blocking layer; An active layer on the second conductivity type semiconductor layer; And it provides a light emitting device comprising a third conductive semiconductor layer on the active layer.

Embodiments can improve dislocations and defects due to lattice mismatch on a patterned sapphire substrate (PSS) substrate.

In addition, the embodiment can improve the reliability and crystallinity of the light emitting device.

Meanwhile, various other effects will be directly or implicitly disclosed in the detailed description according to the embodiment of the present invention to be described later.

1 is a cross-sectional view of a horizontal light emitting device according to the embodiment;
2 is a view showing in detail an example of a potential blocking layer according to the embodiment;
3 is a view showing changes in physical properties according to the composition ratio of the AlInN material according to the embodiment;
4 to 7 illustrate a method of manufacturing a horizontal light emitting device according to the embodiment;
8 is a cross-sectional view of a vertical light emitting device according to the embodiment;
9 is a cross-sectional view of a light emitting device package including a light emitting device according to the embodiment;
10 is a view illustrating a backlight unit including a light emitting device or a light emitting device package according to an embodiment;
11 is a view illustrating a lighting unit including a light emitting device or a light emitting device package according to an embodiment.

In the following description of the embodiments, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

In addition, in the description of the embodiments, each layer (film), region, pattern, or structure may be "top" or "down / down" of the substrate, each layer (film), region, pad, or pattern. under) " includes all that are formed directly or through another layer. Criteria for the top / bottom or bottom / bottom of each layer will be described with reference to the drawings.

The thickness or the size of each layer (film), region, pattern or structure in the drawings may be modified for clarity and convenience of explanation, and thus does not entirely reflect the actual size.

Hereinafter, a light emitting device, a light emitting device manufacturing method, a light emitting device package, and an illumination system according to embodiments will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a horizontal light emitting device according to an embodiment.

The light emitting device 100 according to the embodiment includes a substrate 110, a first semiconductor layer 120 formed on the substrate 110, a potential blocking layer 130 formed on the first semiconductor layer 120, and the The light emitting structure 165 formed on the potential blocking layer 130, the light transmitting electrode layer 170 formed on the light emitting structure 165, and the first and second electrodes 180 and 190 are included.

The light emitting structure 165 includes a second conductive semiconductor layer 140, an active layer 150, and a third conductive semiconductor layer 160, and the second conductive semiconductor layer 140 and the third conductive layer. Electrons and holes provided from the type semiconductor layer 160 may be recombined in the active layer 150 to generate light.

The substrate 110 may be an insulating substrate, a conductive substrate, a semiconductor substrate, and the like, for example, in the group consisting of sapphire substrate (Al ₂ 0 ₃ ), GaN, SiC, ZnO, Si, GaP, InP, GaAs, and the like. Can be selected.

A plurality of patterns 105 may be formed on the substrate 110. The plurality of patterns 105 may be formed by an etching process of the substrate 110 or may be formed in a lens pattern with a separate material. In the following embodiment, the substrate 110 will be described on the assumption that it is a patterned sapphire substrate (hereinafter, referred to as a 'PSS') having a plurality of patterns 105.

The plurality of patterns 105 of the substrate 110 may be formed at regular intervals, at irregular intervals, or at random intervals, and the shapes of the patterns 105 may be formed of convex lenses, stripes, and polygonal shapes. The interval of the pattern 105 may be formed in the range of several nm to several μm, for example, 1 to 1.5 μm, and the width and the height thereof are in the range of several nm to several μm, for example, 3 μm in height and 2 μm in width. The first semiconductor layer 120 formed on the substrate 110 includes at least one semiconductor layer of a first conductivity type semiconductor layer and an undoped semiconductor layer.

For example, in the exemplary embodiment of the present invention, a first conductive semiconductor layer or an undoped semiconductor layer is formed below the potential blocking layer 130. However, the first conductivity type semiconductor layer may be formed under the potential blocking layer 130, and an undoped semiconductor layer may be formed under the potential blocking layer 130.

The first conductive semiconductor layer may include a compound semiconductor of a group III-V element doped with an n-type dopant. Such a first conductivity type semiconductor layer is a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1), for example InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN and the like may be selected, and n-type dopants such as Si, Ge, Sn, and the like may be doped. Here, the doping concentration of the first conductivity type semiconductor layer is preferably lower than the doping concentration of the second conductivity type semiconductor layer 140.

Although the undoped semiconductor layer is not intentionally implanted with n-type impurities, the undoped semiconductor layer may have a n-type conductivity, for example, the undoped semiconductor layer may be formed of Undoped-GaN.

Meanwhile, a buffer layer (not shown) may be formed between the substrate 110 and the first semiconductor layer 120 to mitigate lattice mismatch due to a lattice constant difference. On the first semiconductor layer 120, a buffer layer may be formed. A potential blocking layer 130 having a super lattice structure may be formed.

The potential blocking layer 130 plays a role of flattening or terminating the dislocations generated in the pattern portion of the substrate 110 toward the light emitting structure 165. .

The potential blocking layer 130 may be formed by repeatedly stacking a plurality of layers made of AlInN material. Here, since the AlInN material serves as a high resistance layer and can achieve lattice matching with the nitride semiconductor layer 120, the AlInN material effectively prevents potentials rising from the substrate 110 without generating a new defect due to the AlInN material. You can block.

In addition, since the AlInN material can control its physical properties by changing the composition of aluminum and indium, it can block the progress of dislocation by using the AlInN material. For example, the AlInN material may be adjusted to increase its aluminum composition ratio so that its physical properties have a tensile stress, or may increase its indium composition ratio to adjust its physical properties to have a compressive stress.

2 is a diagram illustrating an example of a potential blocking layer according to an exemplary embodiment.

Referring to FIG. 2, the potential blocking layer 130 has a structure in which a first AlInN layer and a second AlInN layer having different composition ratios of aluminum (Al) and indium (In) are repeatedly stacked.

For example, the first AlInN layer may be made of an AlInN material having a composition ratio of aluminum and indium of 9: 1, and the second AlInN layer may be made of an AlInN material having a composition ratio of 7: 3 of aluminum and indium. Due to the different composition ratio of the dislocation blocking layer 130, the first AlInN layer may have a tensile stress, and the second AlInN layer may have a compressive stress. In addition, the potential blocking layer 130 may include the second AlInN layer instead of the first AlInN layer.

By forming the super lattice layer having different kinds of stresses as described above, the potential blocking layer 130 may provide a higher potential blocking effect than the potential blocking layer made of AlInN material having a uniform composition ratio.

Meanwhile, it will be apparent to those skilled in the art that the composition ratio of the potential blocking layer illustrated in FIG. 2 is merely an example, and the first AlInN layer and the second AlInN layer may have different composition ratios.

For example, FIG. 3 is a view showing a change in physical properties according to the composition ratio of the AlInN material according to the embodiment. Referring to FIG. 3, when the indium composition ratio of the AlInN material is 18% to 22%, it can be seen that the AlInN material having such a composition ratio is lattice matched with gallium nitride (GaN). That is, at point C of FIG. 3, the AlInN material comprises 18% to 22% indium and 78% to 92% aluminum. In addition, the AlInN material having such a composition ratio may have a lattice constant similar to that of gallium nitride (GaN).

Based on point C of FIG. 3, when the composition of aluminum is increased, the AlInN material may have a tensile stress, and when the composition of aluminum is decreased, the AlInN material may have a compressive stress. . That is, when the composition ratio of aluminum and indium is 8: 2, the AlInN material formed between the gallium nitride layers 120 and 140 may have different physical properties according to the composition change of the aluminum and indium. .

Meanwhile, at the point A of FIG. 3, the AlInN material continues to increase in composition of aluminum, resulting in an AlN material including only aluminum without including indium. On the other hand, at point B of FIG. 3, the AlInN material continues to decrease in composition of aluminum, resulting in an InN material containing only indium and not containing aluminum.

As such, as shown in FIG. 3, when the aluminum composition of the AlInN material is greater than 80% and less than 100% and the indium composition is greater than 0% and less than 20%, that is, Al _x In _(1-x) N (0.8 When <x <1), the AlInN material formed between the gallium nitride layers 120 and 140 may be subjected to tensile stress.

And when the aluminum composition of the AlInN material is greater than 0% and less than 80% and the indium composition is greater than 20% and less than 100%, that is, Al _x In _(1-x) N (0 <x <0.8) In this case, the AlInN material formed on the gallium nitride layers 120 and 140 may be subjected to compressive stress.

Therefore, a first AlInN layer having a composition ratio of Al _x In _(1-x) N (0.8 <x <1) and a composition having a composition ratio of Al _x In _(1-x) N (0 <x <0.8) The dislocation blocking layer 130 repeatedly stacking 2 AlInN layers may improve electrostatic dischage (ESD) characteristics by minimizing dislocations generated in the substrate 110 and propagating toward the light emitting structure 165.

Referring back to FIG. 1, a second conductivity type semiconductor layer 140 may be formed on the potential blocking layer 130.

The second conductive semiconductor layer 140 may include a compound semiconductor of a group III-V element doped with an n-type dopant. The first semiconductor material having a composition formula of a second conductivity type semiconductor layer 140 is Al _x In _y Ga _{1 -x-} N _y (0≤x≤1, 0≤y≤1, 0≤x + y≤1), For example, it may be selected from InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN, and the like, and an n-type dopant such as Si, Ge, Sn, or the like may be doped. Here, the doping concentration of the second conductive semiconductor layer 140 is preferably higher than the doping concentration of the first semiconductor layer 120.

The second conductivity type semiconductor layer 140 may be formed as a single layer or a multilayer, but is not limited thereto.

In the active layer 150, electrons injected through the second conductivity type semiconductor layer 140 and holes injected through the third conductivity type semiconductor layer 160 meet each other to form a material of the active layer 150. The layer emits light by the band gap difference of the energy band.

The active layer 150 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto.

The active layer 150 may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1). When the active layer 150 has a multi-quantum well structure, the active layer 150 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, the active layer 150 may be formed by alternately stacking a well layer including InGaN and a barrier layer including GaN.

A clad layer (not shown) doped with an n-type or p-type dopant may be formed on and / or under the active layer 150, and the clad layer (not shown) may be implemented as an AlGaN layer or an InAlGaN layer. have.

The third conductive semiconductor layer 160 may include a compound semiconductor of a group III-V element doped with a p-type dopant. The first semiconductor material having a composition formula of the third conductive type semiconductor layer 160 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1), For example, it may be selected from InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN, and the like, and p-type dopants such as Mg, Zn, Ca, Sr, and Ba may be doped. The third conductive semiconductor layer 160 may be formed as a single layer or a multilayer, but is not limited thereto.

Meanwhile, another n-type or p-type semiconductor layer (not shown) may be formed under the third conductive semiconductor layer 160. Accordingly, the light emitting structure 165 may have at least one of np, pn, npn, and pnp junction structures. That is, the structure of the light emitting structure 165 may be variously modified, but is not limited thereto.

In addition, doping concentrations of the dopants in the first semiconductor layer 120, the second conductive semiconductor layer 140, and the third conductive semiconductor layer 160 may be uniform or non-uniform.

The transparent electrode layer 170 may be formed on the third conductive semiconductor layer 160. The transparent electrode layer 170 serves to uniformly spread current in the third conductivity-type semiconductor layer 160.

The light transmitting electrode layer 170 is, for example, ITO, IZO (In-ZnO), GZO (Ga-ZnO), AZO (Al-ZnO), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), At least one of IrO _x , RuO _x , RuO _x / ITO, Ni / IrO _x / Au, and Ni / IrO _x / Au / ITO, but is not limited thereto.

A second electrode 190 may be formed on the light transmissive electrode layer 170, and a first electrode 180 may be formed on the second conductive semiconductor layer 140. The first electrode 180 and the second electrode 190 provide power to the light emitting device 100.

As described above, the light emitting device 100 according to the embodiment is generated from the substrate 110 by disposing the potential blocking layer 130 between the first semiconductor layer 120 and the second conductivity-type semiconductor layer 140. The potentials can be effectively blocked. 4 to 7 illustrate a method of manufacturing the horizontal light emitting device according to the embodiment. Hereinafter, the manufacturing process of the light emitting device according to the embodiment is, for example, metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD; Plasma-Enhanced Chemical) Vapor Deposition), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like, and the like, but are not limited thereto.

Referring to FIG. 4, the first semiconductor layer 120 is formed on the substrate 110 on which the plurality of patterns are formed.

The substrate 110 may be an insulating substrate, a conductive substrate, a semiconductor substrate, and the like, for example, in the group consisting of sapphire substrate (Al ₂ 0 ₃ ), GaN, SiC, ZnO, Si, GaP, InP, GaAs, and the like. Can be selected.

A plurality of patterns 105 may be formed on the substrate 110. The plurality of patterns 105 may be formed by an etching process of the substrate 110 or may be formed in a lens pattern with a separate material.

The first semiconductor layer 120 may be formed of a first conductivity type semiconductor layer or an undoped semiconductor layer.

When formed of the first conductivity type semiconductor layer, the first semiconductor layer 120 may have In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). A semiconductor material having a composition formula) may be selected from InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN, and the like, and n-type dopants such as Si, Ge, Sn, and the like may be doped. Here, the doping concentration of the first conductivity type semiconductor layer is preferably lower than the doping concentration of the second conductivity type semiconductor layer 140.

Meanwhile, when the undoped semiconductor layer is formed, the first semiconductor layer 120 may be formed of Undoped-GaN, which may not have n-type impurities, but may have n-type conductivity.

A buffer layer (not shown) may be formed between the substrate 110 and the first semiconductor layer 120 to mitigate lattice mismatch due to a lattice constant difference.

Referring to FIG. 5, a potential blocking layer 130 having a super lattice structure is formed on the first semiconductor layer 120.

The dislocation blocking layer 130 may be formed by alternately forming layers having a composition formula of Al _x In _(1-x) N (0 <x <1), and changing the value of x to form a super lattice structure. It can be formed as. For example, the potential blocking layer 130 may include a first AlInN layer having a composition ratio of Al _x In _(1-x) N (0.8 <x <1) and the Al _x In _(1-x) N (0 <x < It can be formed by alternately stacking the second AlInN layer having a composition ratio of 0.8).

In the growth method of the potential blocking layer 130, a mixed gas of NH ₃ / H ₂ / N ₂ , TMGa (or TEGa) and TMAl are selectively supplied, and the potential is removed and the potential is changed by changing an alkyl source. It will grow into a layer that can control the direction of. The potential blocking layer 130 is formed of a composition formula of Al _x In _(1-x) N (0 <x <1), and the growth temperature thereof may be heated to a temperature of 700 ° C. to 1100 ° C.

In the potential blocking layer 130, two different AlInN layers may be repeatedly stacked in a pair for a predetermined period. For example, the potential blocking layer 130 may be repeatedly stacked by 2 pairs to 50 pairs.

In addition, the thickness of each layer of the potential blocking layer 130 may be formed to about 1nm ~ 1㎛, the thickness of the two layers may be the same or different, but is not limited thereto.

Referring to FIG. 6, a light emitting structure 165 is formed on the potential blocking layer 130, and a light transmissive electrode layer 170 is formed on the light emitting structure 165.

The light emitting structure 165 is formed by sequentially growing a second conductive semiconductor layer 140, an active layer 150, and a third conductive semiconductor layer 160 on the potential blocking layer 130.

Semiconductor material having a composition formula of the second conductive type semiconductor layer 140 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1), For example, it may be selected from InAlGaN, GaN, AlGaN, AlInN, InGaN, AlN, InN, and the like, and an n-type dopant such as Si, Ge, Sn, or the like may be doped. Here, the doping concentration of the second conductive semiconductor layer 140 is preferably higher than the doping concentration of the first semiconductor layer 120.

The active layer 150 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto. Further, the active layer 150 may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) have.

Semiconductor material having a composition formula of the third conductive type semiconductor layer 160 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1), For example, it may be selected from InAlGaN, GaN, AlGaN, InGaN, AlInN, AlN, InN, and the like, and p-type dopants such as Mg, Zn, Ca, Sr, and Ba may be doped.

The transparent electrode layer 170 may be formed by, for example, a deposition process such as electron beam (E-beam) deposition, sputtering, and plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.

Referring to FIG. 7, a portion of the light emitting structure 165 and the transparent electrode layer 170 are etched to expose one top surface of the second conductive semiconductor layer 140. The light emitting device according to the embodiment is formed by forming a first electrode 180 on the exposed second conductive semiconductor layer 140 and forming a second electrode 190 on the light transmissive electrode layer 170. It can manufacture.

On the other hand, the potential blocking layer according to the embodiment can be equally applied to the vertical light emitting device as well as the horizontal light emitting device described above. Therefore, the following embodiment will briefly describe an example in which the potential blocking layer is implemented in a vertical light emitting device.

8 is a cross-sectional view of a vertical light emitting device according to the embodiment.

Referring to FIG. 8, the light emitting device 800 according to the embodiment may include a support substrate 880, a light emitting structure 835 on the support substrate 880, and a potential blocking layer 807 on the light emitting structure 835. ), A first conductive semiconductor layer 805 on the potential blocking layer 807, and an electrode 815 on the first conductive semiconductor layer 805.

The light emitting structure 835 includes a second conductive semiconductor layer 810, an active layer 820, and a third conductive semiconductor layer 830, and the second conductive semiconductor layer 810 and the third conductive layer. Electrons and holes provided from the type semiconductor layer 830 may be recombined in the active layer 820 to generate light.

A bonding layer 870, a reflective layer 860, an ohmic layer 850, a channel layer 840, and a current blocking layer 845 may be disposed between the support substrate 880 and the light emitting structure 835. The passivation layer 890 may be formed on the side surface of the light emitting structure 835. This will be described in more detail as follows.

The support substrate 880 may support the light emitting structure 835 and may provide power to the light emitting structure 835 together with the electrode 815. In addition, the support substrate 880 may be a conductive support substrate including at least one of Cu, Au, Ni, Mo, Cu-W, Si, Ge, GaAs, ZnO, or SiC. However, the embodiment is not limited thereto, and an insulating substrate may be used instead of the conductive support substrate, and a separate electrode may be formed.

A bonding layer 870 may be formed on the support substrate 880. The bonding layer 870 may be formed under the reflective layer 860 and the channel layer 840 as a bonding layer or a seed layer. The bonding layer 870 has an outer side surface exposed, and contacts the reflective layer 860, the end of the ohmic layer 850, and the channel layer 840 so that the reflective layer 860, the ohmic layer 850, and the channel layer 840 are exposed. It can strengthen the adhesion between). In addition, the bonding layer 870 includes a barrier metal or a bonding metal.

The reflective layer 860 may be formed on the bonding layer 870. The reflective layer 860 may be generated by the light emitting structure 835 to reflect light toward the reflective layer 860, thereby improving the luminous efficiency of the light emitting device 800.

The reflective layer 860 may include at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, Hf, or an alloy thereof. In addition, the reflective layer 860 is a metal or alloy described above, indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IZO), and indium gallium tin (IGTO) oxide), IGZO (indium gallium zinc oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide) can be formed in a multi-layer using a transmissive conductive material.

An ohmic layer 850 may be formed on the reflective layer 860. The ohmic layer 850 is in ohmic contact with the third conductivity type semiconductor layer 830 so that power can be smoothly supplied to the light emitting structure 835. The ohmic layer 850 may include ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, gallium zinc oxide (GZO), IrO _x , RuO _x , RuO _x / ITO, Ni, Ag, Pt, Ni / IrO _x / Au, or can be implemented as a single layer or multi-layer using at least one of _{Ni / IrO x / Au / ITO} .

A current blocking layer 845 may be formed between the ohmic layer 850 and the third conductive semiconductor layer 830. The current blocking layer 845 may include at least one of ZnO, SiO ₂ , SiON, Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , Ti, Al, Cr.

An upper surface of the current blocking layer 845 may contact the third conductive semiconductor layer 830, and a lower surface and a side surface of the current blocking layer 845 may contact the ohmic layer 850.

The current blocking layer 845 may be formed such that at least a portion of the current blocking layer 845 overlaps with the electrode 815, thereby concentrating a current to a shortest distance between the electrode 815 and the supporting substrate 880. The light emission efficiency of the light emitting device 800 may be improved by mitigating.

Meanwhile, a channel layer 840 may be formed outside the junction layer 870 and the third conductive semiconductor layer 830. That is, the channel layer 840 may be formed in a circumferential region between the light emitting structure 835 and the bonding layer 870, thereby forming a ring shape, a loop shape, a frame shape, or the like.

The channel layer 840 may include ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, ZnO, SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , Al ₂ O ₃ , TiO _x , TiO It may include at least one of ₂ , Ti, Al or Cr. The third conductive semiconductor layer 830 and the passivation layer 890 are in contact with the upper surface of the channel layer 840, and the ohmic layer 850 and the bonding layer 870 are disposed on the lower surface and the side surface of the channel layer 840. You can contact this.

In addition, a portion of the channel layer 840 may overlap the light emitting structure 835 in a vertical direction. The channel layer 840 may increase the distance at the side surface between the bonding layer 870 and the active layer 820 to reduce the possibility of electrical short circuit between the bonding layer 870 and the active layer 820. In addition, the channel layer 840 may prevent an electrical short circuit from occurring in the chip separation process.

In addition, the light emitting structure 835 may be formed on the ohmic layer 850 and the channel layer 840. Side surfaces of the light emitting structure 835 may be inclined by an isolation etching that divides a plurality of chips into unit chip regions.

The light emitting structure 835 may include a second conductive semiconductor layer 810, a third conductive semiconductor layer 830, and an active layer 820 disposed therebetween. In this case, the third conductive semiconductor layer 830 is positioned on the ohmic layer 850 and the channel layer 840, and the active layer 820 is positioned on the third conductive semiconductor layer 830, and the second conductive semiconductor layer 830 is disposed on the second conductive semiconductor layer 830. The conductive semiconductor layer 810 may be located on the active layer 820.

The second conductive type semiconductor layer 810 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) The n-type dopant may be formed by doping. For example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, etc. may be formed by including n-type dopants such as Si, Ge, Sn, Se, Te, and the like. Here, the doping concentration of the second conductivity type semiconductor layer 810 is preferably higher than the doping concentration of the first conductivity type semiconductor layer 805.

The active layer 820 may be formed of any one of a single quantum well structure, a multi quantum well structure (MQW), a quantum dot structure, or a quantum line structure, but is not limited thereto. The active layer 820 may be formed of a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1).

A cladding layer (not shown) doped with an n-type or p-type dopant may be formed on and / or under the active layer 820, and the cladding layer may include an AlGaN layer or an InAlGaN layer.

The second conductive type semiconductor layer 830 is a semiconductor material having a compositional formula of _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) The p-type dopant may be formed by doping. For example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, etc. may be formed by including p-type dopants such as Mg, Zn, Ca, Sr, Br and the like.

A potential blocking layer 807 having a super lattice structure is formed on the nitride semiconductor layer 810.

The dislocation blocking layer 807 may be formed by alternately forming layers having a compositional formula of Al _x In _(1-x) N (0 <x <1), and changing the value of x to form a superlattice structure. It can be formed as. For example, the potential blocking layer 807 may include a first AlInN layer having a composition ratio of Al _x In _(1-x) N (0.8 <x <1) and the Al _x In _(1-x) N (0 <x < It can be formed by alternately stacking the second AlInN layer having a composition ratio of 0.8).

A first conductivity type semiconductor layer 805 may be formed on the potential blocking layer 807. A semiconductor material having a compositional formula of the first conductive semiconductor layer 805 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) The n-type dopant may be formed by doping. The doping concentration of the first conductive semiconductor layer 805 may be lower than that of the nitride semiconductor layer 810.

Meanwhile, an undoped semiconductor layer (not shown) may be formed on the potential blocking layer 807 instead of the first conductive semiconductor layer 805.

The light extracting structure 812 may be formed on an upper surface of the first conductive semiconductor layer 805. The light extraction structure 812 may improve the light extraction efficiency of the light emitting device 800 by minimizing the amount of light totally reflected from the surface. The light extracting structure 812 may have a random shape and arrangement, or may be formed to have a regular shape and arrangement.

An electrode 815 is formed on an upper surface of the first conductive semiconductor layer 805. The electrode 815 may be branched in a predetermined pattern shape, but is not limited thereto. The electrode 815 may be Au, Pd, Pt, Ru, Re, Mg, Zn, Hf, Ta, Rh, Ir, W, Ti, Ag, Cr, Mo, Nb, Al, Ni, Cu, WTi or their It may comprise at least one of the alloys.

Meanwhile, a passivation layer 890 may be formed on at least one side of the light emitting structure 835. The passivation layer 890 may be formed on an upper surface of the first conductive semiconductor layer 805 and an upper surface of the channel layer 840, but is not limited thereto.

The passivation layer 890 may be formed to electrically protect the light emitting structure 835. For example, the passivation layer 890 may be formed of SiO ₂ , SiO _x , SiO _x N _y , Si ₃ N ₄ , and Al ₂ O ₃ . However, the present invention is not limited thereto.

As described above, in the light emitting device 800 according to the embodiment, a growth substrate (not shown) is disposed between the second conductive semiconductor layer 810 and the first conductive semiconductor layer 805 by disposing the potential blocking layer 807. Can effectively block potentials generated from

9 is a cross-sectional view of a light emitting device package including a light emitting device according to the embodiment.

Referring to FIG. 9, the light emitting device package 900 may include a package body 30, a first electrode 31 and a second electrode 32 installed on the package body 30, and a package body 30. The light emitting device 100 is installed to be electrically connected to the first electrode 31 and the second electrode 32, and a molding member 40 surrounding the light emitting device 100.

The package body 30 may include a silicon material, a synthetic resin material, or a metal material, and may have a cavity having an inclined side surface.

The first electrode 31 and the second electrode 32 are electrically separated from each other, and provide power to the light emitting device 100. In addition, the first electrode 31 and the second electrode 32 may increase the light efficiency by reflecting the light generated from the light emitting device 100, the heat generated from the light emitting device 100 to the outside It can also play a role.

The light emitting device 100 may be installed on the package body 30 or on the first electrode 31 or the second electrode 32.

The light emitting device 100 may be electrically connected to the first electrode 31 and the second electrode 32 by any one of a wire method, a flip chip method, and a die bonding method. In the present embodiment, it is illustrated that the light emitting device 100 is electrically connected to the first electrode 31 and the wire 50 and is directly connected to the second electrode 32.

The molding member 40 may surround the light emitting device 100 to protect the light emitting device 100. In addition, the molding member 40 may include a phosphor to change the wavelength of light emitted from the light emitting device 100.

A plurality of light emitting device packages according to the embodiment may be arranged on a substrate, and a light guide plate, a prism sheet, a diffusion sheet, a fluorescent sheet, and the like, which are optical members, may be disposed on a path of light emitted from the light emitting device package. The light emitting device package, the substrate, and the optical member may function as a backlight unit or as a lighting unit. For example, the lighting system may include a backlight unit, a lighting unit, an indicator device, a lamp, and a street lamp.

10 is a view illustrating a backlight unit including a light emitting device or a light emitting device package according to an embodiment. However, the backlight unit 1000 of FIG. 10 is an example of a lighting system, but is not limited thereto.

Referring to FIG. 10, the backlight unit 1000 may include a bottom frame 1040, an optical guide member 1020 disposed in the bottom frame 1040, and at least one side or a bottom surface of the optical guide member 1020. It may include a light emitting module 1010 disposed in. In addition, a reflective sheet 1030 may be disposed under the light guide member 1020.

The bottom frame 1040 may be formed in a box shape having an upper surface open to accommodate the light guide member 1020, the light emitting module 1010, and the reflective sheet 1030. Or it may be formed of a resin material but is not limited thereto.

The light emitting module 1010 may include a substrate 700 and a plurality of light emitting device packages 600 mounted on the substrate 700. The plurality of light emitting device packages 600 may provide light to the light guide member 1020. In the present embodiment, the light emitting module 1010 is illustrated that the light emitting device package 600 is installed on the substrate 700, the light emitting device 100 according to the embodiment may be installed directly.

As shown, the light emitting module 1010 may be disposed on at least one of the inner surfaces of the bottom frame 1040, thereby providing light toward at least one side of the light guide member 1020. can do.

However, the light emitting module 1010 may be disposed under the bottom frame 1040 to provide light toward the bottom of the light guide member 1020, which is according to the design of the backlight unit 1000. Since various modifications are possible, the present invention is not limited thereto.

The light guide member 1020 may be disposed in the bottom frame 1040. The light guide member 1020 may guide the light provided from the light emitting module 1010 to a display panel (not shown) by making a surface light source.

The light guide member 1020 may be a light guide panel (LGP). The light guide plate may be formed of one of an acrylic resin series such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), poly carbonate (PC), COC, and polyethylene naphthalate (PEN) resin.

The optical sheet 1050 may be disposed above the light guide member 1020.

The optical sheet 1050 may include at least one of a diffusion sheet, a light collecting sheet, a luminance rising sheet, and a fluorescent sheet. For example, the optical sheet 1050 may be formed by stacking the diffusion sheet, the light collecting sheet, the luminance increasing sheet, and the fluorescent sheet. In this case, the diffusion sheet 1050 evenly spreads the light emitted from the light emitting module 1010, and the diffused light may be focused onto a display panel (not shown) by the light collecting sheet. In this case, the light emitted from the light collecting sheet is randomly polarized light, and the luminance increasing sheet may increase the degree of polarization of the light emitted from the light collecting sheet. The light collecting sheet may be a horizontal or vertical prism sheet. In addition, the luminance increase sheet may be a roughness enhancement film. In addition, the fluorescent sheet may be a translucent plate or film containing a phosphor.

The reflective sheet 1030 may be disposed under the light guide member 1020. The reflective sheet 1030 may reflect light emitted through the lower surface of the light guide member 1020 toward the exit surface of the light guide member 1020.

The reflective sheet 1030 may be formed of a resin material having good reflectance, that is, PET, PC, PVC resin, etc., but is not limited thereto.

11 is a view illustrating a lighting unit including a light emitting device or a light emitting device package according to an embodiment. However, the lighting unit 1100 of FIG. 11 is an example of a lighting system, but is not limited thereto.

Referring to FIG. 11, the lighting unit 1100 is installed in the case body 1110, the light emitting module 1130 installed in the case body 1110, and the case body 1110 and provides power from an external power source. The receiving connection terminal 1120 may be included.

The case body 1110 may be formed of a material having good heat dissipation, for example, may be formed of a metal material or a resin material.

The light emitting module 1130 may include a substrate 700 and at least one light emitting device package 600 mounted on the substrate 700. In the present embodiment, the light emitting module 1230 is illustrated that the light emitting device package 600 is installed on the substrate 700, the light emitting device 100 according to the present embodiment may be installed directly.

The substrate 700 may be a circuit pattern printed on the insulator, and for example, a general printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, and the like. It may include.

In addition, the substrate 700 may be formed of a material that reflects light efficiently, or may be formed of a color in which the surface is efficiently reflected by light, for example, white, silver, or the like.

The at least one light emitting device package 600 may be mounted on the substrate 700. Each of the light emitting device packages 600 may include at least one light emitting diode (LED). The light emitting diodes may include colored light emitting diodes emitting red, green, blue, or white colored light, and UV light emitting diodes emitting ultraviolet (UV) light.

The light emitting module 1130 may be arranged to have a combination of various light emitting diodes in order to obtain color and brightness. For example, the white light emitting diode, the red light emitting diode, and the green light emitting diode may be combined and disposed to secure high color rendering (CRI). In addition, a fluorescent sheet may be further disposed on a path of the light emitted from the light emitting module 1130, and the fluorescent sheet changes the wavelength of light emitted from the light emitting module 1130. For example, when the light emitted from the light emitting module 1130 has a blue wavelength band, the fluorescent sheet may include a yellow phosphor, and the light emitted from the light emitting module 1130 may finally pass white light through the fluorescent sheet. Will appear.

The connection terminal 1120 may be electrically connected to the light emitting module 1130 to supply power. As shown in FIG. 11, the connection terminal 1120 is coupled to the external power source by being connected to the socket in a socket manner, but is not limited thereto. For example, the connection terminal 1120 may be formed in a pin shape and inserted into an external power source, or may be connected to the external power source by a wire.

In the lighting system as described above, at least one of a light guide member, a diffusion sheet, a light collecting sheet, a luminance rising sheet, and a fluorescent sheet may be disposed on a propagation path of light emitted from the light emitting module to obtain a desired optical effect.

As described above, the illumination system may have excellent light efficiency and reliability by including a light emitting device or a light emitting device package which reduces the operating voltage and improves the light efficiency.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by equivalents to the appended claims, as well as the appended claims.

100: light emitting element 110: substrate
120: first semiconductor layer 130: potential blocking layer
140: second conductive semiconductor layer 150: active layer
160: third conductive semiconductor layer 170: translucent electrode layer
180: first electrode 190: second electrode

Claims (11)

A first semiconductor layer;
A potential blocking layer in which a first AlInN layer having a tensile stress and a second AlInN layer having a compressive stress are alternately stacked on the first semiconductor layer;
A second conductivity type semiconductor layer on the potential blocking layer;
An active layer on the second conductivity type semiconductor layer; And
A light emitting device comprising a third conductive semiconductor layer on the active layer. The method of claim 1,
The first semiconductor layer includes at least one semiconductor layer of a first conductivity type semiconductor layer and an undoped semiconductor layer. The method of claim 2,
The first conductive semiconductor layer has a lower doping concentration than the second conductive semiconductor layer. The method according to claim 2 or 3,
A light emitting device comprising a buffer layer under the first semiconductor layer. The method of claim 1,
A light emitting device comprising a substrate having a plurality of patterns formed under the first semiconductor layer. The method of claim 1,
The potential blocking layer has a super lattice structure. The method of claim 1,
The first AlInN layer and the second AlInN layer is a light emitting device having a different aluminum (Al) / indium (In) composition ratio. The method of claim 1,
Each of the first AlInN layer and the second AlInN layer has a thickness of 1 nm to 1 μm. The method of claim 1,
The first AlInN layer has a higher Al composition ratio than the second AlInN layer. 10. The method of claim 9,
The first AlInN layer has a composition ratio of Al _x In _(1-x) N (0.8 <x <1). The method of claim 10,
The second AlInN layer has a composition ratio of Al _x In _(1-x) N (0 <x <0.8).

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