KR20120065565A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce resistance-string which is included in a data driving unit in vertical interlace and to share two sub pixels. CONSTITUTION: Sub-pixels(SP1,SPr) share a data line of two sub-pixels. The sub-pixels are connected to two gate lines. A gate driving unit supplies a gate signal to the gate lines. The data driving unit supplies a data voltage to the data lines.

Description

[0001] The present invention relates to a liquid crystal display device,

An embodiment of the present invention relates to a liquid crystal display device.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, flat panel displays (FPDs) such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs) may be used. Usage is increasing. Among them, a liquid crystal display capable of realizing high resolution and capable of miniaturization as well as a large size is widely used.

The liquid crystal display device includes a liquid crystal layer positioned between a transistor substrate on which a transistor, a storage capacitor, a pixel electrode, and the like are formed, and a color filter substrate on which a color filter and a black matrix are formed. The liquid crystal display displays an image by emitting light incident from the backlight unit by adjusting an arrangement direction of the liquid crystal layer with an electric field formed at the pixel electrode and the common electrode formed on the transistor substrate or the color filter substrate.

Conventional liquid crystal displays have provided a data voltage by using a dot inversion method to cancel flicker and crosstalk. However, this method has a structure in which the data voltage output from one data output channel is supplied to one sub pixel located in one row, so that the power consumption of the data driver is high.

According to an embodiment of the present invention for solving the problems of the background art, a resistance string (R-String) included in the data driver may be reduced to one during vertical interlace driving, and one data line may be adjacent to each other. The present invention provides a liquid crystal display device which can reduce power consumption due to data voltage generation and can reduce the size of a bezel area by sharing two sub pixels.

Embodiments of the present invention by the above-described problem solving means, the data lines are lined line by line in the column direction; Gate lines interconnected by two lines in a row direction crossing the column direction; Subpixels having a structure in which one data line of the data lines is shared for each of the two sub pixels adjacent to one row, and each of the two sub pixels is divided and connected to two gate lines of the gate lines; A gate driver supplying gate signals to the gate lines; And a data driver for supplying data voltages to the data lines, wherein the gate driver supplies a sequential gate signal to the gate lines for one frame.

The data driver may supply data voltages inverted in order of first polarity, second polarity, second polarity, and first polarity to the data lines.

The sub pixels may have a structure in which one data line is shared for every two sub pixels adjacent to the left and the right with respect to one data line in a row.

The two subpixels may include one subpixel connected to the first data line and connected to the first gate line, and the other subpixel connected to the first data line and connected to the second gate line.

The gate lines may transmit gate signals forming a sequential scan high signal from the first gate line to the fourth gate line during one frame.

In another aspect, an embodiment of the present invention, the data line is wired line by line in the column direction; Gate lines interconnected by two lines in a row direction crossing the column direction; Subpixels having a structure in which one data line of the data lines is shared for each of the two sub pixels adjacent to one row, and each of the two sub pixels is divided and connected to two gate lines of the gate lines; A gate driver supplying gate signals to the gate lines; And a data driver configured to supply data voltages to the data lines, wherein the gate driver supplies gate signals divided into odd frames and even frames to two gate lines.

The data driver may supply data voltages inverted in order of first polarity, second polarity, second polarity, and first polarity to the data lines.

The sub pixels may have a structure in which one data line is shared for every two sub pixels adjacent to the left and the right with respect to one data line in a row.

The two subpixels may include one subpixel connected to the first data line and connected to the first gate line, and the other subpixel connected to the first data line and connected to the second gate line.

The gate lines transmit odd gate signals in which the first gate line and the third gate line form a scan high signal during an odd frame, and the even gates in which the second gate line and the fourth gate line form a scan high signal during an even frame The gate signals may be transferred.

According to an embodiment of the present invention, a resistance string (R-String) included in the data driver may be reduced to one during vertical interlace driving, and data voltages are generated by sharing two data lines adjacent to one sub-pixel. According to the present invention, there is an effect of providing a liquid crystal display that can reduce power consumption and reduce the size of the bezel area.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is a partial configuration diagram of a liquid crystal panel according to a first embodiment of the present invention.
3 is a waveform diagram of a signal supplied to a liquid crystal panel shown in FIG. 2.
4 is a partial configuration diagram of a liquid crystal panel according to a second embodiment of the present invention.
FIG. 5 is a waveform diagram of a signal supplied to the liquid crystal panel shown in FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a timing controller TCN, a power supply unit PWR, a data driver DRV, a gate driver SDRV, a liquid crystal panel PNL, and a backlight. Unit (BLU) is included.

The timing controller TCN receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the data signal DATA from the outside. The timing controller TCN operates the data driver DDRV and the gate driver SDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Control the timing. Since the timing controller TCN may determine the frame period by counting the data enable signal DE of one horizontal period, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside may be omitted. Representative control signals generated by the timing controller TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal for controlling the operation timing of the data driver DDR. DDC). The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is supplied to a gate drive integrated circuit (IC) where the first gate signal is generated. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and the like. The source start pulse SSP controls the data sampling start time of the data driver DDRV. The source sampling clock SSC is a clock signal that controls the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV. Meanwhile, the source start pulse SSP supplied to the data driver DVV may be omitted according to the data transmission method.

The power supply unit PWR adjusts the voltage Vin supplied from the system board to generate a driving voltage, and generates the generated driving voltage as the timing controller TCN, the data driver DRV, the gate driver SDRV, and the liquid crystal panel PNL. Supply to any one or more of them. In addition, the power supply unit PWR generates gamma voltages GMA0 to GMAn and a common voltage Vcom and supplies them to the data driver DDRV and the liquid crystal panel PNL.

The liquid crystal panel PNL includes a liquid crystal layer positioned between the transistor substrate (hereinafter, abbreviated as TFT substrate) and the color filter substrate and includes sub pixels arranged in a matrix form. Data lines, gate lines, TFTs, storage capacitors, and the like are formed on the TFT substrate, and black matrices, color filters, and the like are formed on the color filter substrate. One subpixel SP is defined by a data line D1 and a gate line G1 that cross each other. The subpixel SP includes a TFT driven by a gate signal supplied through the gate line G1, a storage capacitor storing the data signal supplied through the data line D1 as a data voltage, and a data voltage stored in the storage capacitor. A liquid crystal cell driven by is included. The liquid crystal cell is driven by the data voltage supplied to the pixel electrode and the common voltage Vcom supplied to the common electrode. The common electrode is formed on the color filter substrate in a vertical field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. In the driving method, a pixel electrode is formed on the TFT substrate. The polarizing plate is attached to the TFT substrate and the color filter substrate of the liquid crystal panel PNL, and an alignment layer for setting the pre-tilt angle of the liquid crystal is formed. The liquid crystal mode of the liquid crystal panel PNL may be implemented in any liquid crystal mode as well as the above-described TN mode, VA mode, IPS mode, and FFS mode.

The backlight unit BLU provides light to the liquid crystal panel PNL. The backlight unit BLU includes a light source circuit unit including a DC power supply unit, light emitting units, transistors, and a driving control unit, and an optical unit unit including a cover bottom, a light guide plate, an optical sheet, and the like. The backlight unit BLU may be configured in various ways such as an edge type, a dual type, a direct type, and the like. Here, the edge type is one in which light emitting diodes are arranged in a line (or string) form on one side of the liquid crystal panel PNL. The dual type is one in which light emitting diodes are arranged in a string (or string) on both sides of the liquid crystal panel PNL. In the direct type, the light emitting diodes are arranged in a block or matrix form under the liquid crystal panel PNL.

The gate driver SDRV is a swing width of a gate driving voltage at which TFTs of the subpixels SP included in the liquid crystal panel PNL can operate in response to the gate timing control signal GDC supplied from the timing controller TCN. The gate signal is sequentially generated while shifting the signal level. The gate driver SDRV supplies the gate signals generated through the gate lines GL to the subpixels SP included in the liquid crystal panel PNL.

The data driver DDRV samples, latches, and converts the data signal DATA supplied from the timing controller TCN in response to the data timing control signal DDC supplied from the timing controller TCN to convert data into a parallel data system. . The data driver DDRV converts the data signal DATA into a gamma reference voltage when converting the data into a parallel data system. The data driver DDRV supplies the data signal DATA converted through the data lines DL to the subpixels SP included in the liquid crystal panel PNL.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in more detail.

≪ Embodiment 1 >

FIG. 2 is a partial configuration diagram of a liquid crystal panel according to the first embodiment of the present invention, and FIG. 3 is a waveform diagram of a signal supplied to the liquid crystal panel shown in FIG.

1 and 2, in the liquid crystal panel according to the first exemplary embodiment of the present invention, data lines D1 to D3, gate lines G1 to G4, and subpixels SP1 and SPr may be formed. Included.

The data lines D1 to D3 are wired line by line in the column direction. The data lines D1 to D3 have regions wired by one line for every two subpixels.

The gate lines G1 to G4 are wired by two lines in the row direction crossing the column direction. In the gate lines G1 to G4, first and second gate lines G1 and G2 are wired between the subpixels positioned in the first row direction and the subpixels positioned in the second row direction. Accordingly, the remaining third and fourth gate lines G3 and G4 are wired between the subpixels positioned in the second row direction and the subpixels (not shown) located in the third row direction.

The subpixels SPl and SPr share one data line (for example, D1) of the data lines D1 to D3 for each of the two subpixels SPl and SPr adjacent to one row, and the gate lines G1. Two gate lines (for example, G1 and G2) of ˜G4) are divided and connected to each other. In more detail, the subpixels SPl and SPr may have one data line for each of the two subpixels SPl and SPr adjacent to the left and the right with respect to one data line (for example, D1) in one row. For example, it has a structure sharing D1). Accordingly, two sub-pixels SPl and SPr adjacent to one row are connected to the first data line D1 and one subpixel SPl connected to the first gate line G1 and the first data line. The other sub-pixel SPr connected to the D1 and connected to the second gate line G2 is included.

In the liquid crystal display device having the subpixel structure as in the first embodiment, the gate driver SDRV and the data driver DVV are driven as shown in FIG. 3.

The gate driver SDRV supplies sequential gate signals Gclk1 to Gclk4 to the gate lines G1 to G4 for one frame. Accordingly, the first gate signal Gclk1 is supplied to the first gate line G1 during one frame, and then the second gate signal Gclk2 is supplied to the second gate line G2, and the third gate line G3 is supplied. After the third gate signal Gclk3 is supplied to the gate signals, the gate signals Gclk1 to Gclk4 are supplied in the order that the fourth gate signal Gclk4 is supplied to the fourth gate line G4. Therefore, the gate lines G1 to G4 transfer the gate signals Gclk1 to Gclk4 in which scan high signals are sequentially formed from the first gate line G1 to the fourth gate line G4 for one frame.

The data driver DDRV inverts the data lines D1 to D3 in the order of first polarity (-), second polarity (+), second polarity (+), and first polarity (-) for one frame. Supply the voltage. Accordingly, one subpixel SP1 positioned in the first row is charged with the first polarity (−), and the other subpixel SPr adjacent thereto is charged with the second polarity (+), and is positioned in the second row. One subpixel SP1 is charged with a second polarity (+) and the other subpixel SPr adjacent thereto is charged with a first polarity (−).

The liquid crystal display of the first embodiment is driven by the above-described subpixel structure and driving method to drive the vertical interlace, thereby reducing the resistance string included in the data driver DDRV to one. have. Here, the resistance string is a combined resistance block for forming the positive data voltage or the negative data voltage according to the gray scale. In addition, in the liquid crystal display of the first exemplary embodiment, since two subpixels share one data line, power consumption due to generation of data voltage can be reduced and the size of the bezel area can be reduced.

Second Embodiment

4 is a partial configuration diagram of a liquid crystal panel according to a second embodiment of the present invention, and FIG. 5 is a waveform diagram of a signal supplied to the liquid crystal panel shown in FIG. 4.

1 and 4, in the liquid crystal panel according to the second embodiment of the present invention, data lines D1 to D3, gate lines G1 to G4, and subpixels SP1 and SPr are formed. Included.

The data lines D1 to D3 are wired line by line in the column direction. The data lines D1 to D3 have regions wired by one line for every two subpixels.

The gate lines G1 to G4 are wired by two lines in the row direction crossing the column direction. In the gate lines G1 to G4, first and second gate lines G1 and G2 are wired between the subpixels positioned in the first row direction and the subpixels positioned in the second row direction. Accordingly, the remaining third and fourth gate lines G3 and G4 are wired between the subpixels positioned in the second row direction and the subpixels (not shown) located in the third row direction.

The subpixels SPl and SPr share one data line (for example, D1) of the data lines D1 to D3 for each of the two subpixels SPl and SPr adjacent to one row, and the gate lines G1. Two gate lines (for example, G1 and G2) of ˜G4) are divided and connected to each other. In more detail, the subpixels SPl and SPr may have one data line for each of the two subpixels SPl and SPr adjacent to the left and the right with respect to one data line (for example, D1) in one row. For example, it has a structure sharing D1). Accordingly, two sub-pixels SPl and SPr adjacent to one row are connected to the first data line D1 and one subpixel SPl connected to the first gate line G1 and the first data line. The other sub-pixel SPr connected to the D1 and connected to the second gate line G2 is included.

In the liquid crystal display device having the subpixel structure as in the second embodiment, the gate driver SDRV and the data driver DVV are driven as shown in FIG. 4.

The gate driver SDRV divides one frame into an odd frame and an even frame, and is divided into an odd frame and an even frame on the gate lines G1 to G4. The gate signals Gclk1, Gclk3 to Gclk2, and Gclk4 are supplied. Accordingly, the first gate signal Gclk1 is supplied to the first gate line G1 and then the third gate signal Gclk3 is supplied to the third gate line G3 during the odd frame. During the even frame, the second gate signal Gclk2 is supplied to the second gate line G2, and then the fourth gate signal Gclk4 is supplied to the fourth gate line G4. Therefore, the gate lines G1 to G4 are used for the odd gate signals Gclk1 and Gclk3 in which the first gate line G1 and the third gate line G3 form a scan high signal during an odd frame. The second gate line G2 and the fourth gate line G4 transmit the even gate signals Gclk2 and Gclk4 forming the scan high signal during the even frame.

The data driver DVV may include a first polarity (−), a second polarity (+), a second polarity (+), and a polarity in the data lines D1 to D3 during odd and even frames. The data voltage is inverted in the order of the first polarity (−). Accordingly, one subpixel SP1 positioned in the first row and the other subpixel SPr positioned in the second row are charged with the first polarity (−) during the odd frame. During the even frame, the other subpixel SPr positioned in the first row and the one subpixel SPl positioned in the second row are charged with the second polarity (+).

The liquid crystal display of the second embodiment is driven by the above-described subpixel structure and driving method for driving the vertical interlace, thereby reducing the resistance string included in the data driver DDRV to one. have. Here, the resistance string is a combined resistance block for forming the positive data voltage or the negative data voltage according to the gray scale. In addition, in the liquid crystal display of the second exemplary embodiment, since two subpixels share one data line, power consumption due to generation of a data voltage can be reduced and the size of the bezel area can be reduced.

As described above, the present invention can reduce the resistance string (R-String) included in the data driver when driving a vertical interlace, and share a single data line with two adjacent sub-pixels to generate power according to the data voltage. In addition to reducing the consumption, there is an effect of providing a liquid crystal display that can reduce the size of the bezel area.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

TCN: Timing Control PWR: Power Supply
DDRV: data driver SDRV: gate driver
PNL: Liquid Crystal Panel BLU: Backlight Unit
D1 to D3: data lines G1 to G4: gate lines
SPl: one subpixel SPr: the other subpixel

Claims (10)

Data lines wired line by line in a column direction;
Gate lines interconnected by two lines in a row direction crossing the column direction;
Subpixels having a structure sharing one data line of the data lines for each two subpixels adjacent to one row, and having a structure divided and connected to two gate lines of the gate lines;
A gate driver supplying gate signals to the gate lines; And
A data driver configured to supply a data voltage to the data lines,
The gate driver,
And sequentially supplying gate signals to the gate lines for one frame. The method of claim 1,
The data driver,
And supplying data voltages inverted in order of first polarity, second polarity, second polarity, and first polarity to the data lines. The method of claim 1,
The subpixels,
And a structure in which the one data line is shared for each of the two sub-pixels adjacent to the left and the right with respect to the one data line in one row. The method of claim 1,
The two subpixels,
A subpixel connected to the first data line and connected to the first gate line;
And the other subpixel connected to the first data line and connected to the second gate line. The method of claim 1,
The gate lines,
And a gate signal in which a sequential scan high signal is formed from the first gate line to the fourth gate line during the one frame. Data lines wired line by line in a column direction;
Gate lines interconnected by two lines in a row direction crossing the column direction;
Subpixels having a structure sharing one data line of the data lines for each two subpixels adjacent to one row, and having a structure divided and connected to two gate lines of the gate lines;
A gate driver supplying gate signals to the gate lines; And
A data driver configured to supply a data voltage to the data lines,
The gate driver,
And supplying a gate signal divided into an odd frame and an even frame to the two gate lines. The method of claim 6,
The data driver,
And supplying data voltages inverted in order of first polarity, second polarity, second polarity, and first polarity to the data lines. The method of claim 6,
The subpixels,
And a structure in which the one data line is shared for each of the two sub-pixels adjacent to the left and the right with respect to the one data line in one row. The method of claim 6,
The two subpixels,
A subpixel connected to the first data line and connected to the first gate line;
And the other subpixel connected to the first data line and connected to the second gate line. The method of claim 6,
The gate lines,
First and third gate lines transmit odd gate signals that form a scan high signal during the odd frame,
And the second gate line and the fourth gate line transfer the even gate signals forming the scan high signal during the even frame.

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