KR20190012053A - Light Emitting Display Device and Driving Method thereof - Google Patents

Abstract

The present invention provides an electroluminescent display device including a display panel, a data driving part, and a scan driving part. The display panel displays an image. The data driving part supplies a data voltage to the display panel. The scan driving part supplies a scan signal to the display panel. The display panel receives the scan signal and the data voltage by a block unit, wherein a data voltage programming direction between blocks is alternated in first and second directions and the data voltage programming direction between frames is alternated so that the data voltage programming direction is opposed to a previous data voltage programming direction. The electroluminescent display device may relatively display uniform luminance.

Description

[0001] The present invention relates to an electroluminescent display device and a driving method thereof,

The present invention relates to an electroluminescent display device and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a plasma display device are increasingly used.

The display apparatus includes a display panel including a plurality of sub pixels, a driver for driving the display panel, and a power supply unit for supplying power to the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

In the electroluminescent display device, when a scan signal, a data signal, or the like is supplied to subpixels, a light emitting diode of a selected subpixel emits light, thereby displaying an image. Light emitting diodes are implemented on organic basis or on inorganic basis.

The electroluminescent display device can employ a block driving method in which a display region of a display panel is divided into blocks. The block driving method has effects such as reduction of power consumption of display panel, securing of sensing time, improvement of compensation accuracy, improvement of dynamic contrast ratio, improvement of Moving Picture Response Time (MPRT), and BDI (Black Data Insertion). However, the block driving method proposed in the related art has an improvement for improving the performance such that a luminance deviation occurs across the entire display panel.

In order to solve the above problems, the present invention provides a block driving method capable of removing luminance steps between blocks and expressing luminance relatively uniformly. Further, the present invention provides a block driving method capable of reducing a luminance deviation.

According to an aspect of the present invention, there is provided an electroluminescent display device including a display panel, a data driver, and a scan driver. The display panel displays the image. The data driver supplies a data voltage to the display panel. The scan driver supplies a scan signal to the display panel. The display panel receives a scan signal and a data voltage in block units of a display area, and alternates the data voltage programming direction between the blocks in the first direction and the second direction, .

And a scan direction control unit for changing a data voltage programming direction.

The scan direction controller may control the start direction of the start pulse supplied to the scan driver.

The scan direction controller may control the scan driver to output a forward scan signal or to output a reverse scan signal.

The scan direction controller can control the flow of the start pulse input / output from the scan driver.

The scan direction control unit may include transistors that operate in response to an output control signal supplied from the outside.

The transistors may include transistors for controlling the forward scan signal and transistors for controlling the reverse scan signal.

The transistors for controlling the reverse scan signal can be driven inversely to the transistors for controlling the forward scan signal.

According to another aspect of the present invention, there is provided a driving method of an electroluminescent display device in which a display area of a display panel is defined in units of blocks and a scan signal and a data voltage are inputted to perform block-by-block driving. A method of driving an electroluminescent display device includes programming a data voltage in a first direction with respect to a first block defined in a display panel during a first frame period and programming the data voltage with respect to a second block defined in the display panel during a first frame period Programming the data voltage in two directions; And changing the programming direction for the first block and the second block during the second frame period.

When the same data voltage is applied to the display panel during the first frame and the second frame, the brightnesses opposite to each other in the first frame and the second frame may appear.

The present invention provides an electroluminescent display device and a method of driving the same, which can display luminance relatively uniformly by eliminating a brightness step between blocks and accumulating and accumulating luminance deviation. In addition, the present invention provides a block driving method capable of reducing luminance deviation, which can reduce power consumption of a display panel, secure sensing time and improve compensation accuracy, improve dynamic contrast ratio, improve Moving Picture Response Time (MPRT) BDI (Black Data Insertion) and the like can be performed.

1 is a schematic block diagram of an organic light emitting display device.
2 is a schematic circuit configuration diagram of a subpixel.
FIG. 3 is a schematic circuit configuration example of a subpixel capable of controlling the light emission time. FIG.
4 is a waveform diagram of an emission control signal;
5 is a data programming diagram for explaining a conventional driving method proposed in the related art.
6 is a data programming diagram for explaining a block driving method proposed in the related art.
7 is a view for explaining a problem of a block driving method proposed in the related art.
8 is a data programming diagram for explaining a block driving method according to an embodiment of the present invention.
9 is a view for explaining improvement of a block driving method according to an embodiment of the present invention.
10 is a data programming diagram for explaining a block driving method according to a comparative example.
11 is a data programming diagram for explaining a block driving method according to an embodiment.
12 is an exemplary layout of a scan driver for implementing an embodiment of the present invention;
13 is an exemplary internal configuration of one scan driver;
14 is a waveform diagram showing output characteristics of a scan signal according to characteristics of an output control signal applied to a scan driver;
15 is a circuit diagram illustrating a scan driver and a scan direction controller;
16 is a waveform diagram showing output characteristics of a scan signal according to the operation of the scan direction control unit;
FIG. 17 is a schematic diagram illustrating a circuit configuration for controlling a scan driver based on an output control signal. FIG.
18 is an exemplary view showing the flow of start pulses per output control signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The electroluminescent display device described below may be implemented as a television, a video player, a personal computer (PC), a home theater, a smart phone, a virtual reality device (VR), or the like. The electroluminescent display device described below will be described with reference to an organic electroluminescent display device implemented based on an organic light emitting diode (light emitting device). However, the electroluminescent display device described below may be implemented based on inorganic light emitting diodes.

The thin film transistor of the electroluminescence display device described below may be referred to as a source electrode, a drain electrode, a drain electrode, and a source electrode, depending on the type, except for the gate electrode. However, .

FIG. 1 is a schematic block diagram of an organic light emitting display device, and FIG. 2 is a schematic circuit configuration diagram of a subpixel.

1, the organic light emitting display includes an image processing unit 110, a timing control unit 120, a data driving unit 130, a scan driving unit 140, a display panel 150, and a power supply unit 170 .

The image processing unit 110 outputs a data enable signal DE together with a data signal DATA supplied from the outside. The image processing unit 110 may output at least one of a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of explanation.

The timing controller 120 receives a data signal DATA from a video processor 110 in addition to a data enable signal DE or a driving signal including a vertical synchronizing signal, a horizontal synchronizing signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130, .

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 and converts the sampled data signal into a gamma reference voltage . The data driver 130 outputs a data voltage through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an IC (Integrated Circuit).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or a gate-in-panel (GATE) panel in the display panel 150.

The power supply unit 170 outputs a high potential voltage and a low potential voltage. The high-potential voltage and the low-potential voltage output from the power supply unit 170 are supplied to the display panel 150. The high potential voltage is supplied to the display panel 150 through the first power supply line EVDD and the low potential voltage is supplied to the display panel 150 through the second power supply line EVSS.

The display panel 150 displays an image corresponding to the data voltage and the scan signal supplied from the data driver 130 and the scan driver 140 and the power supplied from the power supplier 170. The display panel 150 includes sub-pixels SP that operate to display an image.

The subpixels SP include a red subpixel, a green subpixel, and a blue subpixel or a white subpixel, a red subpixel, a green subpixel, and a blue subpixel. The subpixels SP may have one or more different emission areas depending on the emission characteristics.

As shown in FIG. 2, one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode OLED. The compensation circuit CC may be omitted depending on the compensation scheme or the configuration of the circuit.

The switching transistor SW is operated so that the data voltage supplied through the first data line DL1 is stored in the capacitor Cst in response to the scan signal supplied through the first scan line GL1. The driving transistor DR operates so that a driving current flows between the first power supply line EVDD (high potential voltage) and the second power supply line EVSS (low potential voltage) in accordance with the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light in accordance with the driving current generated by the driving transistor DR.

The compensation circuit CC is a circuit added in the sub-pixel to compensate the threshold voltage of the driving transistor DR and the like. The compensation circuit CC is composed of one or more transistors. The configuration of the compensation circuit CC varies greatly according to the external compensation method, so that an example related thereto will be omitted.

The display panel of the organic light emitting display device can drive the display region by dividing the display region into blocks (a plurality of scan lines). The method of driving the display panel in this manner is referred to as a block driving method. The block driving method includes a scan time varying method for controlling the switching transistor and a light emission time varying method for controlling the light emitting control transistor. A method of controlling the light emitting control transistor will be briefly described as follows.

FIG. 3 is a schematic circuit configuration example of a sub-pixel capable of controlling a light emission time, and FIG. 4 is an exemplary waveform diagram of a light emission control signal.

As shown in Fig. 3, one sub-pixel further includes a light emission control transistor EM. The emission control transistor EM serves to control the emission time of the organic light emitting diode OLED.

The emission control transistor EM is located between the driving transistor DR and the organic light emitting diode OLED as shown in FIG. 3A, or the first power supply line EVDD and the driving transistor DR, As shown in FIG.

4, the emission control transistor EM controls the emission time EMT of the organic light emitting diode OLED to a first time corresponding to the emission control signal applied to the gate electrode (FIG. 4A) (B in Fig. 4) to a second time longer than the first time.

The block driving method has effects such as reduction of power consumption of display panel, securing of sensing time, improvement of compensation accuracy, improvement of dynamic contrast ratio, improvement of Moving Picture Response Time (MPRT), and BDI (Black Data Insertion). However, the block driving method proposed in the related art has a problem that a brightness deviation occurs across the display panel. The problem of the prior art will be briefly described as follows.

≪ Background Art &

FIG. 5 is a data programming diagram for explaining a conventional driving method proposed in the prior art, FIG. 6 is a data programming diagram for explaining a conventional block driving method, FIG. 7 is a block diagram of a conventional driving method Fig.

As shown in FIG. 5, in the conventional driving method, a scan signal is sequentially output from the first scan line to the last scan line along the scan direction, and the data voltage is sequentially programmed according to the scan signal . Conventionally, the conventional driving method continues in the same manner not only in the first frame (1 Frame) but also in the second frame (2 frame) to the fourth frame (4 Frame).

As shown in FIG. 6, in the conventional block driving method, a plurality of scan lines are grouped into one block (for example, Bn-1) and the same data voltage is programmed into one group.

A plurality of blocks grouped by a plurality of scan lines are sequentially programmed in the same scan direction from the first group (e.g., Bn-1) to the last group (e.g., Bn + 1).

Conventionally, the block driving scheme continues in the same manner not only in the first frame (1 frame) but also in the second frame (2 frame) to the fourth frame (4 frame). In Fig. 6, "BD" means an area where block driving is performed within a frame. However, in the conventional block driving method, even if the same data voltage is input, a luminance difference may occur across the entire display panel.

6 and 7, the display region of the display panel includes a plurality of scan lines grouped into one block (e.g., Bn-1), but the scan signals are sequentially transferred from the first scan line to the last scan line . In Fig. 7, "A" is the luminance at the minimum emission time in the block, and "A x omega" is the luminance at the maximum emission time in the block.

Therefore, as shown in the example of the (N-1) th block Bn-1, even if the same data voltage is inputted in the same block, the light emission time EMT is the end point E of the block at the start point S of the block, . As can be seen from the boundary between the (N-1) -th block and the (N-1) th block Bn, the difference in the light emission time EMT in the block is maximized, .

Therefore, the block driving method proposed in the related art not only causes the luminance deviation (brightness gradation generation) of the entire display panel due to the difference in the light emission time in the block, maximizes the difference in the light emission time at the boundary between the blocks, Dim), and suggest improvements such as the following.

<Examples>

FIG. 8 is a data programming diagram for explaining a block driving method according to an embodiment of the present invention, and FIG. 9 is a view for explaining improvement of a block driving method according to an embodiment of the present invention.

8, in the block driving method according to the embodiment of the present invention, a plurality of scan lines are grouped into one block (for example, Bn-1), and the same data voltage is programmed into one group, And changes the programming direction of the data voltage.

A plurality of blocks grouped by a plurality of scan lines are sequentially arranged in a first scan direction and a second scan direction that are different from each other from a first group (e.g., Bn-1) to a last group (e.g., Bn + The voltage is programmed.

For example, the data voltage is programmed along the first scan direction while the Nth block Bn-1 is programmed with the data voltage along the second scan direction. The data voltage is programmed along the first scan direction while the (N + 2) -th block (not shown), which is the next block, is programmed with data The voltage is programmed.

According to the above-described programming method, a certain odd-numbered block is programmed with a data voltage along a first scan direction, while a specific even-numbered block is programmed with a data voltage along a second scan direction.

When the data voltage is programmed in the above manner during the first frame (1 Frame), the data voltage is programmed in the following manner during the second frame (2 Frame) in the following manner.

For example, the data voltage is programmed along the first scan direction while the data voltage is programmed along the second scan direction for the (N-1) th block Bn-1. The data voltage is programmed along the second scan direction in the (N + 1) th block Bn + 1, which is the next block, while the (N + 2) The voltage is programmed.

Hereinafter, the first scan direction and the second scan direction may be defined as a right direction and a left direction. The programming of the data voltage in the first scanning direction can be defined as forward programming (FPG), and the programming of the data voltage in the second scanning direction can be defined as reverse programming (RPG). However, the scanning direction and the programming direction may be defined as opposite to the above.

In the block driving method according to the embodiment, the direction in which the data voltage is programmed between the odd-numbered blocks and the even-numbered blocks is different, and the direction in which the data voltage is programmed is changed for each frame without continuing to be the same in all the frames. In Fig. 8, "BD" means an area where block driving is performed within a frame.

As a result, in the block driving method according to the embodiment, even when the same data voltage is input, a luminance difference or the like which has occurred throughout the display panel can be reduced.

As shown in Figs. 8 and 9, the display area of the display panel is grouped into a plurality of blocks, but forward programming (FPG) and reverse programming (RPG) are alternated for each block. In Fig. 9, "A" is the luminance at the minimum emission time in the block, and "A x omega" is the luminance at the maximum emission time in the block.

As can be seen from the figure, if the data voltage programming direction between the odd-numbered blocks (for example, Bn-1, Bn + 1) and the even-numbered blocks Bn is alternated, the maximum of the emission time EMT Since the deviation is canceled (based on the same data input), it is possible to eliminate or reduce the luminance deviation. That is, when the programming direction is alternated between the blocks, a luminance smoothing effect is generated between the blocks, so that the brightness deviation level is relaxed.

In addition, since the data voltage programming direction between the frames alternates with the alternation of the data voltage programming direction between the blocks, the deviation between the frames is gradated. That is, when the programming directions are alternated between frames, the luminance deviations are cumulatively added so that the perceived luminance accumulated in the eyes of the user can be made similar / equal to each other, so that a relatively uniform luminance display is possible. When the same data voltage is programmed, luminance opposite to each other appears in at least two adjacent frames (see 1 Frame and 2 Frame in Fig. 9).

Meanwhile, the above-described embodiment is provided based on the following comparative example. Differences between the comparative example and the embodiment will be described as follows.

FIG. 10 is a data programming diagram for explaining a block driving method according to a comparative example, and FIG. 11 is a data programming diagram for explaining a block driving method according to an embodiment.

As shown in FIG. 10A, the block driving method according to the comparative example performs forward programming (FPG) on all the blocks Bn-1 to Bn + 1 during the first frame (1 frame) (RPG) to all the blocks Bn-1 to Bn + 1 during the frame (2 frames). That is, the comparative example alternates the data voltage programming direction for each frame.

In the block driving method according to the comparative example, a difference in light emission time (EMT) occurs at the boundary between the blocks. As a result, as shown in the luminance and position graph of FIG. 10B, a luminance step between blocks occurs in the comparative example.

As shown in Fig. 11 (a), the block driving method according to the embodiment alternates the programming direction of the data voltage between the blocks during forward programming (FPG) and backward programming (RPG) during the first frame Reverse programming (RPG) and forward programming (FPG) of the data voltage programming direction between blocks for 2 frames (2 Frames). That is, the embodiment can provide a data voltage programming direction between frames with an alternation, in which the data voltage programming direction between blocks is reversed and forward (or forward and backward, or can not be defined to define the direction, but can be expressed in the first direction and the second direction) Alternate with the previous one.

In the block driving method according to the embodiment, the light emission time (EMT) is the same at the boundary between the blocks. As a result, as shown in the luminance and position graph of FIG. 11 (b), the luminance step between the blocks is removed in the embodiment.

Therefore, the embodiment can cancel out the maximum deviation of the emission time (EMT) occurring at the boundary between the blocks in the control method of the spatial programming direction, and the luminance deviation between the frames becomes gradation, It becomes. In addition, the embodiment may alternate the data voltage programming direction per frame with the alternation of the data voltage programming direction between the blocks, and may further randomly vary the data voltage programming direction per block and frame.

FIG. 12 is a diagram illustrating the arrangement of a scan driver for implementing an embodiment of the present invention, FIG. 13 is an internal configuration example of one scan driver, FIG. Fig. 7 is a waveform diagram showing output characteristics of a signal; Fig.

As shown in FIG. 12, the embodiment of the present invention includes, on the left and right sides of the display panel 150, alternating data voltage programming directions for each frame with alternating data voltage programming directions between blocks in the manner described above And the scan drivers 140L and 140R, respectively. Although the left scan driver 140L and the right scan driver 140R disposed on the left and right sides of the display panel 150 are shown one by one, they are arranged in a plurality of stages and have a dependent connection relationship between the stages.

13, the scan driver 140 includes a first logic circuit 141, a first shift register 143, a second shift register 144, a second logic circuit 146, a level shifter 147 And a gate line driver 148.

The scan driver 140 includes a terminal receiving the start pulses GSP and VSP, a terminal receiving the shift clocks GSC and VSC, a terminal receiving the output control signal SHL, A terminal supplied with the second power supply voltage GND, a terminal supplied with the gate high voltage VGH, and a terminal supplied with the gate low voltage VGL.

The scan driver 140 generates scan signals based on the shift clocks GSC and VSC and the start pulses GSP and VSP. The scan driver 140 varies the output direction of the scan signal according to the output control signal SHL. The scan driver 140 is driven based on the first power supply voltage VCC and the second power supply voltage GND. The scan driver 140 raises the level of the pulse signals generated by the first and second shift registers 143 and 144 based on the gate high voltage VGH and the gate low voltage VGL.

The first and second logic circuit units 141 and 146 set driving conditions of the scan driver 140 and control an internal circuit based on various signals supplied from the outside. The first and second shift registers 143 and 144 generate pulse signals based on the shift clocks GSC and VSC and the start pulses GSP and VSP under the control of the first logic circuit unit 141. The start pulses GSP and VSP include a plurality of start pulses GSP_A1, GSP_B1, GSP_A2, GSP_B2, VSP_A1, VSP_B1, VSP_A2 and VSP_B2 having different phases.

The level shifter 147 raises the levels of the pulse signals supplied from the first and second shift registers 143 and 144 under the control of the second logic circuit section 146 and outputs them as scan signals. The gate line driver 148 drives the scan signals output through the output terminals X1 to Xxxx. Quot; xxx " meaning the number of output terminals X1 to Xxxx depends on the number of scan lines arranged on the display panel.

13 and 14, the scan driver 140 controls the start direction of the start pulse GSP in response to an output control signal SHL supplied from the outside.

For example, when the output control signal for the forward output is inputted as shown in FIG. 14A, the scan driver 140 changes the driving condition such that the start pulse GSP starts from the left side. In this case, the scan driver 140 sequentially outputs the first scan signals (# 1 1st Gout) to the L scan signals (# 1 Last Gout) that form a logic high from the left direction. The scan signal in the first scan direction is a forward scan signal and forms a condition for programming the data voltage in the forward direction.

 As another example, when the output control signal for the reverse output is inputted as shown in FIG. 14B, the scan driver 140 changes the driving condition such that the start pulse GSP starts from the right side. In this case, the scan driver 140 sequentially outputs the first scan signals (# 1 1st Gout) to the L scan signals (# 1 Last Gout) which form a logic high from the right direction. The scan signal in the second scan direction is a reverse scan signal and forms a condition for programming the data voltage in the reverse direction.

FIG. 15 is a circuit diagram illustrating a scan driver and a scan direction controller, and FIG. 16 is a waveform diagram illustrating output characteristics of a scan signal according to the operation of the scan direction controller.

15, the embodiment of the present invention includes left and right scan drivers 140L1 to 140L3 (not shown) for alternating the data voltage programming direction per frame together with the alternation of the data voltage programming direction between the blocks in the manner as described above And 140R1 to 140R3, respectively, are arranged in the left and right scan direction control units 160L1 to 160L3 and 160R1 to 160R3, respectively.

The first left scan driver 140L1 is paired with the first left scan direction controller 160L1 and the second left scan driver 140L2 is paired with the second left scan direction controller 160L2, The driving unit 140L3 is paired with the third left scan direction control unit 160L3. The first to third left scan direction controllers 160L1 to 160L3 may be turned on or off in response to the first to third output control signals SH_ # 1 to SH_ # 3, but are not limited thereto.

The first right scan driver 140R1 is paired with the first right scan direction controller 160R1 and the second right scan driver 140R2 is paired with the second right scan direction controller 160R2, The driver 140R3 is paired with the third right scan direction controller 160R3. The first to third right scan direction controllers 160R1 to 160R3 may be turned on or off according to the inverted first to third output control signals / SH_ # 1 to / SH_ # 3, It does not.

Hereinafter, the configuration and operation of the circuit will be described in detail with reference to FIGS. 15 and 16, based on the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3. In FIG. 16, the scan signals are outputted so as to perform forward programming (FPG), reverse programming (RPG), and forward programming (FPG) on a block-by-block basis. However, this is for the purpose of showing the change of the scan signal due to the operation of the scan direction controllers 160L1 to 160L3 and 160R1 to 160R3, and is therefore merely for reference.

The first left scan driver 140L1 controls the first to Jth scan lines of the display panel 150. [ The second left scan driver 140L2 positioned at the rear end of the first left scan driver 140L1 controls the (J + 1) th to (K) th scan lines of the display panel 150. The third left scan driver 140L3 positioned at the rear end of the second left scan driver 140L2 controls the (K + 1) th to (L) th scan lines of the display panel 150. [

The first left scan direction controller 160L1 may be defined as a front end (not shown but may be defined as a dummy left scan driver) and a rear end (a second left scan driver shown in the drawing) of the first left scan driver 140L1 The start pulses GSP1 and GSP2 transmitted from the sustain pulses GSP1 and GSP2.

The first left scan direction controller 160L1 includes a first A transistor T1, a first B transistor / T1, a second A transistor T2 and a second B transistor / T2. The first and second transistors T1 and T2 may have a driving condition (turn on / off) opposite to the first and / or second transistor T1 and / T2. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be changed randomly for each block and frame.

The first transistor T1 and the second transistor T2 operate so that the first left scan driver 140L1 can sequentially output a logic high scan signal from the left direction. That is, the first transistor T1 and the second transistor T2 are turned on in response to the input of the start pulses GSP1 and GSP2 so that the first left scan driver 140L1 can perform forward programming (FPG) through the scan lines supervised by the first left scan driver 140L1. Direction.

Alternatively, the first B transistor / T1 and the second B transistor / T2 operate so that the first left scan driver 140L1 can sequentially output a logic high scan signal from the right direction. That is, the first B transistor / T1 and the second B transistor / T2 start pulses GSP1 and GSP2 to enable reverse programming (RPG) through the scan lines supervised by the first left scan driver 140L1. As shown in FIG.

The second left scan direction controller 160L2 may be defined as a previous stage (which may be defined as a first left scan driver) and a succeeding stage (which may be defined as a third left scan driver shown in the drawing) of the second left scan driver 140L2, And controls the input direction of the start pulses GSP1 and GSP2.

The second left scan direction controller 160L2 includes a third transistor T3, a third transistor B3, a fourth transistor A4 and a fourth transistor B4. The third and fourth transistors T3 and T4 may have opposite driving conditions (turn on / off) as the third and fourth transistors T3 and / T4. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be changed randomly for each block and frame.

The third transistor T3 and the fourth transistor A4 operate so that the second left scan driver 140L2 can sequentially output a logic high scan signal from the left direction. That is, the third transistor T3 and the fourth transistor T4 are turned on in response to the input of the start pulses GSP1 and GSP2 to enable forward programming (FPG) through the scan lines supervised by the second left scan driver 140L2 Direction.

Alternatively, the third transistor (/ T3) and the fourth transistor (/ T4) operate so that the second left scan driver 140L2 can sequentially output a logic high scan signal from the right direction. That is, the third transistor T3 and the fourth transistor T4 turn on the start pulses GSP1 and GSP2 to enable the reverse programming RPG through the scan lines supervised by the second left scan driver 140L2. As shown in FIG.

The third left scan direction controller 160L3 may be defined as a front end of the third left scan driver 140L3 (which may be defined as a second left scan driver) and a rear end (not shown as a fourth left scan driver) The start pulses GSP1 and GSP2 transmitted from the sustain pulses GSP1 and GSP2.

The third left scan direction controller 160L3 includes a fifth A transistor T5, a fifth B transistor T5, a sixth A transistor T6 and a sixth transistor T6. The fifth and sixth transistors T5 and T6 may have opposite drive conditions (turn on / turn off) to the fifth transistor / T5 and the sixth transistor / T6. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be changed randomly for each block and frame.

The fifth transistor (T5) and the sixth transistor (T6) operate so that the third left scan driver 140L3 can sequentially output a logic high scan signal from the left. That is, the fifth transistor T5 and the sixth transistor T6 are turned on in response to the input of the start pulses GSP1 and GSP2 to enable forward programming (FPG) through the scan lines supervised by the third left scan driver 140L3. Direction.

Alternatively, the fifth transistor (/ T5) and the sixth transistor (/ T6) operate so that the third left scan driver 140L3 can sequentially output a logic high scan signal from the right direction. That is, the fifth transistor (/ T5) and the sixth transistor (/ T6) start pulses GSP1 and GSP2 to enable reverse programming (RPG) through the scan lines supervised by the third left scan driver 140L3. As shown in FIG.

As described above, the first transistor T1 and the second transistor T2 each have a driving condition opposite to that of the first transistor T1 and the second transistor T2 (inversion driving) admit. The first transistor T1 and the second transistor T2 are forward scan signal control transistors and the first transistor T1 and the second transistor T2 are transistors for controlling the reverse scan signal. Transistors T3 to T6 and / T3 to / T6, which are not described below, also have the above driving conditions and uses.

The circuit configurations for the right scan drivers 140R1 to 140R3 and the right scan direction controllers 160R1 to 160R3 are the same as the configurations of the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 .

The right scan drivers 140R1 to 140R3 and the right scan direction controllers 160R1 to 160R3 are connected to the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3, The same operation can be performed.

However, the right scan drivers 140R1 to 140R3, the right scan direction controllers 160R1 to 160R3, the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 may perform different operations.

To this end, the left scan drivers 140L1 to 140L3 can receive the first output control signals SHL_ # 1 to SHL_ # 3, and the right scan drivers 140R1 to 140R3 can receive the first output control signals SHL_ # The first to third inverted output control signals / SHL_ # 1 to / SHL_ # 3, which are inverted from the first to third output control signals SHL_ # 1 to SHL_ # 3, But is not limited thereto.

If the left scan driving units 140L1 to 140L3 and the left scan direction control units 160L1 to 160L3 are operated during the first frame, the right scan driving units 140R1 to 140R3 and the right scan direction control units 160R1 to 160R3 may be set to operate. That is, the left scan drivers 140L1 to 140L3, the left scan direction controllers 160L1 to 160L3, the right scan drivers 140R1 to 140R3, and the right scan direction controllers 160R1 to 160R3, It is possible to alternately drive each frame correspondingly.

As can be seen from the above description, the embodiment is based on the scan direction controllers (integrated definition 160) capable of bi-directionally controlling the start pulse (integrated definition in GSP) corresponding to the output control signal Alternating data voltage programming direction per frame with alternating data voltage programming direction between blocks.

In addition, one of the transistors of the scan direction control unit (for example, a transistor for transferring a start pulse so that the scan driver can be controlled in a forward direction like T1) is connected to the output control signal line through a gate electrode, And the second electrode is connected to the first input terminal (forward control input terminal) of the rear stage scan driver. The other one of the transistors of the scan direction control unit (for example, a transistor for transferring a start pulse so as to control the scan driver in the reverse direction, such as / T1) is connected to the output control signal line and the output electrode of the scan driver And the second electrode is connected to the second input terminal (reverse control input terminal) of the rear stage scan driver.

Meanwhile, in order to drive the apparatus under the same conditions as the above-described embodiments, the timing controller and the scan driver may be configured as follows. The scan direction controller may be included in the scan driver, and only the scan driver is illustrated in the following description.

FIG. 17 is a schematic diagram illustrating a circuit configuration for controlling a scan driver based on an output control signal, and FIG. 18 is a diagram illustrating an example of a start pulse for each output control signal.

As shown in FIG. 17, the scan driver 140 may receive an output control signal from the timing controller 120. To this end, the timing controller 120 and the scan driver 140 are electrically connected by the output control signal line SHL.

The output control signal transmitted through the output control signal line SHL is an output control signal having a value of "000", "001", "010", "011", "100", "101", "110" Quot ;, but the number of bits and the programming direction of the start pulse are not limited thereto. Hereinafter, operations related to the scan driver and the scan direction controller will be described by taking two cases as an example.

<Reverse Programming>

Referring to FIG. 15 and FIG. 18 together, an example of outputting "000" through the output control signal line SHL will be described as follows.

The flow of the start pulse has the order of GSP1 -> GSP2_1 -> GSP1_1 -> GSP2_2 -> GSP1_2 -> GSP2_3 -> GSP1_3 -> GSP2. / T1, / T2, / T3, / T4, / T5 and / T6 are turned on to follow this flow.

As can be seen from the flow and the operation of the apparatus described above, when "000" is outputted through the output control signal line SHL, 140L1, 140L2, and 140L3 output a scan signal for performing reverse programming.

<Forward Programming>

Referring to FIG. 15 and FIG. 18 together, an example in which "111" is outputted through the output control signal line SHL will be described as follows.

The flow of the start pulse has the order of GSP1 -> GSP1_1 -> GSP2_1 -> GSP1_2 -> GSP2_2 -> GSP1_3 -> GSP2_3 -> GSP2. T1, T2, T3, T4, T5, and T6 are turned on to follow this flow.

As can be seen from the flow described above and the operation of the apparatus, when "111" is outputted through the output control signal line (SHL), 140L1, 140L2 and 140L3 output a scan signal for forward programming.

As described above, the present invention provides an electroluminescent display device and a method of driving the same, which can relatively uniformly express brightness by a driving method capable of eliminating the brightness step between blocks and cumulatively adding luminance deviation. In addition, the present invention provides a block driving method capable of reducing luminance deviation, which can reduce power consumption of a display panel, secure sensing time and improve compensation accuracy, improve dynamic contrast ratio, improve Moving Picture Response Time (MPRT) BDI (Black Data Insertion) and the like can be performed.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

110: image processor 120: timing controller
130: Data driver 140:
150: display panel 160: power supply unit
RPG: Reverse Programming FPG: Forward Programming
GSP, VSP: Start pulses SHL: Output control signal
160L1 to 160L3, 160R1 to 160R3: scan direction control units
EMT: emission time

Claims (10)

A display panel for displaying an image;
A data driver for supplying a data voltage to the display panel; And
And a scan driver for supplying a scan signal to the display panel,
Wherein the display panel receives the scan signal and the data voltage in a block unit of a display area, the data voltage programming direction between the blocks is alternated in the first direction and the second direction, and the data voltage programming direction between the frames is reversed So as to be alternately turned on and off. The method according to claim 1,
And a scan direction control unit for changing the programming direction of the data voltage. 3. The method of claim 2,
The scan direction control unit
And controls a start direction of a start pulse supplied to the scan driver. The method of claim 3,
The scan direction control unit
Wherein the scan driver outputs a forward scan signal or outputs a reverse scan signal. The method of claim 3,
The scan direction control unit
And controls the flow of a start pulse input / output from the scan driver. The method of claim 3,
The scan direction control unit
And a transistor that operates in response to an output control signal supplied from the outside. The method according to claim 6,
The transistors
The transistors for forward scan signal control, and the transistors for reverse scan signal control. 8. The method of claim 7,
The reverse scan signal control transistors
And the forward scan signal control transistors are invertedly driven. There is provided a driving method of an electroluminescent display device in which a display area of a display panel is defined in units of blocks and a scan signal and a data voltage are inputted to perform block-
Programming a data voltage in a first direction for a first block defined in the display panel during a first frame interval;
Programming a data voltage in a second direction for a second block defined in the display panel during the first frame period; And
And changing a programming direction for the first block and the second block during the second frame period. 10. The method of claim 9,
When the same data voltage is applied to the display panel during the first frame and the second frame,
Wherein the first frame and the second frame exhibit brightness opposite to each other in the first frame and the second frame.

Images