KR102316100B1 - Light Emitting Display Device and Driving Method thereof - Google Patents

Abstract

The present invention provides an electroluminescent display device including a display panel, a data driver, and a scan driver. The display panel displays an image. The data driver supplies a data voltage to the display panel. The scan driver supplies a scan signal to the display panel. The display panel receives a scan signal and a data voltage in units of blocks of the display area, and the data voltage programming direction between blocks is alternated in the first direction and the second direction and the data voltage programming direction between frames is alternated to be opposite to the previous one. .

Description

Electroluminescent display device and driving method thereof

The present invention relates to an electroluminescent display device and a driving method thereof.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of various types of display devices such as an electroluminescent display device, a liquid crystal display device, and a plasma display device is increasing.

The display device includes a display panel including a plurality of sub-pixels, a driving unit for driving the display panel, and a power supply unit for supplying power to the display panel. The driver includes a scan driver that supplies a scan signal (or a gate signal) to the display panel and a data driver that supplies a data signal to the display panel.

In the electroluminescent display device, when a scan signal and a data signal are supplied to the sub-pixels, the light emitting diodes of the selected sub-pixels emit light, so that an image can be displayed. The light emitting diode is implemented based on an organic material or is implemented based on an inorganic material.

The electroluminescent display device may apply a block driving method in which the display area of the display panel is divided into blocks and driven. The block driving method has effects such as reducing power consumption of the display panel, securing sensing time and improving compensation accuracy, improving dynamic contrast ratio, improving moving picture response time (MPRT), and improving black data insertion (BDI). However, the conventionally proposed block driving method has improvements for performance improvement, such as luminance variation across the display panel.

SUMMARY OF THE INVENTION The present invention for solving the problems of the background art is to provide a block driving method capable of expressing luminance relatively uniformly while removing a luminance step between blocks. In addition, it is to provide a block driving method capable of reducing the luminance deviation.

As a means for solving the above problems, the present invention provides an electroluminescent display device including a display panel, a data driver, and a scan driver. The display panel displays an image. The data driver supplies a data voltage to the display panel. The scan driver supplies a scan signal to the display panel. The display panel receives a scan signal and a data voltage in units of blocks of the display area, and the data voltage programming direction between blocks is alternated in the first direction and the second direction and the data voltage programming direction between frames is alternated to be opposite to the previous one. .

It may include a scan direction control unit for changing the data voltage programming direction.

The scan direction controller may control a start direction of a start pulse supplied to the scan driver.

The scan direction controller may control the scan driver to output a forward scan signal or a reverse scan signal.

The scan direction controller may control the flow of start pulses input/output from the scan driver.

The scan direction control unit may include transistors operating in response to an output control signal supplied from the outside.

The transistors may include transistors for controlling a forward scan signal and transistors for controlling a reverse scan signal.

The transistors for controlling the reverse scan signal may be driven inversely with the transistors for controlling the forward scan signal.

In another aspect, the present invention provides a method of driving an electroluminescent display device in which a display area of a display panel is defined in units of blocks, and a scan signal and a data voltage are input to drive the display in units of blocks. A method of driving an electroluminescent display device includes: programming a data voltage in a first direction with respect to a first block defined on a display panel during a first frame period; programming the data voltage in two directions; and changing programming directions for the first block and the second block during the second frame period.

When the same data voltage is applied to the display panel during the first frame and the second frame, luminance opposite to each other may appear for each block in the first frame and the second frame.

The present invention has the effect of providing an electroluminescent display device capable of expressing relatively uniform luminance by a driving method capable of accumulating and summing luminance deviations while eliminating a luminance step between blocks, and a driving method thereof. In addition, the present invention provides a block driving method capable of reducing luminance deviation, reducing power consumption of a display panel, securing sensing time and improving compensation accuracy, improving dynamic contrast ratio, improving moving picture response time (MPRT), There is an effect that can perform Black Data Insertion (BDI) and the like.

1 is a schematic block diagram of an organic light emitting display device;
2 is a schematic circuit configuration diagram of a sub-pixel;
3 is a schematic circuit configuration diagram of a sub-pixel capable of controlling a light emission time;
4 is an exemplary diagram of a waveform of a light emission control signal;
5 is a data programming diagram for explaining a conventionally proposed general driving method;
6 is a data programming diagram for explaining a block driving method proposed in the prior art;
7 is a diagram for explaining a problem of a block driving method proposed in the prior art;
8 is a data programming diagram for explaining a block driving method according to an embodiment of the present invention.
9 is a view for explaining an improvement point of a block driving method according to an embodiment of the present invention;
10 is a data programming diagram for explaining a block driving method according to a comparative example;
11 is a data programming diagram for explaining a block driving method according to an embodiment;
12 is an exemplary arrangement view of a scan driver for implementing an embodiment of the present invention.
13 is an exemplary diagram of an internal configuration of one scan driving unit;
14 is a waveform diagram illustrating output characteristics of a scan signal according to characteristics of an output control signal applied to a scan driver;
15 is an exemplary circuit configuration diagram specifically illustrating a scan driver and a scan direction controller;
16 is a waveform diagram illustrating output characteristics of a scan signal according to an operation of a scan direction control unit;
17 is an exemplary diagram schematically illustrating a circuit configuration for controlling a scan driver based on an output control signal;
18 is an exemplary view showing the flow of start pulses for each output control signal.

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

The electroluminescent display device described below may be implemented as a TV, an image player, a personal computer (PC), a home theater, a smart phone, a virtual reality device (VR), and the like. In addition, as an electroluminescent display device to be described below, an organic light emitting display device implemented based on an organic light emitting diode (light emitting device) will be described as an example. However, the electroluminescent display device described below may be implemented based on an inorganic light emitting diode.

The thin film transistor of the electroluminescent display device described below may be named as a source electrode and a drain electrode or a drain electrode and a source electrode depending on the type except for the gate electrode. To avoid limitation, the first electrode and the second electrode explained as

1 is a schematic block diagram of an organic light emitting display device, and FIG. 2 is a schematic circuit configuration diagram of a sub-pixel.

As shown in FIG. 1 , the organic light emitting display device includes an image processing unit 110 , a timing control unit 120 , a data driving unit 130 , a scan driving unit 140 , a display panel 150 , and a power supply unit 170 . Included.

The image processing unit 110 outputs a data enable signal DE along with the data signal DATA supplied from the outside. The image processing unit 110 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE, but these signals are omitted for convenience of description.

The timing controller 120 receives the data signal DATA from the image processing unit 110 as well as a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 130 based on the driving signal. to output

The data driver 130 samples and latches the data signal DATA supplied from the timing controller 120 in response to the data timing control signal DDC supplied from the timing controller 120 , and converts it into a gamma reference voltage and outputs it. . The data driver 130 outputs a data voltage through the data lines DL1 to DLn. The data driver 130 may be formed in the form of an integrated circuit (IC).

The scan driver 140 outputs a scan signal in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 140 outputs a scan signal through the scan lines GL1 to GLm. The scan driver 140 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 in the form of a gate in panel.

The power supply unit 170 outputs a high potential voltage, a low potential voltage, and the like. The high potential voltage and low potential voltage output from the power supply unit 170 are supplied to the display panel 150 . The high potential voltage is supplied to the display panel 150 through the first power line EVDD, and the low potential voltage is supplied to the display panel 150 through the second power line EVSS.

The display panel 150 displays an image corresponding to the data voltage and scan signal supplied from the data driver 130 and the scan driver 140 , and power supplied from the power supply unit 170 . The display panel 150 includes sub-pixels SP that operate to display an image.

The sub-pixels SP include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The sub-pixels SP may have one or more different emission areas according to emission characteristics.

As shown in FIG. 2 , one sub-pixel includes a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light emitting diode (OLED). The compensation circuit CC may be omitted depending on a compensation scheme or circuit configuration.

The switching transistor SW performs a switching operation such that the data voltage supplied through the first data line DL1 is stored in the capacitor Cst in response to the scan signal supplied through the first scan line GL1 . The driving transistor DR operates so that a driving current flows between the first power line EVDD (high potential voltage) and the second power line EVSS (low potential voltage) according to the data voltage stored in the capacitor Cst. The organic light emitting diode OLED operates to emit light according to a driving current formed by the driving transistor DR.

The compensation circuit CC is a circuit added to the sub-pixel to compensate for the threshold voltage of the driving transistor DR. The compensation circuit CC is composed of one or more transistors. Since the configuration of the compensation circuit CC varies greatly depending on the external compensation method, an example related thereto will be omitted.

The display panel of the organic light emitting display device can be driven by dividing the display area into blocks (units of a plurality of scan lines). A method of driving the display panel in this way is referred to as a block driving method. The block driving method includes a scan time variable method for controlling a switching transistor, a light emission time variable method for controlling a light emission control transistor, and the like. A method of controlling the emission control transistor will be briefly described as follows.

3 is a schematic circuit configuration diagram of a sub-pixel capable of controlling the emission time, and FIG. 4 is an illustration of a waveform of the emission control signal.

As shown in FIG. 3 , one sub-pixel further includes an emission control transistor EM. The emission control transistor EM serves to control the emission time of the organic light emitting diode OLED.

The emission control transistor EM is positioned between the driving transistor DR and the organic light emitting diode OLED as shown in FIG. 3(a) or between the first power line EVDD and the driving transistor DR as shown in FIG. 3(b). can be located between

As shown in FIG. 4 , the emission control transistor EM controls the emission time EMT of the organic light emitting diode OLED to a first time in response to the emission control signal applied to the gate electrode (FIG. 4a). Alternatively, the second time period longer than the first time period may be controlled (FIG. 4 b).

The block driving method has effects such as reducing power consumption of the display panel, securing sensing time and improving compensation accuracy, improving dynamic contrast ratio, improving moving picture response time (MPRT), and improving black data insertion (BDI). However, the conventionally proposed block driving method has a problem in that a luminance deviation occurs throughout the display panel. The problems of the prior art will be briefly described as follows.

<Prior art>

5 is a data programming diagram for explaining a conventionally proposed general driving method, FIG. 6 is a data programming diagram for explaining a conventionally proposed block driving method, and FIG. 7 is a problem of a conventionally proposed block driving method It is a drawing for explaining.

As shown in FIG. 5 , a conventional driving method sequentially outputs a scan signal from a first scan line to a last scan line along a scan direction and sequentially programs a data voltage according to the scan signal. . The conventionally proposed general driving method continues in the same manner not only in the first frame, but also in the second frames to the fourth frames.

As shown in FIG. 6 , in the conventionally proposed block driving method, a plurality of scan lines are grouped into one block (eg, Bn-1) and the same data voltage is programmed into the group.

In the plurality of blocks grouped by the plurality of scan lines, data voltages are sequentially programmed from the first group (eg, Bn-1) to the last group (eg, Bn+1) along the same scan direction.

The conventionally proposed block driving method continues in the same manner not only in the first frame but also in the second frame 2 to the fourth frame 4 frames. In FIG. 6 , “BD” refers to a region in which block driving is performed within a frame. However, in the conventionally proposed block driving method, a luminance difference may occur across the display panel even when the same data voltage is input. This will be described as follows.

As shown in FIGS. 6 and 7 , in the display area of the display panel, a plurality of scan lines are grouped into one block (eg, Bn-1), but the scan signal is sequential from the first scan line to the last scan line. is supplied with In Fig. 7, "A" is the luminance at the minimum light emission time in the block, and "Axω" is the brightness at the maximum light emission time in the block.

For this reason, as can be seen in the example of the N-1th block (Bn-1), even if the same data voltage is input in the same block, the emission time (EMT) varies from the starting point (S) of the block to the ending point (E) of the block. becomes shorter as And, as can be seen in the boundary between the N-1th block (Bn-1) and the Nth block (Bn), the difference in emission time (EMT) within the block maximizes the difference in emission time, and the “luminance step between blocks” region will form

Therefore, the conventionally proposed block driving method not only induces luminance deviation (luminance gradation) across the display panel due to the difference in luminance time within the block, but also maximizes the luminescence time difference at the boundary between blocks, resulting in block dim (block dimming) according to the luminance deviation between blocks. Dim), there are improvements to improve performance, so the following methods are proposed.

<Example>

8 is a data programming diagram for explaining a block driving method according to an embodiment of the present invention, and FIG. 9 is a diagram for explaining an improvement of the block driving method according to an embodiment of the present invention.

As shown in FIG. 8 , in the block driving method according to the embodiment of the present invention, a plurality of scan lines are grouped into one block (eg, Bn-1) and the same data voltage is programmed in the grouped group, but for each block. Change the programming direction of the data voltage.

A plurality of blocks grouped by a plurality of scan lines sequentially data from a first group (eg, Bn-1) to a last group (eg, Bn+1) along different first and second scan directions. voltage is programmed.

For example, the data voltage is programmed in the N-th block Bn-1 in the first scan direction while the data voltage in the N-th block Bn is programmed in the second scan direction. In the next block, the N+1th block (Bn+1), the data voltage is programmed along the first scan direction, while the next block, the N+2th block (not shown), has data along the second scan direction. voltage is programmed.

According to the above-described programming method, data voltages are programmed in specific odd-numbered blocks along the first scan direction, but data voltages are programmed in specific even-numbered blocks in the second scan direction.

When the data voltage is programmed in the above manner during the first frame (1 Frame), the data voltage is programmed in the following manner during the second frame (2 Frame).

For example, the data voltage is programmed in the N-th block Bn-1 along the second scan direction while the data voltage is programmed in the N-th block Bn along the first scan direction. In the next block, the N+1th block (Bn+1), the data voltage is programmed along the second scan direction, while the next block, the N+2th block (not shown), has data along the first scan direction. voltage is programmed.

Hereinafter, the first scan direction and the second scan direction may be defined as a right direction and a left direction. In addition, programming of the data voltage in the first scan direction may be defined as forward programming (FPG), and programming of the data voltage in the second scan direction may be defined as reverse programming (RPG). However, the scan direction and the programming direction may be defined opposite to the above.

In the block driving method according to the embodiment, the direction in which the data voltage is programmed is different between the odd blocks and the even blocks, and the direction in which the data voltage is programmed does not continue to be the same in all frames but is changed for each frame. In FIG. 8 , “BD” refers to a region in which block driving is performed within a frame.

As a result, the block driving method according to the embodiment can reduce a luminance difference occurring across the display panel even when the same data voltage is input. This will be described as follows.

8 and 9 , the display area of the display panel is grouped into a plurality of blocks, but forward programming (FPG) and reverse programming (RPG) alternate for each block. In Fig. 9, "A" is the luminance at the minimum light emission time in the block, and "Axω" is the brightness at the maximum light emission time in the block.

As can be seen from the illustrated figure, when the data voltage programming directions between odd blocks (eg, Bn-1, Bn+1) and even blocks (Bn) are alternated, the maximum emission time (EMT) occurring at the boundary between blocks is increased. Since the deviation is canceled (based on the same data input), the perception of the luminance deviation can be eliminated or reduced. That is, if the programming direction is alternated between blocks, a luminance smoothing effect between blocks is expressed, and the level of perception of luminance deviation is alleviated.

In addition, since the data voltage programming direction between blocks is alternated and the data voltage programming direction between frames is reversed as before, the deviation between frames is gradated. That is, if the programming direction is alternated between frames, the luminance deviations are cumulatively summed so that the perceived luminance accumulated in the user's eyes can be similar/same, so that a relatively uniform luminance expression is possible. When the same data voltage is programmed, opposite luminance appears for each block in at least two adjacent frames (see 1 Frame and 2 Frame in FIG. 9 ).

On the other hand, the above-described embodiment was prepared based on the following comparative example, the difference between the comparative example and the embodiment will be described as follows.

10 is a data programming diagram illustrating a block driving method according to a comparative example, and FIG. 11 is a data programming diagram illustrating a block driving method according to an embodiment.

As shown in FIG. 10A , in the block driving method according to the comparative example, forward programming (FPG) is performed on all blocks Bn-1 to Bn+1 during a first frame, and a second During frame 2, reverse programming (RPG) is performed on all blocks Bn-1 to Bn+1. That is, the comparative example alternates the data voltage programming direction for each frame.

In the block driving method according to the comparative example, a difference in emission time (EMT) occurs at the boundary between blocks. As a result, in the comparative example, as can be seen from the luminance and position graph of FIG.

11 (a), the block driving method according to the embodiment alternates the data voltage programming direction between blocks into forward programming (FPG) and reverse programming (RPG) during a first frame, and During two frames, the data voltage programming direction between blocks alternates between reverse programming (RPG) and forward programming (FPG). That is, in the embodiment, the data voltage programming direction between the frames is reversed and the forward direction (or the forward direction and the reverse direction, or the first direction and the second direction may be expressed in order not to limit the direction) alternating the data voltage programming direction between blocks. is reversed as before.

In the block driving method according to the embodiment, the emission time (EMT) is the same at the boundary between blocks. As a result, in the embodiment, as shown in the luminance and position graph of FIG. 11B , the luminance step between blocks is removed.

Therefore, the embodiment can offset the maximum deviation in emission time (EMT) occurring at the boundary between blocks by adjusting the spatial programming direction, as well as gradation of the luminance deviation between frames, so that a relatively uniform luminance expression is possible. becomes In addition, according to the embodiment, the data voltage programming direction may be changed for each frame along with the data voltage programming direction between blocks, and furthermore, the data voltage programming direction may be changed randomly for each block and frame.

12 is an exemplary arrangement diagram of a scan driver for implementing an embodiment of the present invention, FIG. 13 is an exemplary diagram of an internal configuration of one scan driver, and FIG. 14 is a scan according to the characteristics of an output control signal applied to the scan driver It is a waveform diagram showing the output characteristics of the signal.

As shown in FIG. 12 , in the embodiment of the present invention, the left and right sides of the display panel 150 are provided to alternate the data voltage programming direction for each frame together with the alternating data voltage programming direction between blocks in the same manner as described above. The scan drivers 140L and 140R are respectively disposed. Although the left scan driver 140L and the right scan driver 140R disposed on the left and right sides of the display panel 150 are illustrated one by one, they are disposed in the form of a plurality of stages, and each stage has a dependent connection relationship.

13 , the scan driver 140 includes a first logic circuit unit 141 , a first shift register 143 , a second shift register 144 , a second logic circuit unit 146 , and a level shifter 147 . ) and a gate line driver 148 .

The scan driver 140 includes a terminal receiving the start pulses GSP and VSP, a terminal receiving the shift clocks GSC and VSC, a terminal receiving the output control signal SHL, and a first power voltage VCC. It includes a terminal supplied with , a terminal supplied with the second power voltage GND, a terminal supplied with a gate high voltage VGH, and a terminal supplied with a gate low voltage VGL.

The scan driver 140 generates a scan signal based on the shift clocks GSC and VSC and the start pulses GSP and VSP. The scan driver 140 changes the output direction of the scan signal according to the output control signal SHL. The scan driver 140 is driven based on the first power voltage VCC and the second power voltage GND. The scan driver 140 increases the levels of the pulse signals generated by the first and second shift registers 143 and 144 based on the gate high voltage VGH and the gate low voltage VGL.

The first and second logic circuit units 141 and 146 set driving conditions of the scan driver 140 based on various signals supplied from the outside and control the internal circuits. The first and second shift registers 143 and 144 generate pulse signals based on the shift clocks GSC and VSC and the start pulses GSP and VSP under the control of the first logic circuit unit 141 . The start pulses GSP and VSP include a plurality of start pulses GSP_A1, GSP_B1, GSP_A2, GSP_B2, VSP_A1, VSP_B1, VSP_A2, and VSP_B2 having different phases.

The level shifter 147 raises the levels of the pulse signals supplied from the first and second shift registers 143 and 144 under the control of the second logic circuit unit 146 and outputs them as scan signals. The gate line driver 148 drives a scan signal output through the output terminals X1 to Xxxx. "xxx", which means the number of output terminals (X1 to Xxxx), varies depending on the number of scan lines arranged on the display panel.

13 and 14 , the scan driver 140 controls the start direction of the start pulse GSP in response to the output control signal SHL supplied from the outside.

For example, when an output control signal for forward output is input as shown in FIG. 14A , the scan driver 140 changes the driving condition so that the start pulse GSP starts from the left side. In this case, the scan driver 140 outputs a first scan signal #1 1st Gout to an L-th scan signal #1 Last Gout that sequentially form a logic high from the left. The scan signal in the first scan direction is a forward scan signal and forms a condition for programming the data voltage in the forward direction.

As another example, when an output control signal for reverse output is input as shown in FIG. 14B , the scan driver 140 changes the driving condition so that the start pulse GSP starts from the right side. In this case, the scan driver 140 outputs a first scan signal #1 1st Gout to an L-th scan signal #1 Last Gout that sequentially form a logic high from the right direction. The scan signal in the second scan direction is a reverse scan signal and forms a condition for programming the data voltage in the reverse direction.

15 is an exemplary circuit configuration diagram specifically illustrating a scan driver and a scan direction controller, and FIG. 16 is a waveform diagram illustrating output characteristics of a scan signal according to an operation of the scan direction controller.

As shown in FIG. 15 , in the embodiment of the present invention, the left and right scan drivers 140L1 to 140L3 are used to alternate the data voltage programming direction for each frame together with the data voltage programming direction between blocks in the same manner as described above. , 140R1 to 140R3, the left and right scan direction control units 160L1 to 160L3, 160R1 to 160R3 are respectively disposed.

The first left scan driver 140L1 is paired with the first left scan direction controller 160L1, the second left scan driver 140L2 is paired with the second left scan direction controller 160L2, and the third left scan The driving unit 140L3 is paired with the third left scan direction control unit 160L3. The first to third left scan direction controllers 160L1 to 160L3 may be turned on or off in response to the first to third output control signals SH_#1 to SH_#3, but are not limited thereto.

The first right scan driver 140R1 is paired with the first right scan direction controller 160R1, the second right scan driver 140R2 is paired with the second right scan direction controller 160R2, and the third right scan The driving unit 140R3 is paired with the third right scan direction control unit 160R3. The first to third right scan direction control units 160R1 to 160R3 may be turned on or off in response to the inverted first to third output control signals /SH_#1 to /SH_#3, but are limited thereto. doesn't happen

Hereinafter, with reference to FIGS. 15 and 16 , the configuration and operation of the circuit will be described in detail based on the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 . However, FIG. 16 illustrates that the scan signal is output to perform forward programming (FPG), reverse programming (RPG), and forward programming (FPG) for each block as an example. However, since this is to show the change of the scan signal by the operation of the scan direction controllers 160L1 to 160L3 and 160R1 to 160R3, it is for reference only.

The first left scan driver 140L1 controls the first to Jth scan lines of the display panel 150 . The second left scan driver 140L2 positioned at the rear end of the first left scan driver 140L1 controls the J+1th to Kth scan lines of the display panel 150 . The third left scan driver 140L3 positioned at the rear end of the second left scan driver 140L2 controls the K+1th to Lth scan lines of the display panel 150 .

The first left scan direction control unit 160L1 may be defined as a front end (not shown, but may be defined as a dummy left scan driver) and a rear end (the illustrated second left scan driver) of the first left scan driver 140L1. ) governs the input direction of the start pulses GSP1 and GSP2 transmitted from

The first left scan direction control unit 160L1 includes a transistor 1A (T1), a transistor 1B (/T1), a transistor 2A (T2), and a transistor 2B (/T2). The first A transistor T1 and the second A transistor T2 may have driving conditions (turn-on/turn-off) opposite to those of the first B transistor /T1 and the second B transistor /T2. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be randomly varied for each block and frame.

The first A transistor T1 and the second A transistor T2 operate so that the first left scan driver 140L1 sequentially outputs a logic high scan signal from the left direction. That is, the first A transistor T1 and the second A transistor T2 are input to the start pulses GSP1 and GSP2 so that forward programming (FPG) can be performed through the scan lines managed by the first left scan driver 140L1. control the direction

In contrast, the first B transistor /T1 and the second B transistor /T2 operate such that the first left scan driver 140L1 sequentially outputs a logic high scan signal from the right direction. That is, the first B transistor (/T1) and the second B transistor (/T2) receive start pulses GSP1 and GSP2 to perform reverse programming (RPG) through the scan lines managed by the first left scan driver 140L1. control the input direction.

The second left scan direction control unit 160L2 includes a front end (which may be defined as the illustrated first left scan driver) and a rear end (which may be defined as the illustrated third left scan driver) of the second left scan driver 140L2. It controls the input direction of the start pulses GSP1 and GSP2 transmitted from .

The second left scan direction control unit 160L2 includes a 3A transistor T3, a 3B transistor /T3, a 4A transistor T4, and a 4B transistor /T4. The 3A transistor T3 and the 4A transistor T4 may have driving conditions (turn on/off) opposite to those of the 3B transistor /T3 and the 4B transistor /T4. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be randomly varied for each block and frame.

The 3A transistor T3 and the 4A transistor T4 operate so that the second left scan driver 140L2 sequentially outputs a logic high scan signal from the left direction. That is, the 3A transistor T3 and the 4A transistor T4 input the start pulses GSP1 and GSP2 so that forward programming (FPG) can be performed through the scan lines managed by the second left scan driver 140L2. control the direction

In contrast, the third B transistor /T3 and the fourth B transistor /T4 operate so that the second left scan driver 140L2 sequentially outputs a logic high scan signal from the right direction. That is, the 3B transistor (/T3) and the 4B transistor (/T4) receive start pulses GSP1 and GSP2 to perform reverse programming (RPG) through the scan lines managed by the second left scan driver 140L2. control the input direction.

The third left scan direction control unit 160L3 may be defined as a front end (which may be defined as the illustrated second left scan driver) and a rear end (not illustrated as a fourth left scan driver) of the third left scan driver 140L3 ) governs the input direction of the start pulses GSP1 and GSP2 transmitted from

The third left scan direction control unit 160L3 includes a 5A transistor T5, a 5B transistor /T5, a 6A transistor T6, and a 6B transistor /T6. The 5A transistor T5 and the 6A transistor T6 may have driving conditions (turn on/off) opposite to those of the 5B transistor /T5 and the 6B transistor /T6. However, they may all have individually controlled driving conditions so that the data voltage programming direction can be randomly varied for each block and frame.

The 5A transistor T5 and the 6A transistor T6 operate such that the third left scan driver 140L3 sequentially outputs a logic high scan signal from the left direction. That is, the 5A transistor T5 and the 6A transistor T6 input the start pulses GSP1 and GSP2 so that forward programming (FPG) can be performed through the scan lines managed by the third left scan driver 140L3. control the direction

On the contrary, the 5B transistor /T5 and the 6B transistor /T6 operate so that the third left scan driver 140L3 sequentially outputs a logic high scan signal from the right direction. That is, the 5B transistor (/T5) and the 6th transistor (/T6) receive start pulses GSP1 and GSP2 to perform reverse programming (RPG) through the scan lines managed by the third left scan driver 140L3. control the input direction.

As can be seen from the above description, the first B transistor (/T1) and the second B transistor (/T2) are transistors having the opposite driving condition (reverse driving) to the first A transistor T1 and the second A transistor T2. admit. In addition, the first A transistor T1 and the second A transistor T2 are forward scan signal control transistors, and the 1B transistor /T1 and 2B transistor /T2 are reverse scan signal control transistors. Transistors T3 to T6 and /T3 to /T6 not described below also have the above driving conditions and uses.

The circuit configuration of the right scan drivers 140R1 to 140R3 and the right scan direction controllers 160R1 to 160R3 is the above-described configuration of the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3. refer to

The right scan drivers 140R1 to 140R3 and the right scan direction controllers 160R1 to 160R3 are the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 to solve the propagation delay of the scan signal. You can do the same operation as

However, the right scan drivers 140R1 to 140R3, the right scan direction controllers 160R1 to 160R3, and the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 may perform different operations.

To this end, the left scan drivers 140L1 to 140L3 may receive the first output control signal SHL_#1 to the third output control signal SHL_#3, and the right scan drivers 140R1 to 140R3 may The first inverted output control signal (/SHL_#1) to the third inverted output control signal (/SHL_#3) obtained by inverting the first output control signal (SHL_#1) to the third output control signal (SHL_#3) input may be received, but is not limited thereto.

In addition, if the left scan drivers 140L1 to 140L3 and the left scan direction controllers 160L1 to 160L3 operated during the first frame, the right scan drivers 140R1 to 140R3 and the right scan direction controllers ( 160R1 ~ 160R3) can be set to operate. That is, the left scan drivers 140L1 to 140L3, the left scan direction controllers 160L1 to 160L3, and the right scan drivers 140R1 to 140R3 and the right scan direction controllers 160R1 to 160R3 are in the programming direction of the data voltage. Correspondingly, it is possible to alternately drive for each frame.

As can be seen from the above description, the embodiment is based on the scan direction control units (integrated defined as 160) capable of bidirectional control of the start pulse (integrated defined as GSP) in response to the output control signal (integrated defined as SHL) The data voltage programming direction is alternated for each frame along with the alternating data voltage programming direction between blocks.

In addition, one of the transistors of the scan direction control unit (eg, a transistor that transmits a start pulse to forward control the scan driver like T1) has a gate electrode connected to an output control signal line, and a gate electrode connected to the output terminal of the previous scan driver. The first electrode is connected and the second electrode is connected to the first input terminal (forward control input terminal) of the rear-end scan driver. And the other one of the transistors of the scan direction control unit (eg, a transistor that transmits a start pulse so as to control the scan driver in the reverse direction such as /T1) has a gate electrode connected to an output control signal line, and is connected to the output terminal of the previous scan driver. It is configured such that the first electrode is connected and the second electrode is connected to the second input terminal (reverse control input terminal) of the scan driver at the rear stage.

Meanwhile, in order to drive the device under the same conditions as in the above-described embodiment, the timing controller and the scan driver may be configured as follows. The scan direction control unit may be included in the scan driver, and only the scan driver is illustrated in the following description.

17 is an exemplary diagram schematically illustrating a circuit configuration for controlling a scan driver based on an output control signal, and FIG. 18 is an exemplary diagram illustrating a flow of start pulses for each output control signal.

17 , the scan driver 140 may receive an output control signal from the timing controller 120 . To this end, the timing controller 120 and the scan driver 140 are electrically connected by an output control signal line SHL.

The output control signals transmitted through the output control signal line SHL are “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” shown in FIG. ", but may be composed of a binary number, but the number of bits or the programming direction of the start pulse is not limited thereto. Hereinafter, operations related to the scan driver and the scan direction controller will be described using two cases as an example.

<Reverse programming>

An example of a case in which “000” is output through the output control signal line SHL will be described with reference to FIGS. 15 and 18 together.

The flow of the start pulse has the order of GSP1 -> GSP2_1 -> GSP1_1 -> GSP2_2 -> GSP1_2 -> GSP2_3 -> GSP1_3 -> GSP2. And to follow this flow, /T1, /T2, /T3, /T4, /T5, /T6 are turned on.

As can be seen through the flow and operation of the device described above, when “000” is output through the output control signal line SHL, 140L1, 140L2, and 140L3 output a scan signal for reverse programming.

<Forward Programming>

An example of a case in which “111” is output through the output control signal line SHL will be described with reference to FIGS. 15 and 18 together.

The flow of the start pulse has the order of GSP1 -> GSP1_1 -> GSP2_1 -> GSP1_2 -> GSP2_2 -> GSP1_3 -> GSP2_3 -> GSP2. And to follow this flow, T1, T2, T3, T4, T5, T6 are turned on.

As can be seen through the flow and operation of the device described above, when “111” is output through the output control signal line SHL, 140L1, 140L2, and 140L3 output a scan signal for forward programming.

As described above, the present invention has the effect of providing an electroluminescent display device capable of expressing relatively uniform luminance in a driving method capable of accumulating and summing luminance deviations while eliminating a luminance step between blocks, and a driving method thereof. In addition, the present invention provides a block driving method capable of reducing luminance deviation, reducing power consumption of a display panel, securing sensing time and improving compensation accuracy, improving dynamic contrast ratio, improving moving picture response time (MPRT), There is an effect that can perform Black Data Insertion (BDI) and the like.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

110: image processing unit 120: timing control unit
130: data driver 140: scan driver
150: display panel 160: power supply
RPG: Reverse Programming FPG: Forward Programming
GSP, VSP: start pulses SHL: output control signal
160L1 ~ 160L3, 160R1 ~ 160R3: Scan direction control units
EMT: Emission time

Claims (10)

a display panel for displaying an image;
a data driver supplying a data voltage to the display panel;
a scan driver supplying a scan signal to the display panel; and
a scan direction control unit for changing a data voltage programming direction by controlling a start direction of a start pulse supplied to the scan driver;
The display panel receives the scan signal and the data voltage in units of blocks of a display area, wherein the data voltage programming direction between blocks is alternated in a first direction and a second direction and the data voltage programming direction between frames is changed from the previous one. alternated so as to be opposite,
The scan direction control unit
An electroluminescent display device comprising transistors operating in response to an output control signal supplied from the outside. delete delete According to claim 1,
The scan direction control unit
An electroluminescence display for controlling the scan driver to output a forward scan signal or a reverse scan signal. According to claim 1,
The scan direction control unit
An electroluminescent display device for controlling the flow of start pulses input and output from the scan driver. delete According to claim 1,
The transistors are
An electroluminescent display device comprising transistors for controlling a forward scan signal and transistors for controlling a reverse scan signal. 8. The method of claim 7,
Transistors for controlling the reverse scan signal are
An electroluminescent display device that is driven inversely with the forward scan signal control transistors. A method of driving an electroluminescent display device in which a display area of a display panel is defined in units of blocks, and a scan signal and a data voltage are input to drive in units of blocks, the method comprising:
programming a data voltage in a first direction with respect to a first block defined on the display panel during a first frame period;
programming a data voltage in a second direction with respect to a second block defined on the display panel during the first frame period; and
including changing programming directions for the first block and the second block during the second frame period,
When the same data voltage is applied to the display panel during the first frame and the second frame,
A method of driving an electroluminescent display device in which opposite luminances are displayed for each block in the first frame and the second frame. delete

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