KR20120119427A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce color distortion due to an inclined polarity, thereby reducing horizontal and vertical dims. CONSTITUTION: A liquid crystal panel(100) comprises m x n liquid crystal cells and TFT(Thin Film Transistor)s. The liquid crystal cells are formed by crossing m/2 data lines with 2n gate lines. The TFTs are connected to the liquid crystal cells. A data operating circuit(103) supplies a data voltage to the data lines in response to a polarity control signal. A gate operating circuit(104) outputs a plurality of san signals for operating the gate lines. [Reference numerals] (AA) Data line; (BB) Gate line

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of reducing color distortion due to polarity bias and dim in a horizontal or vertical direction.

Recently, liquid crystal displays are the most used display devices due to their even image quality, light weight, thinness, and low power.

In the liquid crystal display, inversion driving in which the polarity is inverted and the polarity is inverted in units of frames is applied between neighboring liquid crystal cells in order to reduce the DC offset component and reduce the deterioration of the liquid crystal.

Meanwhile, in order to reduce the circuit cost of the liquid crystal display, adjacent thin film transistors (TFTs) in the same display line are connected to the same data line to reduce the number of data lines and reduce the number of output channels of the data driving circuit. A double rate driving (DRD) panel structure is being developed.

In the liquid crystal display device using the DRD panel, a vertical two-dot or horizontal two-dot inversion driving is applied. The same polarity is repeatedly charged only to cells having a specific color among the RGB colors, so that one of the RGB colors is strongly visible. There was a problem that occurs, in addition, there was a problem that a dim in a horizontal or vertical direction occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device which can reduce color distortion due to polarity bias and dim in a horizontal or vertical direction.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes m × n liquid crystal cells defined as an intersection of m / 2 data lines and 2n gates (m and n are natural numbers). A liquid crystal panel comprising TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; A gate driving circuit outputting a plurality of scan signals for driving the gate lines; The liquid crystal cells are supplied with the data voltages in order of first to fourth liquid crystal cells, and the first liquid crystal cell is disposed at the upper left of the first crossing portion where the odd data line and the four gate lines intersect, and the even data line is provided. And the four gate lines intersect each other at an upper right side of the second intersection, and the second liquid crystal cell is disposed at a lower left side of the first intersection, and is disposed at a lower right side of the second intersection. The liquid crystal cell is disposed at the upper right of the first intersection, the upper left of the second intersection, and the fourth liquid crystal cell is disposed at the lower right of the first intersection, and at the lower left of the second intersection. It is characterized in that the arrangement.

The gate driving circuit sequentially outputs the plurality of scan signals to odd gate lines and sequentially supplies even gate lines; The plurality of scan signals may be alternately supplied to the odd gate lines and the even gate lines.

The data voltages having the same polarity are applied to the first and second liquid crystal cells, and the data voltages of the opposite polarity to the first and second liquid crystal cells are applied to the third and fourth liquid crystal cells. .

The first and second liquid crystal cells disposed at the positions opposite to each other are applied with data voltages having the same polarity, and the third and fourth liquid crystal cells disposed at the positions opposite to each other are applied with the data voltage having the same polarity as each other. It features.

The polarity control signal is phase inverted in four horizontal periods.

According to an embodiment of the present invention, power polarization and heat generation can be reduced by inverting the polarity of the data voltage in 4 horizontal periods, and luminance is uniform for each RGB color, thereby reducing color distortion and horizontal or vertical dim. can do.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the pixel array shown in FIG. 1.
3 is a driving waveform diagram of a scan signal according to an exemplary embodiment.
4 is a driving waveform diagram of a data voltage according to an embodiment.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the pixel array shown in FIG. 1.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 100, a timing controller 101, a data modulation logic circuit 102, a data driving circuit 103, and a gate. The drive circuit 104 is provided.

The liquid crystal panel 100 includes an upper glass substrate and a lower glass substrate facing each other with the liquid crystal layer interposed therebetween. The liquid crystal panel 100 includes a pixel array 10 displaying video data. The pixel array 10 has a cross structure of m (m is a positive integer) / 2 data lines D1 to Dm / 2 and 2n (n is a positive integer) gate lines G1 to G2n. M × n liquid crystal cells Clc arranged in a matrix form.

The m × n liquid crystal cells Clc include m vertical display lines in which the liquid crystal cells Clc are arranged in the data line direction, and n horizontal display lines in which the liquid crystal cells Clc are arranged in the gate line direction. Include. The liquid crystal cells Clc of the pixel array 10 are connected to an electric field generated by a voltage difference between the data voltage supplied to the pixel electrode 1 through the TFT and the common voltage Vcom supplied to the common electrode 2. Accordingly, an image is displayed by charging the data voltage and maintaining the data voltage for a predetermined period by the storage capacitor Cst.

The pixel array 10 includes m / 2 data lines D1 to Dm / 2, 2n gate lines G1 to G2n, m × n pixel electrodes 1, and pixel electrodes 1. M x n TFTs connected, and m x n storage capacitors Cst connected to the pixel electrodes 1. The left and right neighboring TFTs on the same line are connected to the same data line. The connection structure of the TFT and the data line is shown in FIG.

In the lower glass substrate of the liquid crystal panel 100, a gate driving circuit 104 connected to the gate lines G1 to G2n may be directly formed on the non-display surface outside the pixel array 10. In this case, the pixel array 10 and the gate driving circuit 104 are simultaneously formed on the lower glass substrate of the liquid crystal panel 100 in the same thin film process.

A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal panel 100. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the driving method.

A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal panel 100, and an alignment layer for setting the pre-tiltangle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal panel 100 applicable in the present invention may be implemented in any liquid crystal mode as well as the above-described TN mode, VA mode, IPS mode, FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as an edge type backlight unit or a direct type backlight unit. The edge type backlight unit has a structure in which a light source is disposed to face the side of the light guide plate, and a plurality of optical sheets are disposed between the liquid crystal panel and the light guide plate. The direct backlight unit has a structure in which optical sheets and a diffusion plate are stacked below the liquid crystal panel 100 and a plurality of light sources are disposed below the diffusion plate. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

Hereinafter, the TFTs disposed on the left side of the odd data lines D1, D3,..., Dm / 2-1 are referred to as the A liquid crystal cell and the first TFT, and the odd data lines D1, D3,... The liquid crystal cell Clc and the TFT disposed on the right side of 2-1) are the B liquid crystal cell and the second TFT, respectively, and the liquid crystal cell disposed on the left side of the even data lines D2, D4, ... Dm / 2. Clc) and TFT are respectively C liquid crystal cell and third TFT, and liquid crystal cell (Clc) and TFT disposed on the right side of even data lines (D2, D4, ... Dm / 2) are respectively D liquid crystal cell and fourth. It is defined as TFT.

The first TFT has a data voltage from the odd data lines D1, D3 ... Dm / 2-1 in response to a gate pulse (or scan signal) from the odd gate lines G1, G3 ... G2n-1. Is supplied to the pixel electrode 1 of the A liquid crystal cell Clc. For this purpose, the gate electrode of the first TFT is connected to the odd gate lines G1, G3 ... G2n-1, and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1. . The source electrode of the first TFT is connected to the pixel electrode 1 of the A liquid crystal cell Clc.

The second TFT converts the data voltages from the odd data lines D1, D3 ... Dm / 2-1 in response to the gate pulses from the even gate lines G2, G4 ... G2n to the B liquid crystal cell Clc. Is supplied to the pixel electrode 1. For this purpose, the gate electrode of the second TFT is connected to the even gate lines G2, G4 ... G2n, and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1. The source electrode of the second TFT is connected to the pixel electrode 1 of the B liquid crystal cell Clc.

The third TFT receives the data voltages from the even data lines D2, D4 ... Dm / 2 in response to the gate pulses from the even gate lines G2, G4 ... G2n. Supply to the pixel electrode 1. For this purpose, the gate electrode of the third TFT is connected to the even gate lines G2, G4 ... G2n, and the drain electrode is connected to the even data lines D2, D4 ... Dm / 2. The source electrode of the third TFT is connected to the pixel electrode 1 of the C liquid crystal cell Clc.

The fourth TFT receives the data voltages from the even data lines D2, D4 ... Dm / 2 in response to the gate pulses from the odd gate lines G1, G3 ... G2n-1, and the D liquid crystal cell Clc. Is supplied to the pixel electrode 1. For this purpose, the gate electrode of the fourth TFT is connected to odd gate lines G1, G3 ... G2n-1, and the drain electrode is connected to even data lines D2, D4 ... Dm / 2. The source electrode of the fourth TFT is connected to the pixel electrode 1 of the D liquid crystal cell Clc.

Data of liquid crystal cells connected to the odd data lines D1, D3,..., Dm / 2-1 according to the connection relationship between the TFTs T1 to T4 and the data lines D1 to Dm / 2. The charging order and the data charging order of the liquid crystal cells connected to the even data lines D2, D4... Dm / 2 are reversed. In other words, the data charging order of the liquid crystal cells connected to the odd data lines D1, D3, ..., Dm / 2-1, and the even data lines D2, D4 ... Dm / 2. The data charging order of the connected liquid crystal cells is in the symmetrical direction.

The timing controller 101 receives timing signals such as vertical / horizontal synchronization signals Vsync and Hsync, data enable, and clock signal CLK from the system board 105 and the data driver circuit 103. Control signals for controlling the operation timing of the gate driving circuit 104 and the polarity control signal (hereinafter, POL) and the data modulation logic circuit 102 are generated. The timing controller 101 then supplies RGB digital video data to the POL and data modulation logic circuit 102. The timing controller 101 generates a data timing control signal for controlling the data driving circuit 103 and a gate timing control signal for controlling the gate driving circuits 104 using the timing signal. The timing controller controls the gate timing control signal and the timing control signal so that digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array 10 of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer of 2 or more) The frequency of the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

Control signals output from the timing controller 101 include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse. (Source Start Pulse: SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and POL. The gate start pulse (GSP) indicates a starting horizontal line at which the scanning starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to the shift register in the gate drive circuit and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated with a pulse width corresponding to the ON period of the TFT. The gate output enable signal GOE indicates the output of the gate drive circuit 104. [ The source start pulse SSP indicates the starting pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 103 on the basis of the rising or falling edge. The source output enable signal SOE indicates the output of the data driving circuit 103. POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. This POL is phase inverted in four horizontal period periods.

The data modulation logic circuit 102 receives the gate start pulse GSP, the source output enable signal SOE, and the POL in sequence to first and second POLs whose phases are inverted from each other to prevent afterimages and flicker. Output

The data driving circuit 103 latches the digital video data RGB 'modulated by the POL and the data modulation logic circuit 102 under the control of the timing controller 101. The data driving circuit 103 converts the latched digital video data into an analog positive / negative gamma compensation voltage in response to the POL from the data modulation logic circuit 102 to generate a positive / negative data voltage. The data driving circuit 103 supplies the positive / negative data voltage to the data lines D1 to Dm / 2.

The gate driver circuit 104 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to G2n And a plurality of gate drive ICs. The gate driving circuit 104 outputs a scan signal having a pulse width of approximately one horizontal period synchronized with the positive / negative data voltage. In this case, the gate driving circuit 104 transmits a plurality of scan signals to the odd gate lines G1, G3... G2n-1 and the even gate lines G2, G4 .. G2n, as shown in FIG. 3. Each of them is sequentially supplied, and a plurality of scan signals are alternately supplied to odd gate lines G1, G3 ... G2n-1 and even gate lines G2, G4 ... G2n.

Hereinafter, the data charging order of the liquid crystal cells according to the embodiment will be described.

As shown in FIG. 2, the liquid crystal cells according to the embodiment are filled with data in order of the first to fourth liquid crystal cells ①, ②, ③, and ④. Here, the first liquid crystal cell ① has a first intersection where the odd data lines D1, D3, ..., Dm / 2-1 and the four gate lines G1 to G4, G5 to G8, ... cross each other. A second intersection part disposed at the upper left of the part P1 and crossing even data lines D2, D4 ... Dm / 2 and the four gate lines G1 to G4, G5 to G8, ... The second liquid crystal cell ② is disposed at the upper right of P2, and the second liquid crystal cell ② is disposed at the lower left of the first intersection P1, and is disposed at the lower right of the second intersection P2. ③) is disposed at the upper right side of the first intersection P1, is disposed at the upper left of the second intersection P2, and the fourth liquid crystal cell ④ is disposed at the lower right of the first intersection P1. It is arrange | positioned and it is arrange | positioned at the lower left of the 2nd intersection part P2.

4 is a driving waveform diagram of a data voltage according to an embodiment.

Meanwhile, as shown in FIG. 4, the data driving circuit 103 outputs a data voltage whose polarity is inverted in four horizontal periods using POL. In this case, data voltages having the same polarity are applied to the first and second liquid crystal cells ① and ②, and the third and fourth liquid crystal cells ③ and ④ are the first and second liquid crystal cells ①. , And data voltage of opposite polarity is applied. In addition, the first and second liquid crystal cells ① and ② disposed at opposite positions are applied with data voltages having the same polarity, and the third and fourth liquid crystal cells ③ and ④ disposed at opposite positions to each other. ) Are applied with data voltages of the same polarity.

That is, in the embodiment, the data driving circuit 103 inverts the polarity of the data voltage in four horizontal periods, but the actual liquid crystal cells are driven inverting the vertical two dots. Accordingly, the embodiment can reduce power consumption and heat generation of the data driving circuit 103 than when performing vertical or horizontal two dot inversion driving. Of course, the embodiment is applied to the two-dot inversion driving, as is known, compared to the inversion driving method such as four-dot inversion, line inversion driving, there will also be an advantage that the image quality degradation phenomenon such as vertical / horizontal crosstalk or afterimage is reduced.

On the other hand, the present invention can improve the color distortion phenomenon or the dim problem occurred in the conventional liquid crystal display device using the DRD panel.

First, the color distortion phenomenon of the conventional liquid crystal display is caused by the luminance of the liquid crystal cell of a specific color being intensively lowered for each RGB color. The decrease in luminance of the liquid crystal cell occurs when the input data voltage is the data voltage inverted from the polarity of the previous data, because the charging / discharging time is required more than when the polarity is inverted.

Referring to Table 1 and FIG. 4, the embodiment is reversed when the polarity of the data voltage is supplied from the second liquid crystal cell ② to the third liquid crystal cell ③. Therefore, the luminance of the liquid crystal cells corresponding to the third liquid crystal cell ③ decreases according to the charge / discharge time delay, and it can be seen that the number of the liquid crystal cells ③ is the same for each of the RGB colors. Therefore, the embodiment can prevent a color distortion phenomenon in which only the luminance of a specific color is lowered among the RGB colors.

In addition, the embodiment can reduce the dim phenomenon generated in the conventional liquid crystal display. In Table 1, the third liquid crystal cell ③ having the lowered luminance is shown by a dotted line. Referring to Table 1, it can be seen that in the embodiment, the number of the third liquid crystal cells ③ is not only the same for each RGB, but alternately arranged in each vertical line. Therefore, in the exemplary embodiment, since the normal fourth liquid crystal cell ④ and the third liquid crystal cell ③ are not alternately disposed, the horizontal and vertical dim phenomena are reduced.

As described above, the embodiment of the present invention can reduce the power consumption and heat generation by inverting the polarity of the data voltage in four horizontal periods, compared to the two-dot inversion driving, uniform luminance by RGB colors, color distortion and horizontal or Vertical dimming can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

100: liquid crystal panel 101: timing controller
102: data modulation logic circuit 103: data driving circuit
104: gate driving circuit

Claims (5)

a liquid crystal panel including m × n liquid crystal cells defined by the intersection of m / 2 data lines and 2n gate lines (m and n are natural numbers), and TFTs connected to the liquid crystal cells;
A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal;
A gate driving circuit outputting a plurality of scan signals for driving the gate lines;
The liquid crystal cells are supplied with the data voltages in order of first to fourth liquid crystal cells,
The first liquid crystal cell is disposed on the upper left of the first intersection where the odd data lines and the four gate lines intersect, and is disposed on the upper right of the second intersection where the even data lines and the four gate lines intersect.
The second liquid crystal cell is disposed at the lower left of the first intersection, and disposed at the lower right of the second intersection.
The third liquid crystal cell is disposed on the upper right side of the first intersection, and disposed on the upper left side of the second intersection,
And the fourth liquid crystal cell is disposed at a lower right side of the first intersection and is disposed at a lower left side of the second intersection. The method of claim 1,
The gate driving circuit
Outputting the plurality of scan signals sequentially to odd gate lines and sequentially supplying even gate lines;
And supplying the plurality of scan signals alternately to the odd gate lines and the even gate lines. The method of claim 1,
The first and second liquid crystal cells are applied with data voltages having the same polarity, and the third and fourth liquid crystal cells are applied with data voltages of opposite polarity to the first and second liquid crystal cells. Liquid crystal display. The method of claim 3, wherein
The first and second liquid crystal cells disposed at positions opposite to each other are applied with data voltages having the same polarity.
The liquid crystal display of claim 3, wherein the third and fourth liquid crystal cells disposed at opposite positions are applied with data voltages having the same polarity. The method of claim 1,
And the polarity control signal is inverted in phase in four horizontal periods.

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