KR102600441B1 - Organic light emitting diode display device and driving method thereof - Google Patents

Abstract

Disclosed is an organic light emitting diode display device and a method of driving the same.
An organic light emitting diode display device according to an embodiment of the present invention is an organic light emitting diode display device in which pixels adjacent to each other along the gate line direction are arranged in pairs to share one data line in pixel areas defined by a plurality of gates and data lines. A timing control unit that aligns and outputs image data so that pixels of the same color can continuously emit light along the data line direction while driving the LED display panel and pixels in the DRD method, as well as generating and outputting gate and data control signals. It can achieve the effect of reducing the amount of data voltage variation supplied to each pixel through the data line and the data voltage charging rate deviation between adjacent pixels.

Description

Organic light emitting diode display device and driving method thereof {ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention is an organic light emitting diode display device that drives an organic light emitting diode display panel in a DRD (Double Rating Driving) method and changes the driving order of the pixels, thereby reducing the amount of data voltage variation and charging rate deviation supplied to each pixel. and a driving method thereof.

Liquid crystal display devices have been widely used as flat image display devices, but liquid crystal displays require a backlight as a separate light source and have technical limitations in brightness, contrast ratio, and viewing angle.

Accordingly, organic light emitting diode display devices (Organic Light Emitting Diode Display devices), which are self-luminous and do not require a separate light source, and are relatively superior in brightness, contrast ratio, and viewing angle, are increasingly expanding.

The organic light-emitting diode display device uses a light-emitting device, that is, an organic light-emitting diode, in which a light-emitting layer is formed between a cathode for injecting electrons and an anode for injecting holes. The organic light emitting diode display device arranges organic light emitting diodes in each pixel area of the video display panel, and electrons generated from the cathode of the organic light emitting diode and holes generated from the anode combine within the light emitting layer to produce light emission. Display the video.

A conventional organic light emitting diode display device displays a color image by forming red, green, and blue color filters in each pixel area where the organic light emitting diode is disposed, so that each pixel emits red, green, and blue light.

However, in recent years, as the utilization of organic light-emitting diode displays has increased and the fields of use have become more diverse, there is a growing need for improvement and development to enable organic light-emitting diode displays to be more easily applied to various fields.

The present invention aims to increase the usability of organic light-emitting diode displays. By changing the driving order of pixels while driving the organic light-emitting diode display panel in the DRD method, the amount of data voltage variation and charge rate deviation supplied to each pixel is reduced. The purpose is to provide an organic light-emitting diode display device and a method of driving the same that can reduce the amount of light.

In order to achieve the above object, an organic light emitting diode display device according to an embodiment of the present invention has pixels adjacent to each other along the gate line direction in pairs in pixel areas defined by a plurality of gates and data lines, each forming a single pair. An organic light emitting diode display panel arranged to share a data line, and the arrayed pixels are driven in the DRD method while aligning and outputting image data so that pixels of the same color can continuously emit light along the data line direction, as well as gate and data A timing control unit that generates and outputs a control signal, a gate driver that outputs a gate on signal to the gate lines according to the gate control signal, and a timing control unit that generates a data voltage to correspond to the aligned image data and generates a gate signal according to the data control signal. It includes a data driver that outputs a data voltage to each data line in synchronization with the output timing of the on signal.

In addition, in order to achieve the above object, a method of driving an organic light emitting diode display device according to an embodiment of the present invention includes pixels adjacent to each other along the gate line direction in pixel areas defined by a plurality of gates and data lines. In a method of driving an organic light emitting diode display device having organic light emitting diode display panels arranged in pairs to share one data line, the arranged pixels are driven in the DRD method, and pixels of the same color are driven along the data line direction. It includes the steps of aligning and outputting image data so that they can be continuously emitted, as well as generating and outputting gate and data control signals.

The organic light-emitting diode display device and its driving method according to an embodiment of the present invention, which has the various technical features described above, operates the organic light-emitting diode display panel in a DRD (Double Rating Driving) method, so that the organic light-emitting diode display panel is connected to the data lines. The number of channels can be reduced by half and the data driving circuit can be simplified.

In addition, the pixels of the same color arranged on the organic light emitting diode display panel are allowed to emit light continuously, and the driving order of the pixels is varied by at least one frame, thereby increasing the data voltage supplied to each pixel through the data line. The amount of variation and the data voltage charging rate deviation between adjacent pixels can be reduced.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1.
FIG. 3 is a configuration diagram specifically showing the pixel arrangement structure of the organic light emitting diode display panel shown in FIG. 1.
Figure 4 is a pixel arrangement diagram showing the pixel driving order of the odd-numbered frame period according to the first embodiment of the present invention.
Figure 5 is a pixel arrangement diagram showing the pixel driving order of the even-numbered frame period according to the first embodiment of the present invention.
Figure 6 is a pixel arrangement diagram showing the pixel driving order in the first frame period according to the second embodiment of the present invention.
FIG. 7 is a diagram showing data voltage and gate on signal output timing during the first frame period shown in FIG. 6.
Figure 8 is a pixel arrangement diagram showing the pixel driving order of the second frame period according to the second embodiment of the present invention.
FIG. 9 is a diagram showing data voltage and gate on signal output timing during the second frame period shown in FIG. 8.
Figure 10 is a pixel arrangement diagram showing the pixel driving order of the third frame period according to the second embodiment.
Figure 11 is a pixel arrangement diagram showing the pixel driving order of the fourth frame period according to the second embodiment.
Figure 12 is a pixel arrangement diagram showing the pixel driving order in the first frame period according to the third embodiment of the present invention.
Figure 13 is a pixel arrangement diagram showing the pixel driving order in the second frame period according to the third embodiment of the present invention.
Figure 14 is a pixel arrangement diagram showing the pixel driving order of the third frame period according to the third embodiment of the present invention.

The above-mentioned objects, features, and advantages will be described in detail later with reference to the attached drawings, so that those skilled in the art will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention. And FIG. 2 is an equivalent circuit diagram of one pixel shown in FIG. 1.

The organic light emitting diode display device shown in FIG. 1 includes an organic light emitting diode display panel 100, a gate driver 200, a data driver 300, a power supply unit 400, and a timing control unit 500.

The organic light emitting diode display panel 100 is configured such that pixels P are arranged in pixel areas defined by intersections of gate lines GL1 to GLn and data lines DL1 to DLm. Here, pixels P located adjacent to each other along the direction of the gate lines GL1 to GLn are arranged in pairs to share one data line DL1 to DLm. The connection structure of the gate lines (GL1 to GLn), data lines (DL1 to DLm), and pixels (P) of the organic light emitting diode display panel 100 will be described in detail later with reference to the attached drawings.

Each pixel P includes an organic light emitting diode (OLED) and a pixel circuit that independently drives the organic light emitting diode (OLED). Specifically, each pixel P as shown in FIG. 2 is a pixel circuit connected to each gate line GL, data line DL, compensation power line CPL, etc., and a pixel circuit and a low-potential power supply. It includes an organic light emitting diode (OLED) connected between the signals (VSS) and equivalently expressed as a diode.

The pixel circuit may be composed of a source follower type compensation circuit structure, including first and second switching elements (T1, T2), a first stabilizing element (C1), and a driving switching element (DT). It may be configured to include, etc.

Specifically, the first switching element T1 of the pixel circuit is switched by a gate on signal from the gate line GL to drive the data voltage from the corresponding data line DL. The first node to which the switching element DT is connected Send to (N1).

The second switching element T2 drives the compensation voltage Vref input through the compensation power line CPL in response to the gate on signal from the gate line GL to the drain terminal (or data terminal) of the switching element DT. It is transmitted to the first node (N2) connected to the voltage output terminal).

The driving switching element DT has a first node N1 connected to the gate terminal, a second node N2 connected to the drain terminal, and a third node N3 connected to the source terminal (or driving pressure input terminal). It is configured to be electrically connected. Accordingly, the driving switching element (DT) receives the data voltage input through the first node (N1) and the first stabilization element (C1), and the compensation input through the second switching element (T2) and the second node (N2). The data voltage of the data line DL is transmitted to the organic light emitting diode (OLED) according to the voltage Vref.

The first stabilizing element C1 is connected between the first node N1 and the second node N2 of the driving switching element DT and serves to maintain the data voltage for one frame.

A second stabilization element (C2) for stabilizing the compensation voltage (Vref) may be additionally configured in the compensation power line (CPL).

The timing control unit 500 drives the pixels (P) of the organic light emitting diode display panel 100 in a DRD (Double Rating Driving) method, while pixels of the same color arranged along the data line (DL1 to DLm) direction are arranged in a plurality of horizontal rows. The image data (RGB) is sorted and output so that it can be continuously emitted in period units. The timing control unit 500 provides image data (RGB) so that pixels of the same color can continuously emit light in a plurality of horizontal periods and the driving order of each pixel (P) can be varied and driven by at least one frame. ) can also be sorted and printed.

In addition, the timing control unit 500 generates synchronization signals (DCLK, DE, Hsync, A gate control signal (GVS) and a data control signal (DVS) are generated using Vsync) and transmitted to the gate and data drivers 200 and 300, respectively.

The gate driver 200 outputs a gate on signal to each gate line GL1 to GLn in an order determined according to the gate control signal GVS.

Specifically, the gate driver 200 has built-in circuits such as at least one level shifter, a shift register, a delay circuit, and a flip-flop, and generates a gate control signal (GVS), such as a gate start pulse (GSP). The gate on signal is sequentially generated according to the pulse, gate shift clock (GSC), and gate output enable (GOE) signals. At this time, GSP is shifted according to GSC to sequentially generate gate-on signals. Then, the sequentially generated gate-on signals are supplied to each of the gate lines (GL1 to GLn) according to the connection structure of the gate lines (GL1 to GLn) of the organic light-emitting diode display panel 100.

The gate on signal output sequentially from the gate driver 200 is not necessarily output in the order in which the gate lines (GL1 to GLn) are arranged, and the gate on signal output channel of the gate driver 200 and each gate line (GL1 to GLn) The output order may vary depending on the connection structure. Additionally, depending on the design structure of built-in circuits such as delay circuits and flip-flops, the gate-on voltage output order may be reset and output for each gate line. A gate-off voltage is supplied during a period when the gate-on voltage is not supplied to the gate lines GL1 to GLn. Here, the output width of the gate on signal can be controlled according to the GOE signal.

The data driver 300 sequentially receives image data (Data) sorted by the timing control unit 500, at least one horizontal line at a time. Image data (Data) arranged in the timing control unit 500 is such that all pixels (P) are driven in the DRD method, while pixels of the same color arranged in the direction of the data lines (DL1 to DLm) continuously emit light in multiple horizontal periods. This is data arranged so that the driving order of each pixel (P) can be varied at least by one frame.

Accordingly, the data driver 300 generates a data control signal (DCS), such as a source start pulse (SSP), a source shift clock (SSC), and a source output enable (SOE). ) Using signals, etc., the above-mentioned aligned image data (Data) is converted to analog data voltage for one horizontal line at a time. Specifically, the data driver 300 samples image data (Data) sorted according to SSC by one horizontal line and converts it into a data voltage. And in response to the SOE signal, the data voltage for one horizontal line is supplied to each data line (DL1 to DLm) for each horizontal cycle in which the gate on signal is supplied to each gate line (GL1 to GLn). In this way, the data driver 300 generates a data voltage so that pixels arranged in the same color in the data line direction can continuously emit light for a plurality of horizontal periods, and each data line (DL1) is synchronized with the output timing of the gate on signal. to DLm) can be sequentially supplied with data voltages.

FIG. 3 is a configuration diagram specifically showing the pixel arrangement structure of the organic light emitting diode display panel shown in FIG. 1.

As shown in FIG. 3, the organic light emitting diode display panel 100 is arranged so that all data lines (DL1 to DLm) are halved by half compared to all pixel columns, and all gate lines (GL1 to GLn) are halved to all pixel rows. The number is doubled compared to the number of rows. Here, n and m are natural numbers excluding 0, and may be the same or different natural numbers.

Each pixel P is disposed in a pixel area defined by the intersection of two gate lines (for example, the 2n-1th gate line and the 2nth gate line) and one data line DL.

Each pixel P is paired with adjacent pixels P in the gate line GL direction and shares one data line. Specifically, the odd-numbered 2m-1th data line (DL1, DL3, ...DLm-1) is placed between the 4m-3rd and 4m-2th pixel columns, and the 4m-3th and 4m-2th pixel columns are The pixels arranged in the pixel row share each 2m-1th data line arranged between them.

The even-numbered 2m-th data line (DL2, DL4, ...DLm) is placed between the 4m-1th and 4m-th pixel columns, and the pixels placed in the 4m-1th and 4m-th pixel columns are placed between them. Each 2mth data line in the array is shared.

In addition, each pixel adjacent to each other in the pixel row direction (data line direction) receives a gate on signal from a different gate line, and among the pixels arranged in the same pixel row (gate line direction), the pixel in the 4m-3rd pixel column The pixels (P) of the 4m-th pixel column receive a gate-on signal from the 2n-1th gate line (the nearest odd-numbered gate line) arranged closest to it.

Among the pixels arranged in the same pixel row, the pixels (P) of the 4m-2th pixel column and the pixels (P) of the 4m-1th pixel column receive a gate-on signal from the 2nth gate line (the most adjacent even-numbered gate line). receives.

Figure 4 is a pixel arrangement diagram showing the pixel driving order of the odd-numbered frame period according to the first embodiment of the present invention.

Referring to FIG. 4, the timing control unit 500 controls the odd-numbered pixel column (2m-1th pixel) through the odd-numbered data lines (2m-1th data lines) during the odd-numbered frame (Odd Frame) period. After the data voltage is supplied to the pixel (①) arranged in the first pixel row of the even-numbered pixel row (2m-th pixel row), the pixels (②) of the same color are arranged in the first and second pixel rows of the even-numbered pixel row (2m-th pixel row). Arrange the image data so that the data voltage is continuously supplied to ,③). Next, the data voltage is supplied continuously to the pixels (④, ⑤) of the same color arranged in the second and third pixel rows of the odd-numbered pixel column (2m-1st pixel column), and then again in the even-numbered pixel column. The image data is aligned so that the data voltage is continuously supplied to the pixels (⑥, ⑦) of the same color arranged in the third and fourth pixel rows of the (2mth pixel row).

In this way, the timing control unit 500 controls the odd-numbered pixel column (2m-1th pixel column) through the odd-numbered data lines (2m-1th data lines) during the odd frame period. After the data voltage is supplied to the first pixel (①) of The image data is aligned so that the data voltage is continuously supplied to two pixels (②③, ④⑤, ⑥⑦) alternately.

At this time, in the case of the even-numbered data lines (2m-th data lines), the data voltage is supplied to the pixel (①) arranged in the first pixel row of the even-numbered pixel column (2m-th pixel column), and then The image data is aligned so that data voltage is continuously supplied to the pixels (②,③) of the same color arranged in the first and second pixel rows of the 2m-1th pixel column (2m-1st pixel column). Next, the data voltage is supplied continuously to the pixels (④,⑤) of the same color arranged in the second and third pixel rows of the even-numbered pixel column (2m-th pixel column), and then again in the odd-numbered pixel column (2m-th pixel column). The image data is aligned so that the data voltage is continuously supplied to the pixels (⑥, ⑦) of the same color arranged in the third and fourth pixel rows of the -1st pixel row.

In this way, in the case of the even-numbered data lines (2m-th data lines), the timing control unit 500 supplies the data voltage to the very first pixel of the even-numbered pixel column (2m-th pixel column) and then to the odd-numbered pixel column. Starting from the pixel column (2m-1st pixel column), the data voltage is applied continuously to pixels of the same color, alternating between the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Sort the image data so that it can be supplied. The image data (Data) arranged in this way is supplied to the data driver 300 at least one horizontal line at a time.

The timing control unit 500 controls the first pixel of the odd-numbered pixel column (2m-1th pixel column) of the odd-numbered data lines (2m-1th data lines), and the first pixel of the odd-numbered data lines (2m-1th data lines) and the even-numbered data lines (2m-1th data lines). After the data voltage is supplied to the first pixel of the even-numbered pixel column (2m pixel column) of the lines), unlike in FIG. 4, the data voltage is supplied alternately in succession to three pixels of the same color instead of two. It is also possible to drive it so that it is supplied. However, as shown in FIG. 4, an example in which data voltages are continuously supplied to pixels of the same color alternately, two at a time, will be described.

In addition, the timing control unit 500 controls the 8n-6th gate line (GL(8n-6)), the 8n-7th gate line (GL(8n-7)), and the 8n-4th gate line (GL(8n- 4)), 8n-5th gate line (GL(8n-5)), 8n-2nd gate line (GL(8n-2)), 8n-3rd gate line (GL(8n-3)), 8n A gate control signal (GVS) is generated so that the gate-on voltage is supplied to all gate lines (GL1 to GLn) in the order of the 8th gate line (GL(8n)) and the 8n-1th gate line (GL(8n-1)). It is transmitted to the gate driver 200.

Accordingly, the gate driver 200 controls the 8n-6th gate line (GL(8n-6)) and the 8n-7th gate line (GL() to all gate lines (GL1 to GLn) during the odd frame period (Odd Frame). 8n-7)), 8n-4th gate line (GL(8n-4)), 8n-5th gate line (GL(8n-5)), 8n-2nd gate line (GL(8n-2)) , the gate-on voltage is sequentially supplied to the 8n-3rd gate line (GL(8n-3)), the 8nth gate line (GL(8n)), and the 8n-1st gate line (GL(8n-1)). .

At this time, the data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially operates each gate line (GL1 to GLn) during the odd frame period (Odd Frame). ), the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period according to the timing at which the gate-on voltage is supplied.

Accordingly, the data voltage is supplied first to the pixel (①) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column) of the first pixel row, and the even-numbered pixel column (2m-1st pixel column) Data voltage is continuously supplied to the same color pixels (②,③) arranged in the first and second pixel rows. Subsequently, data voltage is continuously supplied to the same color pixels (④,⑤) arranged in the second and third pixel rows of the odd-numbered pixel column (2m-1st pixel column), and again in the even-numbered pixel column (2m-1st pixel column). Data voltage is continuously supplied to the same color pixels (⑥, ⑦) arranged in the 3rd and 4th pixel rows of the 3rd and 4th pixel rows, starting from the even-numbered pixel column (2mth pixel row) to the even-numbered pixel rows. The data voltage is continuously supplied to pixels (②③, ④⑤, ⑥⑦) of the same color, alternating in turns (2m-th pixel column) and odd-numbered pixel column (2m-1st pixel column).

At the same time, the data voltage is supplied first to the pixel (①) placed in the first pixel row of the even-numbered pixel column (2m-th pixel column) of the even-numbered data lines (2m-th data lines), and the data voltage is supplied to the odd-numbered data lines (2m-th data lines). Data voltage is continuously supplied to the same color pixels (②,③) arranged in the first and second pixel rows of the pixel column (2m-1st pixel column). Next, the data voltage is continuously supplied to the same color pixels (④,⑤) arranged in the second and third pixel rows of the even-numbered pixel column (2m-th pixel column), and then again in the odd-numbered pixel column (2m-1). Data voltage is supplied continuously to the same color pixels (⑥, ⑦) arranged in the 3rd and 4th pixel rows of the 2m-1st pixel row, and from the odd-numbered pixel row (2m-1st pixel row) The data voltage is continuously supplied to pixels of the same color, two alternately in the pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column).

Figure 5 is a pixel arrangement diagram showing the pixel driving order of the even-numbered frame period according to the first embodiment of the present invention.

Referring to FIG. 5, unlike FIG. 4, the timing control unit 500 controls the even-numbered pixel column (2m-th data lines) connected to the odd-numbered data lines (2m-1-th data lines) during the even-numbered frame (Even Frame) period. After the data voltage is supplied to the pixel (①) arranged in the first pixel row of the odd-numbered pixel row (2m-1th pixel row), the same color Image data is aligned so that data voltage is continuously supplied to the pixels (②,③). Next, the data voltage is supplied continuously to the pixels (④,⑤) of the same color arranged in the second and third pixel rows of the even-numbered pixel column (2m-th pixel column), and then again in the odd-numbered pixel column (2m-th pixel column). The image data is aligned so that the data voltage is continuously supplied to the pixels (⑥, ⑦) of the same color arranged in the third and fourth pixel rows of the -1st pixel row.

In this way, the timing control unit 500 supplies the data voltage to the very first pixel (①) of the even-numbered pixel column (2m-th pixel column) in the case of odd-numbered data lines (2m-1st data lines). Afterwards, starting from the odd-numbered pixel row (2m-1st pixel row), pixels of the same color are alternately displayed in the odd-numbered pixel row (2m-1st pixel row) and the even-numbered pixel row (2m-th pixel row). Arrange the image data so that the data voltage can be supplied continuously.

Then, the data voltage is supplied to the pixel (①) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column) through the even-numbered data lines (2m-th data lines). , the image data is aligned so that the data voltage is continuously supplied to the pixels (②,③) of the same color arranged in the first and second pixel rows of the even-numbered pixel column (2m pixel column). Next, the data voltage is supplied continuously to the pixels (④, ⑤) of the same color arranged in the second and third pixel rows of the odd-numbered pixel column (2m-1st pixel column), and then again in the even-numbered pixel column. The image data is aligned so that the data voltage is continuously supplied to the pixels (⑥, ⑦) of the same color arranged in the third and fourth pixel rows of the (2mth pixel row).

In this way, the timing control unit 500 controls the top of the odd-numbered pixel column (2m-1st pixel column) through the even-numbered data lines (2m-th data lines) during the even-numbered frame (Even Frame) period. After the data voltage is supplied to the first pixel (①), starting from the even-numbered pixel column (2m-th pixel column), it alternates between the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). The image data is aligned so that the data voltage can be supplied continuously to two pixels (②③,④⑤,⑥⑦). The image data (Data) arranged in this way is supplied to the data driver 300 at least one horizontal line at a time.

In addition, the timing control unit 500 generates a gate control signal (GVS) so that the gate-on voltage is sequentially supplied to the first to n-th gate lines (GL1 to GLn) in the even frame period (Even Frame), so that the gate driver Send to (200).

Accordingly, the gate driver 200 sequentially supplies the gate-on voltage to all gate lines GL1 to GLn during the even frame period (Even Frame).

At this time, the data driver 300 converts the image data (Data) aligned in the timing control unit 500 into a data voltage for one horizontal line at a time. And during the even frame period (Even Frame), according to the timing at which the gate-on voltage is sequentially supplied to each gate line (GL1 to GLn), all odd and even data lines (DL1 to DLm) are supplied in units of one horizontal period. Supply data voltage.

Accordingly, the data voltage is supplied first to the pixel (①) arranged in the first pixel row of the even-numbered pixel column (2m-th pixel column) connected to the odd-numbered data lines (2m-1st data lines), Data voltage is continuously supplied to the same color pixels (②,③) arranged in the first and second pixel rows of the odd-numbered pixel column (2m-1 pixel column). Next, the data voltage is continuously supplied to the same color pixels (④,⑤) arranged in the second and third pixel rows of the even-numbered pixel column (2m-th pixel column), and then again in the odd-numbered pixel column (2m-1). Data voltage is supplied continuously to the same color pixels (⑥, ⑦) arranged in the 3rd and 4th pixel rows of the 2m-1st pixel row, and from the odd-numbered pixel row (2m-1st pixel row) The data voltage is continuously supplied to pixels of the same color, two alternately in the pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column).

At the same time, the data voltage is supplied first to the pixel (①) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column), and the first and second pixels of the even-numbered pixel column (2m-1st pixel column) are supplied first. Data voltage is continuously supplied to the same color pixels (②,③) arranged in the second pixel row. Subsequently, data voltage is continuously supplied to the same color pixels (④,⑤) arranged in the second and third pixel rows of the odd-numbered pixel column (2m-1st pixel column), and again in the even-numbered pixel column (2m-1st pixel column). Data voltage is continuously supplied to the same color pixels (⑥, ⑦) arranged in the 3rd and 4th pixel rows of the 3rd and 4th pixel rows, starting from the even-numbered pixel column (2mth pixel row) to the even-numbered pixel rows. The data voltage is continuously supplied to pixels (②③, ④⑤, ⑥⑦) of the same color, alternating in turns (2m-th pixel column) and odd-numbered pixel column (2m-1st pixel column).

As such, according to the first embodiment of the present invention, the pixels of the same color arranged in the organic light emitting diode display panel 100 alternately emit light in two or three successive rows, and the pixels are illuminated in odd and even frame periods. The pixels can be driven by changing their driving order. In this case, since the grayscale values of pixels of the same color are generally similar, when the pixels of the same color are driven continuously, the amount of data voltage variation supplied to each pixel through each data line (DL1 to DLm), and The data voltage charging rate deviation between adjacent pixels can be reduced.

Figure 6 is a pixel arrangement diagram showing the pixel driving order in the first frame period according to the second embodiment of the present invention. And FIG. 7 is a diagram showing the data voltage and gate on signal output timing during the first frame period shown in FIG. 6.

Referring to FIGS. 5 and 6, the timing control unit 500 performs odd-numbered data lines (2m-1-th data lines) during the 1st frame period, which is the 4n-3-th frame period. After the data voltage is successively supplied to the pixels (①,②) arranged in the first and second pixel rows of the 2m-1th pixel row (2m-1st pixel row), the even-numbered pixel row (2m-1st pixel row) The image data (RGB) is aligned so that the data voltage is continuously supplied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the odd-numbered pixel column (2m-1st pixel column), so that the even-numbered pixel Starting from the 2mth pixel column, the data voltage is supplied continuously to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). Sort the image data (RGB) so that

At this time, data is continuously transmitted to the pixels (①,②) arranged in the first and second pixel rows of the even-numbered pixel column (2m-th pixel column) through the even-numbered data lines (2m-th data lines). After the voltage is supplied, the data voltage is continuously applied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the odd-numbered pixel column (2m-1st pixel column). Sort the image data (RGB) so that it is supplied. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column ( From the 2m-1st pixel column, the data voltage is supplied continuously to four pixels of the same color alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Sort the image data (RGB) so that

In addition, as shown in FIG. 7, the timing control unit 500 controls the 8n-6th gate line (GL(8n-6)), the 8n-4th gate line (GL(8n-4)), and the 8n-7th gate line. (GL(8n-7)), 8n-5th gate line (GL(8n-5)), 8n-3rd gate line (GL(8n-3)), 8n-1st gate line (GL(8n- 1)), the gate control signal ( GVS) is generated and transmitted to the gate driver 200.

Accordingly, the gate driver 200 applies the 8n-6th gate line (GL(8n-6)) and the 8n-4th gate line (GL(8n-) to all gate lines (GL1 to GLn) during the 4n-3th frame period. 4)), 8n-7th gate line (GL(8n-7)), 8n-5th gate line (GL(8n-5)), 8n-3rd gate line (GL(8n-3)), 8n The gate-on voltage is sequentially supplied to the -1st gate line (GL(8n-1)), the 8n-2nd gate line (GL(8n-2)), and the 8nth gate line (GL(8n)).

At this time, the data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially applies it to each gate line (GL1 to GLn) during the 4n-3th frame period. In accordance with the timing at which the gate-on voltage is supplied, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the pixels ① and ② arranged in the first and second pixel rows of the odd-numbered pixel column (2m-1th pixel column) are connected to the pixels ① and ② through the odd-numbered data lines (2m-1th data lines). After the data voltage is continuously supplied, data is continuously supplied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the even-numbered pixel column (2m pixel column). Voltage is supplied. Next, the data voltage is continuously supplied to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the odd-numbered pixel column (2m-1st pixel column), and the even-numbered pixel column Starting from the 2mth pixel column, the data voltage is supplied sequentially to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). .

At the same time, through the even-numbered data lines (2m-th data lines), the pixels (①, ②) arranged in the first and second pixel rows of the even-numbered pixel column (2m-th pixel column) are continuously connected. After the data voltage is supplied, data is sequentially transmitted to four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the odd-numbered pixel column (2m-1st pixel column). Voltage is supplied. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column ( Starting from the 2m-1st pixel column, the data voltage is supplied sequentially to four pixels of the same color alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). .

Figure 8 is a pixel arrangement diagram showing the pixel driving order of the second frame period according to the second embodiment of the present invention. And FIG. 9 is a diagram showing the data voltage and gate on signal output timing during the second frame period shown in FIG. 8.

Referring to FIGS. 8 and 9, unlike in FIG. 6, the timing control unit 500 controls odd-numbered data lines (2m-1th data line) during the 2nd frame period, which is the 4n-2th frame period. After the data voltage is continuously supplied to the pixels (①,②) arranged in the first and second pixel rows of the even-numbered pixel column (2m-th pixel column), the data voltage is continuously supplied to the odd-numbered pixel column (2m- The image data (RGB) is aligned so that the data voltage is continuously supplied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the first pixel row. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column ( From the 2m-1st pixel column, the data voltage is continuously alternated to four pixels of the same color, alternating in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Sort the image data (RGB) so that it can be supplied.

And through the even-numbered data lines (2m-th data lines), the pixels (①, ②) arranged in the first and second pixel rows of the odd-numbered pixel column (2m-1st pixel column) are continuously connected. After the data voltage is supplied, the data voltage is continuously applied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the even-numbered pixel column (2m pixel column). Sort the image data (RGB) so that it is supplied. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the odd-numbered pixel column (2m-1st pixel column), so that the even-numbered pixel Starting from the 2mth pixel column, the data voltage is supplied continuously to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). Sort the image data (RGB) so that At least one horizontal line worth of image data (Data) of the aligned frames is supplied to the data driver 300.

In addition, as shown in FIG. 9, the timing control unit 500 controls the 8n-7th gate line (GL(8n-7)), the 8n-5th gate line (GL(8n-5)), and the 8n-6th gate line. (GL(8n-6)), 8n-4th gate line (GL(8n-4)), 8n-2nd gate line (GL(8n-2)), 8nth gate line (GL(8n)), A gate control signal ( GVS) is generated and transmitted to the gate driver 200.

Accordingly, the gate driver 200 adds the 8n-7th gate line (GL(8n-7)) and the 8n-5th gate line (GL(8n-) to all gate lines (GL1 to GLn) during the 4n-2th frame period. 5)), 8n-6th gate line (GL(8n-6)), 8n-4th gate line (GL(8n-4)), 8n-2nd gate line (GL(8n-2)), 8n The gate-on voltage is sequentially supplied to the 8n-th gate line (GL(8n)), the 8n-3rd gate line (GL(8n-3)), and the 8n-1st gate line (GL(8n-1)).

The data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially turns on the gate on each gate line (GL1 to GLn) during the 4n-2th frame period. In accordance with the voltage supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the pixels (①,②) arranged in the first and second pixel rows of the even-numbered pixel column (2m-th pixel column) are sequentially connected through the odd-numbered data lines (2m-1th data lines). After the data voltage is supplied, data is sequentially transmitted to four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the odd-numbered pixel column (2m-1st pixel column). Voltage is supplied. And again, the data voltage is supplied continuously to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column ( Starting from the 2m-1st pixel column, the data voltage is supplied sequentially to four pixels of the same color alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). .

At the same time, the pixels (①,②) arranged in the first and second pixel rows of the odd-numbered pixel column (2m-1th pixel column) are connected through the even-numbered data lines (2m-th data lines). After the data voltage is continuously supplied, data is continuously supplied to the four pixels (③,④,⑤,⑥) of the same color arranged in the first to fourth pixel rows of the even-numbered pixel column (2m pixel column). Voltage is supplied. Next, the data voltage is continuously supplied to the four pixels (⑦⑧) of the same color arranged in the 3rd to 6th pixel rows of the odd-numbered pixel column (2m-1st pixel column), and the even-numbered pixel column Starting from the 2mth pixel column, the data voltage is supplied sequentially to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). .

In this way, the timing control unit 500 operates each pixel (P) in the 2nd frame period, which is the 4n-2nd frame period, in the opposite order to the driving order of the pixels (P) that were driven in the 4n-3rd frame period. Let it run.

As described above, according to the second embodiment, up to four pixels of the same color arranged in the organic light emitting diode display panel 100 alternately emit light in succession, and pixels are displayed in units of odd and even frame periods. They can be driven by changing their driving order.

Figure 10 is a pixel arrangement diagram showing the pixel driving order of the third frame period according to the second embodiment.

Referring to FIG. 10, the timing control unit 500 controls the even-numbered pixels through odd-numbered data lines (2m-1-th data lines) during the 3rd frame period, which is the 4n-1th frame period. The data voltage is first supplied to the pixel (①) placed in the first pixel row of the column (2m-th pixel column), and then to the first to third pixel rows of the odd-numbered pixel column (2m-1st pixel column). Data voltage is supplied continuously in order to the three arranged pixels of the same color (②,③,④). And, the image data ( Sort RGB). Next, the data voltage is continuously supplied to the four pixels (⑨,⑩) of the same color arranged in the 4th to 7th pixel rows of the odd-numbered pixel column (2m-1st pixel column), From the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the even-numbered pixel column (2m-th pixel column), the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column The image data (RGB) is aligned so that data voltages can be continuously supplied to four pixels of the same color alternately in the th pixel column (2m-1st pixel column).

At this time, in the case of the even-numbered data lines (2m-th data lines), the data voltage is supplied first to the pixel (①) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column). Afterwards, the data voltage is supplied sequentially in order to the three same color pixels (②,③,④) arranged in the first to third pixel rows of the even-numbered pixel column (2m pixel column). And, the image voltage is supplied continuously to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the odd-numbered pixel column (2m-1st pixel column). Sort data (RGB). Next, the data voltage is supplied continuously to the four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column Starting from the pixel column (2m-1st pixel column), the data voltage is applied sequentially to pixels of the same color, four in a row, alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Sort the image data so that it can be supplied. Then, aligned image data (Data) is supplied to the data driver 300 at least one horizontal line at a time.

In addition, the timing control unit 500 controls the 8n-7th gate line (GL(8n-7)), the 8n-6th gate line (GL(8n-6)), and the 8n-4th gate line (GL(8n- 4)), 8n-2nd gate line (GL(8n-2)), 8n-5th gate line (GL(8n-5)), 8n-3rd gate line (GL(8n-3)), 8n -To all gate lines (GL1 to GLn) in the following order: 1st gate line (GL(8n-1)), 8n-7th gate line (GL(8n-7)), and 8nth gate line (GL(8n)). A gate control signal (GVS) is generated and transmitted to the gate driver 200 so that the gate-on voltage is supplied.

Accordingly, the gate driver 200 adds the 8n-7th gate line (GL(8n-7)) and the 8n-6th gate line (GL(8n-) to all gate lines (GL1 to GLn) during the 4n-1th frame period. 6)), 8n-4th gate line (GL(8n-4)), 8n-2nd gate line (GL(8n-2)), 8n-5th gate line (GL(8n-5)), 8n -3rd gate line (GL(8n-3)), 8n-1st gate line (GL(8n-1)), 8n-7th gate line (GL(8n-7)), 8n-th gate line (GL (8n)), supply the gate-on voltage sequentially.

The data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially turns on the gate on each gate line (GL1 to GLn) during the 4n-1th frame period. In accordance with the voltage supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the data voltage is first supplied to the pixel (①) arranged in the first pixel row of the even-numbered pixel column (2m-th pixel column) through the odd-numbered data lines (2m-1th data lines). , the data voltage is supplied sequentially in order to the three same-color pixels (②,③,④) arranged in the first to third pixel rows of the odd-numbered pixel column (2m-1 pixel column). Then, the data voltage is successively supplied to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the even-numbered pixel column (2m-th pixel column), and again in odd-numbered pixel columns. A method of supplying data voltage continuously to four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the 2m-1st pixel column (2m-1st pixel column), so that the even-numbered pixel column Starting from (2m-th pixel column), data voltage is supplied continuously to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and odd-numbered pixel column (2m-1st pixel column).

At the same time, in the case of even-numbered data lines (2m-th data lines), the data voltage is supplied first to the pixel (①) placed in the first pixel row of the odd-numbered pixel column (2m-1st pixel column). After that, the data voltage is sequentially supplied to the three same color pixels (②,③,④) arranged in the first to third pixel rows of the even-numbered pixel column (2m pixel column). In addition, the data voltage is continuously supplied to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the second to fifth pixel rows of the odd-numbered pixel column (2m-1st pixel column), Again, the data voltage is supplied continuously to the four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column Starting from (2m-1st pixel column), data voltage is supplied continuously to four pixels of the same color alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). do.

In this way, the timing control unit 500 operates such that during the 3rd frame period, which is the 4n-1th frame period, the driving order of the pixels P that were driven in the 4n-3rd frame period is driven in a form where the driving order is shifted by 1 horizontal line. do.

Subsequently, the timing control unit 500 may drive the pixels P that were driven in the 4n-2th frame period in a manner in which the driving order of the pixels P that was driven in the 4n-2th frame period is shifted by 1 horizontal line. there is.

Figure 11 is a pixel arrangement diagram showing the pixel driving order of the fourth frame period according to the second embodiment.

Referring to FIG. 11, unlike in FIG. 10, the timing control unit 500 operates an odd number connected to the odd numbered data lines (2m-1th data lines) during the 4th frame period, which is the 4nth frame period. The data voltage is first supplied to the pixel (①) arranged in the first pixel row of the 2m-1st pixel row, and then the 1st to 3rd images of the even-numbered pixel row (2m-1st pixel row). Data voltage is supplied sequentially in order to the three same color pixels (②,③,④) arranged in the row. And, the image voltage is supplied continuously to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the odd-numbered pixel column (2m-1st pixel column). Sort data (RGB). Next, the data voltage is supplied continuously to the four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column Starting from the pixel column (2m-1st pixel column), the data voltage is applied sequentially to pixels of the same color, four in a row, alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Sort the image data so that it can be supplied.

In the case of the even-numbered data lines (2m-th data lines), the data voltage is supplied first to the pixel (①) placed in the first pixel row of the even-numbered pixel column (2m-th pixel column), and then the data voltage is supplied to the odd-numbered data lines (2m-th data lines). The data voltage is supplied continuously in order to the three same color pixels (②,③,④) arranged in the first to third pixel rows of the pixel column (2m-1st pixel column). And, the image data ( Sort RGB). Next, the data voltage is continuously supplied to the four pixels (⑨,⑩) of the same color arranged in the 4th to 7th pixel rows of the odd-numbered pixel column (2m-1st pixel column), From the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the even-numbered pixel column (2m-th pixel column), the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column The image data (RGB) is aligned so that data voltages can be continuously supplied to four pixels of the same color alternately in the th pixel column (2m-1st pixel column). Then, image data (Data) of the aligned frames is supplied to the data driver 300 at least for one horizontal line.

In addition, the timing control unit 500 controls the 8n-6th gate line (GL(8n-6)), the 8n-7th gate line (GL(8n-7)), and the 8n-5th gate line (GL(8n- 5)), 8n-3rd gate line (GL(8n-3)), 8n-4th gate line (GL(8n-4)), 8n-2nd gate line (GL(8n-2)), 8n to all gate lines (GL1 to GLn) in the order of the 8n-6th gate line (GL(8n)), the 8n-1st gate line (GL(8n-1)), and the 8n-6th gate line (GL(8n-6)). A gate control signal (GVS) is generated and transmitted to the gate driver 200 so that the gate-on voltage is supplied.

Accordingly, the gate driver 200 adds the 8n-6th gate line (GL(8n-6)) and the 8n-7th gate line (GL(8n-7) to all gate lines (GL1 to GLn) during the 4nth frame period. ), 8n-5th gate line (GL(8n-5)), 8n-3rd gate line (GL(8n-3)), 8n-4th gate line (GL(8n-4)), 8n-2 8n-th gate line (GL(8n-2)), 8nth gate line (GL(8n)), 8n-6th gate line (GL(8n-6)), 8n-1st gate line (GL(8n-1) )) Supply the gate-on voltage sequentially in order.

At this time, the data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially turns on the gate on each gate line (GL1 to GLn) during the 4nth frame period. In accordance with the voltage supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the data voltage is supplied first to the pixel (①) placed in the first pixel row of the odd-numbered pixel column (2m-1st pixel column) connected to the odd-numbered data lines (2m-1st data lines). After that, the data voltage is sequentially supplied to the three same color pixels (②,③,④) arranged in the first to third pixel rows of the even-numbered pixel column (2m pixel column). In addition, the data voltage is continuously supplied to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the second to fifth pixel rows of the odd-numbered pixel column (2m-1st pixel column), Again, the data voltage is supplied continuously to the four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the even-numbered pixel column (2m-th pixel column), and the odd-numbered pixel column Starting from (2m-1st pixel column), data voltage is supplied continuously to four pixels of the same color alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). do.

At the same time, the data voltage is first supplied to the pixel (①) arranged in the first pixel row of the even-numbered pixel column (2m-th pixel column) through the even-numbered data lines (2m-th data lines). , the data voltage is supplied sequentially in order to the three same-color pixels (②,③,④) arranged in the first to third pixel rows of the odd-numbered pixel column (2m-1 pixel column). Then, the data voltage is successively supplied to the four pixels (⑤,⑥,⑦,⑧) of the same color arranged in the 2nd to 5th pixel rows of the even-numbered pixel column (2m-th pixel column), and again in odd-numbered pixel columns. A method of supplying data voltage continuously to four pixels (⑨, ⑩) of the same color arranged in the 4th to 7th pixel rows of the 2m-1st pixel column (2m-1st pixel column), so that the even-numbered pixel column Starting from (2m-th pixel column), data voltage is supplied continuously to four pixels of the same color alternately in the even-numbered pixel column (2m-th pixel column) and odd-numbered pixel column (2m-1st pixel column).

In this way, the timing control unit 500 drives each pixel (P) in the opposite order to the driving order of the pixels (P) that were driven in the 4n-1th frame period during the 4th frame period, which is the 4nth frame period. However, the driving order of the pixels P that were driven during the 4n-2th frame period can be driven in a form that is shifted by 1 horizontal line.

As such, according to the second embodiment, four pixels of the same color arranged in the organic light emitting diode display panel 100 are alternately illuminated in succession, and the driving order of the pixels is changed in units of odd and even frame periods. It can be driven by shifting. In this case, there is an effect of further reducing the amount of data voltage variation supplied to each pixel through the data lines DL1 to DLm and the difference in data voltage charging rate between adjacent pixels.

Figure 12 is a pixel arrangement diagram showing the pixel driving order in the first frame period according to the third embodiment of the present invention.

Referring to FIG. 12, the timing control unit 500 controls odd-numbered data lines (2m-1-th data lines) during a 1st frame period of a plurality of preset frame periods, for example, an 8-frame period. After the data voltage is supplied sequentially to the pixels (G1 to G4) arranged in the first to fourth pixel rows of the odd-numbered pixel column (2m-1st pixel column) through ), the even-numbered pixel column (2m-1st pixel column) The image data is arranged so that data voltages are supplied continuously in order to the pixels (R1 to R8) arranged in the first to eighth pixel rows (th pixel column). Next, the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the odd-numbered pixel column (2m-1st pixel column), and from the even-numbered pixel column (2m-1st pixel column) to the even-numbered pixels. The image data (RGB) is arranged so that the data voltage is continuously supplied to pixels of the same color, eight in a row alternately in the row (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column).

At this time, in the case of the even-numbered data lines (2m-th data lines), the pixels (B1 to B4) arranged in the first to fourth pixel rows of the even-numbered pixel column (2m-th pixel column) are sequentially connected. After the data voltage is supplied, the image data is arranged so that the data voltage is supplied sequentially to the pixels (W1 to W8) arranged in the 1st to 8th pixel rows of the odd-numbered pixel column (2m-1st pixel column). do. Next, the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the even-numbered pixel column (2m-th pixel column), and from the odd-numbered pixel column (2m-1st pixel column) to the odd-numbered pixels. The image data is aligned so that the data voltage can be supplied continuously to pixels of the same color, 8 alternately in the even-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Image data (Data) for at least one horizontal line is supplied to the data driver 300.

In addition, the timing control unit 500 operates the first gate line (GL1) according to the data voltage supply order of odd-numbered data lines (2m-1-th data lines) and even-numbered data lines (2m-th data lines). ), a gate control signal (GVS) is generated and transmitted to the gate driver 200 so that the gate-on voltage is supplied to the entire gate line (GLn). Accordingly, the gate driver 200 operates the first gate line (GL1) according to the data voltage supply order of the odd-numbered data lines (2m-1-th data lines) and the even-numbered data lines (2m-th data lines). The gate-on voltage is sequentially supplied to all gate lines (GLn).

The data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially applies the gate-on voltage to each gate line (GL1 to GLn) during the first frame period. In accordance with the supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, in the case of odd-numbered data lines (2m-1th data lines), the pixels (G1 to G4) arranged in the first to fourth pixel rows of the odd-numbered pixel column (2m-1th pixel column) After the data voltage is supplied continuously in order, the data voltage is supplied in succession to the pixels (R1 to R8) arranged in the first to eighth pixel rows of the even-numbered pixel column (2m pixel column). Next, the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the odd-numbered pixel column (2m-1st pixel column), and from the even-numbered pixel column (2m-1st pixel column) to the even-numbered pixel rows. The data voltage is continuously supplied to eight pixels of the same color alternately in the (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column).

At the same time, in the case of the even-numbered data lines (2m-th data lines), the pixels (B1 to B4) arranged in the first to fourth pixel rows of the even-numbered pixel column (2m-th pixel column) continue in order. After the data voltage is supplied, the data voltage is sequentially supplied to the pixels (W1 to W8) arranged in the 1st to 8th pixel rows of the odd-numbered pixel column (2m-1th pixel column). Next, the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the even-numbered pixel column (2m-th pixel column), and from the odd-numbered pixel column (2m-1st pixel column) to the odd-numbered pixels. The data voltage is continuously supplied to eight pixels of the same color alternately in the row (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column).

As described above, according to the third embodiment, up to eight pixels of the same color arranged in the organic light emitting diode display panel 100 alternately emit light in succession, and pixels are displayed in units of odd and even frame periods. They can be driven by changing their driving order. Since the grayscale values of pixels of the same color are generally similar, when up to 8 pixels of the same color are driven continuously, the amount of data voltage variation supplied to each pixel through each data line (DL1 to DLm), And the data voltage charging rate deviation between adjacent pixels can be further reduced.

Figure 13 is a pixel arrangement diagram showing the pixel driving order in the second frame period according to the third embodiment of the present invention.

The timing control unit 500 controls even-numbered pixels through odd-numbered data lines (2m-1-th data lines) during a 2nd frame period of a plurality of preset frame periods, for example, an 8-frame period. The data voltage is first supplied to the pixel R1 arranged in the first pixel row of the column (2m-th pixel column), and then to the first to fifth pixel rows of the odd-numbered pixel column (2m-1st pixel column). The image data is arranged so that the data voltage is supplied sequentially to the pixels of the same color, including the arranged pixels (G1 to G5). And, starting from the even-numbered pixel column (2m-th pixel column), eight pixels of the same color are sequentially displayed alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). Align the image data (RGB) so that the data voltage can be supplied.

In the case of even-numbered data lines (2m-th data lines), the data voltage is first supplied to the pixel (W1) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column), The image data is arranged so that data voltages are sequentially supplied to pixels of the same color, including pixels (B1 to B5) arranged in the first to fifth pixel rows of the even-numbered pixel column (2m pixel column). And again, from the odd-numbered pixel column (2m-1st pixel column), eight pixels of the same color are alternately placed in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-1st pixel column). The image data is aligned so that the data voltage can be continuously supplied to the data driver 300, and at least one horizontal line of image data (Data) of the aligned frames is supplied to the data driver 300.

The timing control unit 500 operates from the first gate line (GL1) to the entire data voltage supply order of odd-numbered data lines (2m-1th data lines) and even-numbered data lines (2m-th data lines). A gate control signal (GVS) is generated and transmitted to the gate driver 200 so that the gate-on voltage is supplied to the gate line (GLn). Accordingly, the gate driver 200 operates the first gate line (GL1) according to the data voltage supply order of the odd-numbered data lines (2m-1-th data lines) and the even-numbered data lines (2m-th data lines). The gate-on voltage is sequentially supplied to all gate lines (GLn).

The data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially applies the gate-on voltage to each gate line (GL1 to GLn) during the first frame period. In accordance with the supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the data voltage is first supplied to the pixel R1 arranged in the first pixel row of the even-numbered pixel column (2m-th pixel column) through the odd-numbered data lines (2m-1th data lines), and then , the data voltage is continuously supplied to the pixels of the same color in order, including the pixels (G1 to G5) arranged in the first to fifth pixel rows of the odd-numbered pixel column (2m-1th pixel column). And, starting from the even-numbered pixel column (2m-th pixel column), eight pixels of the same color are sequentially displayed alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). Data voltage is supplied.

In the case of even-numbered data lines (2m-th data lines), the data voltage is first supplied to the pixel (W1) arranged in the first pixel row of the odd-numbered pixel column (2m-1st pixel column), Data voltages are sequentially supplied to pixels of the same color, including pixels (B1 to B5) arranged in the first to fifth pixel rows of the even-numbered pixel column (2m pixel column). And from the odd-numbered pixel column (2m-1st pixel column), eight pixels of the same color are displayed alternately in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-1st pixel column). The data voltage is supplied.

In this way, starting from the second frame, the timing control unit 500 causes the driving order of the pixels P that were driven during the first frame period to be driven in a manner that is shifted by one horizontal line.

Figure 14 is a pixel arrangement diagram showing the pixel driving order of the third frame period according to the third embodiment of the present invention.

Referring to FIG. 14, the timing control unit 500 controls odd-numbered data lines (2m-1-th data lines) during a plurality of preset frame periods, for example, the 3rd frame period of an 8-frame period. ), data voltages are first successively supplied to the pixels (R1, R2) arranged in the first and second pixel rows of the even-numbered pixel column (2m-1st pixel column), and then The image data (RGB) is aligned so that data voltages are sequentially supplied to the pixels of the same color, including the pixels (G1 to G6) arranged in the first to sixth pixel rows of the pixel row. And, starting from the even-numbered pixel column (2m-th pixel column), eight pixels of the same color are sequentially displayed alternately in the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). Align the image data (RGB) so that the data voltage can be supplied.

At this time, in the case of even-numbered data lines (2m-th data lines), the pixels (W1, W2) arranged in the first and second pixel rows of the odd-numbered pixel column (2m-1st pixel column) are ordered first. After the data voltage is supplied as shown, the image data (RGB) is supplied sequentially to the pixels (B1 to B6) arranged in the first to sixth pixel rows of the even-numbered pixel column (2m pixel column). ) are sorted. And again, starting from the odd-numbered pixel column (2m-1st pixel column), eight pixels of the same color are alternately placed in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). The image data is aligned so that the data voltage can be continuously supplied, and the image data (Data) of the aligned frames is supplied to the data driver 300 for at least one horizontal line.

The timing control unit 500 operates from the first gate line (GL1) to the entire data voltage supply order of odd-numbered data lines (2m-1th data lines) and even-numbered data lines (2m-th data lines). A gate control signal (GVS) is generated and transmitted to the gate driver 200 so that the gate-on voltage is supplied to the gate line (GLn). Accordingly, the gate driver 200 operates the first gate line (GL1) according to the data voltage supply order of the odd-numbered data lines (2m-1-th data lines) and the even-numbered data lines (2m-th data lines). The gate-on voltage is sequentially supplied to all gate lines (GLn).

The data driver 300 converts the image data (Data) sorted by the timing control unit 500 into a data voltage for one horizontal line, and sequentially applies the gate-on voltage to each gate line (GL1 to GLn) during the first frame period. In accordance with the supply timing, the data voltage is supplied to all odd-numbered and even-numbered data lines (DL1 to DLm) in units of one horizontal period.

Accordingly, the data voltage is first successively supplied to the first and second pixels of the even-numbered pixel column (2m-th pixel column) through the odd-numbered data lines (2m-1-th data lines), and then the odd-numbered data The data voltage is supplied continuously in order to the pixels of the same color from the very first to the sixth pixel of the odd-numbered pixel column (2m-1st pixel column) of the lines (2m-1th data lines), and then again. Starting from the even-numbered pixel column (2m-th pixel column), the data voltage is continuously applied to pixels of the same color, eight in a row, alternating between the even-numbered pixel column (2m-th pixel column) and the odd-numbered pixel column (2m-1st pixel column). This supply is supplied.

At the same time, in the case of the even-numbered data lines (2m-th data lines), the data voltage is supplied sequentially to the first and second pixels of the odd-numbered pixel column (2m-1st pixel column), and then to the even-numbered pixel column. Data voltage is supplied sequentially to pixels of the same color from the first to the sixth pixel of the pixel column (2mth pixel column). And again, starting from the odd-numbered pixel column (2m-1st pixel column), eight pixels of the same color are alternately placed in the odd-numbered pixel column (2m-1st pixel column) and the even-numbered pixel column (2m-th pixel column). Data voltage is continuously supplied to .

In this way, after the first frame period, the timing control unit 500 operates from the second frame to the eighth frame period in such a way that the driving order of the pixels (P) driven in the first frame period is shifted sequentially by 1 horizontal line to 8 horizontal lines. It can be done as much as possible.

As described above, the organic light emitting diode display device and its driving method according to an embodiment of the present invention drive the organic light emitting diode display panel 100 in a DRD (Double Rating Driving) method, thereby driving the data lines DL1 to DLm. ) and the number of channels connected to the data lines can be reduced by half and the configuration of the data driver can be simplified.

In addition, the pixels (P) of the same color arranged in the organic light emitting diode display panel 100 are allowed to emit light continuously, and the driving order of the pixels (P) is varied by at least one frame, thereby driving the data line ( It is possible to reduce the amount of data voltage variation supplied to each pixel (P) through DL1 to DLm and the data voltage charging rate deviation between adjacent pixels.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is commonly known in the technical field to which the present invention pertains that various substitutions, modifications, and changes can be made without departing from the technical details of the present invention. It will be clear to those who have the knowledge of. Therefore, the scope of the present invention is indicated by the claims described later, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention.

100: Organic light emitting diode display panel
200: Gate driver
300: data driving unit
400: power supply unit
500: Timing control unit

Claims (20)

An organic light emitting diode display panel in which pixels adjacent to each other along the gate line direction are arranged in pairs in pixel areas defined by a plurality of gates and data lines, each sharing one data line;
A timing control unit that aligns and outputs image data so that pixels of the same color can continuously emit light along the data line direction while the arrayed pixels are driven in a DRD manner, and generates and outputs gate and data control signals;
a gate driver outputting a gate on signal to the gate lines according to the gate control signal;
A data driver generating a data voltage to correspond to the image data aligned in the timing control unit and outputting the data voltage to each data line in synchronization with the output timing of the gate on signal according to the data control signal,
Each pixel adjacent to each other in the data line direction receives a gate on signal from a different gate line,
Among the pixels arranged in the same pixel row, the pixels in the 4m-3th pixel row and the pixels in the 4m-th pixel row receive a gate on signal from the odd-numbered 2n-1th gate line arranged closest to them,
Among the pixels arranged in the same pixel row, the pixels in the 4m-2nd pixel row and the pixels in the 4m-1st pixel row are connected to receive a gate on signal from the even-numbered 2nth gate line arranged most adjacent to each other, an organic light emitting device. Diode display.
According to claim 1,
The organic light emitting diode display panel is
The number of data lines is arranged to be halved by half compared to the total number of pixel rows, and the number of total gate lines is arranged to be doubled compared to the total number of pixel rows,
Each pixel is disposed in a pixel area defined by the intersection of two gate lines and one data line,
Each pixel is a pair of pixels adjacent to each other in the gate line direction, sharing one data line,
Organic light emitting diode display device.
delete According to claim 2,
The timing control unit
The image data is stored so that pixels of the same color arranged along the data line direction can continuously emit light in a plurality of horizontal periods, and the driving order of each pixel can be varied and driven by at least one frame. Sorted by frame and transmitted to the data driver,
Organic light emitting diode display device.
According to claim 4,
The timing control unit, in the odd-numbered frame period,
Through the odd-numbered data lines, the data voltage is supplied to the pixels arranged in the first pixel row of the odd-numbered pixel column, and then continuously to the same color pixels arranged in the first and second pixel rows of the even-numbered pixel column. The data voltage is supplied, and then the data voltage is continuously supplied to the pixels of the same color arranged in the second and third pixel rows of the odd-numbered pixel column, and then again arranged in the third and fourth pixel rows of the even-numbered pixel column. A method of supplying data voltage continuously to pixels of the same color, so that from the even-numbered pixel column, the data voltage can be supplied alternately to two pixels of the same color arranged in the even-numbered pixel column and the odd-numbered pixel column. sort the data,
A data voltage is supplied to the pixels arranged in the first pixel row of the even-numbered pixel column through the even-numbered data lines, and then continuously supplied to the pixels of the same color arranged in the first and second pixel rows of the odd-numbered pixel column. Then, the data voltage is supplied continuously to the pixels of the same color arranged in the second and third pixel rows of the even-numbered pixel column, and then again to the third and fourth pixel rows of the odd-numbered pixel column. This is a method of supplying data voltage continuously to pixels of the same color arranged in a pixel row. Starting from the odd-numbered pixel column, the data voltage is supplied continuously to two pixels of the same color alternately in the odd-numbered pixel column and the even-numbered pixel column. Sorting the image data so that it can be supplied, and supplying the image data of the aligned frames to the data driver at least one horizontal line
Organic light emitting diode display device.
According to claim 4,
The timing control unit
The timing control unit operates in the first frame period, which is the 4n-3th frame period,
After the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the odd-numbered pixel column through the odd-numbered data lines, the four identical pixels arranged in the first to fourth pixel rows of the even-numbered pixel column The data voltage is supplied continuously to the pixels of each color, and the data voltage is supplied continuously to the four pixels of the same color arranged in the third to sixth pixel rows of the odd-numbered pixel row. Starting from the pixel column, the image data is arranged so that the data voltage is continuously supplied to four pixels of the same color arranged in the even-numbered pixel column and the odd-numbered pixel column,
Through the even-numbered data lines, the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the even-numbered pixel column, and then the four pixel voltages arranged in the first to fourth pixel rows of the odd-numbered pixel column are supplied. The data voltage is supplied continuously to the pixels of the same color, and the data voltage is supplied continuously to the four pixels of the same color arranged in the third to sixth pixel rows of the even-numbered pixel row. Starting from the pixel column, the image data is arranged so that the data voltage can be continuously supplied to four pixels of the same color arranged in the odd-numbered pixel column and the even-numbered pixel column, and supplied to the data driver at least one horizontal line,
8n-6th gate line, 8n-4th gate line, 8n-7th gate line, 8n-5th gate line, 8n-3rd gate line, 8n-1st gate line, 8n-2nd gate line, 8n Generating the gate control signal and transmitting it to the gate driver so that the gate-on voltage is supplied to all gate lines in the order of the th gate line,
Organic light emitting diode display device.
According to claim 6,
The timing controller operates in the second frame period, which is the 4n-2th frame period,
Through the odd-numbered data lines, data voltages are continuously supplied to the pixels arranged in the first and second pixel rows of the even-numbered pixel column, and then the four pixel voltages arranged in the first to fourth pixel rows of the odd-numbered pixel column are supplied. A method of arranging image data so that data voltage is continuously supplied to pixels of the same color, and data voltage is continuously supplied to four pixels of the same color arranged in the third to sixth pixel rows of the even-numbered pixel column. Starting from the odd-numbered pixel column, the image data is aligned so that the data voltage is supplied alternately to pixels of the same color, four in a row, alternately in the odd-numbered pixel column and the even-numbered pixel column,
After the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the odd-numbered pixel column through the even-numbered data lines, the 4th pixel arranged in the first to fourth pixel rows of the even-numbered pixel column Arranges image data so that data voltage is continuously supplied to pixels of the same color, and data voltage is supplied continuously to four pixels of the same color arranged in the third to sixth pixel rows of the odd-numbered pixel row. In this way, starting from the even-numbered pixel column, the image data is aligned and supplied to the data driver so that data voltages can be continuously supplied to pixels of the same color, 4 alternately in the even-numbered pixel column and the odd-numbered pixel column,
8n-7th gate line, 8n-5th gate line, 8n-6th gate line, 8n-4th gate line, 8n-2th gate line, 8n-th gate line, 8n-3rd gate line, 8n-1 A gate control signal is generated and transmitted to the gate driver so that the gate-on voltage is supplied to all gate lines in the order of the second gate line.
Organic light emitting diode display device.
According to claim 7,
The timing control unit
In the 3rd frame period, which is the 4n-1th frame period, the image data is sorted and supplied to the data driver so that the driving order of the pixels driven in the 4n-3rd frame period is driven in a form shifted by 1 horizontal line, and at the same time, gate control is performed. Generating a signal and transmitting it to the gate driver,
In the 4th frame period, which is the 4nth frame period, each pixel is driven in the opposite order to the driving order of the pixels in the 4n-1th frame period, and the driving order of the pixels that were driven in the 4n-2th frame period Sorting the image data so that it is driven in a 1-horizontal line shift form and supplying it to the data driver, while simultaneously generating a gate control signal and transmitting it to the gate driver,
Organic light emitting diode display device.
According to claim 4,
The timing control unit
The timing control unit operates in a first frame period among a plurality of preset frame periods,
The data voltage is supplied sequentially through the odd-numbered data lines to the pixels arranged in the first to fourth pixel rows of the odd-numbered pixel column, and then to the pixels arranged in the first to eighth pixel rows of the even-numbered pixel column. The image data is arranged so that the data voltage is supplied continuously in order, and the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the odd-numbered pixel row, starting from the even-numbered pixel row to the even-numbered pixels. Arranging the image data so that data voltages are continuously supplied to eight pixels of the same color alternately in each row and odd-numbered pixel columns,
Through the even-numbered data lines, the data voltage is supplied sequentially to the pixels arranged in the first to fourth pixel rows of the even-numbered pixel column, and then to the pixels arranged in the first to eighth pixel rows of the odd-numbered pixel column. The image data is arranged so that the data voltage is supplied continuously in order, and the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the even-numbered pixel row, starting from the odd-numbered pixel row to the odd-numbered pixel rows. Aligning image data so that data voltages can be continuously supplied to eight pixels of the same color alternately in the pixel column and the even-numbered pixel column and supplying the image data to the data driver,
Organic light emitting diode display device.
According to clause 9,
The timing control unit sorts the image data so that the driving order of the pixels driven in the first frame period is sequentially shifted by one horizontal line for a plurality of preset frame periods starting from the second frame after the first frame period and supplies the image data to the data driver. doing,
Organic light emitting diode display device.
An organic light emitting diode display device having an organic light emitting diode display panel arranged in pixel areas defined by a plurality of gates and data lines, with pixels adjacent to each other along the gate line direction forming pairs and sharing one data line. In the driving method,
Aligning and outputting image data so that pixels of the same color can continuously emit light along the data line direction while the arrayed pixels are driven in the DRD method, and generating and outputting gate and data control signals do,
Each pixel adjacent to each other in the data line direction receives a gate on signal from a different gate line,
Among the pixels arranged in the same pixel row, the pixels in the 4m-3th pixel row and the pixels in the 4m-th pixel row receive a gate on signal from the odd-numbered 2n-1th gate line arranged closest to them,
Among the pixels arranged in the same pixel row, the pixels in the 4m-2nd pixel row and the pixels in the 4m-1st pixel row are connected to receive a gate on signal from the even-numbered 2nth gate line arranged most adjacent to each other, an organic light emitting device. How to drive a diode display device.
According to claim 11,
The organic light emitting diode display panel is
The number of data lines is arranged to be halved by half compared to the total number of pixel rows, and the number of total gate lines is arranged to be doubled compared to the total number of pixel rows,
Each pixel is disposed in a pixel area defined by the intersection of two gate lines and one data line,
Each pixel is a pair of pixels adjacent to each other in the gate line direction, sharing one data line,
Method of driving an organic light emitting diode display device.
delete According to claim 12,
The image data sorting step is
The image data is stored so that pixels of the same color arranged along the data line direction can continuously emit light in a plurality of horizontal periods, and the driving order of each pixel can be varied and driven by at least one frame. Sorting by frame,
Method of driving an organic light emitting diode display device.
According to claim 14,
The image data sorting step is
In the odd-numbered frame period, the data voltage is supplied to the pixels arranged in the first pixel row of the odd-numbered pixel column through the odd-numbered data lines, and then the same color is placed in the first and second pixel rows of the even-numbered pixel column. The data voltage is continuously supplied to the pixels, and then the data voltage is continuously supplied to the pixels of the same color arranged in the second and third pixel rows of the odd-numbered pixel row, and again to the third and third pixel rows of the even-numbered pixel row. Data voltage is supplied continuously to pixels of the same color arranged in 4 pixel rows, and from the even-numbered pixel column, the data voltage is alternately supplied to two pixels of the same color arranged in the even-numbered and odd-numbered pixel columns. Sorting image data so that it can be supplied,
A data voltage is supplied to the pixels arranged in the first pixel row of the even-numbered pixel column through the even-numbered data lines, and then continuously supplied to the pixels of the same color arranged in the first and second pixel rows of the odd-numbered pixel column. Then, the data voltage is supplied continuously to the pixels of the same color arranged in the second and third pixel rows of the even-numbered pixel column, and then again to the third and fourth pixel rows of the odd-numbered pixel column. This is a method of supplying data voltage continuously to pixels of the same color arranged in a pixel row. Starting from the odd-numbered pixel column, the data voltage is supplied continuously to two pixels of the same color alternately in the odd-numbered pixel column and the even-numbered pixel column. comprising arranging the image data so that it can be supplied.
Method of driving an organic light emitting diode display device.
According to claim 14,
The image data sorting step is
In the first frame period, which is the 4n-3rd frame period,
After the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the odd-numbered pixel column through the odd-numbered data lines, the four identical pixels arranged in the first to fourth pixel rows of the even-numbered pixel column The data voltage is supplied continuously to the pixels of each color, and the data voltage is supplied continuously to the four pixels of the same color arranged in the third to sixth pixel rows of the odd-numbered pixel row. Sorting the image data so that data voltages can be continuously supplied to four pixels of the same color arranged in even-numbered pixel columns and odd-numbered pixel columns, starting from the pixel column;
Through the even-numbered data lines, the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the even-numbered pixel column, and then the four pixel voltages arranged in the first to fourth pixel rows of the odd-numbered pixel column are supplied. The data voltage is supplied continuously to the pixels of the same color, and the data voltage is supplied continuously to the four pixels of the same color arranged in the third to sixth pixel rows of the even-numbered pixel row. Starting from the pixel column, aligning the image data so that data voltages can be continuously supplied to four pixels of the same color arranged in the odd-numbered pixel column and the even-numbered pixel column,
Method of driving an organic light emitting diode display device.
According to claim 16,
The image data sorting step is
In the second frame period, which is the 4n-2th frame period, after the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the even-numbered pixel column through the odd-numbered data lines, the data voltage of the odd-numbered pixel column is The image data is arranged so that data voltages are continuously supplied to the four pixels of the same color arranged in the first to fourth pixel rows, and the four pixels of the same color arranged in the third to sixth pixel rows of the even-numbered pixel rows. In such a way that the data voltage is continuously supplied to the pixels, starting from the odd-numbered pixel column, the data voltage can be supplied continuously and alternately to pixels of the same color, four in a row, alternately in the odd-numbered pixel column and the even-numbered pixel column. Sorting the image data, and
After the data voltage is continuously supplied to the pixels arranged in the first and second pixel rows of the odd-numbered pixel column through the even-numbered data lines, the 4th pixel rows arranged in the first to fourth pixel rows of the even-numbered pixel column Arranges image data so that data voltage is continuously supplied to pixels of the same color, and data voltage is supplied continuously to four pixels of the same color arranged in the third to sixth pixel rows of the odd-numbered pixel row. The method includes arranging the image data so that data voltages are continuously supplied to pixels of the same color, four in a row, starting from the even-numbered pixel column and alternating between the even-numbered pixel column and the odd-numbered pixel column.
Method of driving an organic light emitting diode display device.
According to claim 17,
The image data sorting step is
In the third frame period, which is the 4n-1th frame period, arranging the image data so that the driving order of the pixels driven in the 4n-3th frame period is driven in a form shifted by one horizontal line;
In the 4th frame period, which is the 4nth frame period, each pixel is driven in the opposite order to the driving order of the pixels in the 4n-1th frame period, and the driving order of the pixels that were driven in the 4n-2th frame period Comprising the step of aligning the image data so that it is driven in a 1-horizontal line shifted form,
Method of driving an organic light emitting diode display device.
According to claim 14,
The image data sorting step is
During the first frame period of a plurality of preset frame periods, the data voltage is supplied sequentially through the odd-numbered data lines to the pixels arranged in the first to fourth pixel rows of the odd-numbered pixel column, and then to the even-numbered pixel. Arrange the image data so that data voltages are supplied continuously in order to the pixels arranged in the first to eighth pixel rows of the column, and data voltages are supplied to the pixels arranged in the fifth to twelfth pixel rows of the odd-numbered pixel rows. In this way, the image data is arranged so that the data voltage is continuously supplied to eight pixels of the same color, starting from the even-numbered pixel column, alternately in the even-numbered pixel column and the odd-numbered pixel column,
Through the even-numbered data lines, the data voltage is supplied sequentially to the pixels arranged in the first to fourth pixel rows of the even-numbered pixel column, and then to the pixels arranged in the first to eighth pixel rows of the odd-numbered pixel column. The image data is arranged so that the data voltage is supplied continuously in order, and the data voltage is supplied to the pixels arranged in the 5th to 12th pixel rows of the even-numbered pixel row, starting from the odd-numbered pixel row to the odd-numbered pixel rows. Comprising the step of aligning the image data so that data voltages can be continuously supplied to eight pixels of the same color alternately in the pixel column and the even-numbered pixel column,
Method of driving an organic light emitting diode display device.
According to claim 19,
The image data sorting step is
After the first frame period, arranging the image data so that the driving order of the pixels driven in the first frame period is sequentially shifted by one horizontal line for a plurality of preset frame periods starting from the second frame,
Method of driving an organic light emitting diode display device.

Images