CN111028814A - Gate driving module, gate driving method and display device - Google Patents
Gate driving module, gate driving method and display device Download PDFInfo
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- CN111028814A CN111028814A CN202010000874.2A CN202010000874A CN111028814A CN 111028814 A CN111028814 A CN 111028814A CN 202010000874 A CN202010000874 A CN 202010000874A CN 111028814 A CN111028814 A CN 111028814A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a grid driving module, a grid driving method and a display device. The grid driving module is used for respectively providing grid driving signals for a plurality of rows of grid lines of the display panel, the display panel comprises a plurality of rows of sub-pixels, and the sub-pixels are respectively electrically connected with the grid lines; the grid driving module comprises a grid driving circuit; the grid driving circuit is used for respectively providing corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode. The invention can improve the bad phenomenon of the head shaking lines.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving module, a gate driving method and a display device.
Background
In the related art, for a dual-gate display panel, the same row of sub-pixels is electrically connected with a first-to-open row gate line and a second-to-open row gate line, because of the dual-gate line design, the second-to-open row gate line is closer to the pixel electrode of the sub-pixel controlled by the first-to-open row gate line, and there is a coupling capacitance between the second-to-open row gate line and the sub-pixel controlled by the first-to-open row gate line; taking a sub-pixel as an example, when an arc scanning mode is adopted, firstly turning on a row grid line to control a thin film transistor included in the sub-pixel to be turned on, when a later-turned-on row grid line is turned on, because of the coupling capacitor, the pixel voltage of the sub-pixel is pulled up, but at the moment, the firstly-turned-on row grid line is still turned on, and then the sub-pixel is pulled back to the charging voltage; then, turning on a row grid line and turning off the row grid line, wherein the pixel voltage of the sub-pixel is pulled down by a coupling offset voltage again due to the grid-source capacitance of the sub-pixel; for the positive sub-pixel, after the two biases, the brightness of the positive sub-pixel is darker; for the sub-pixel with negative polarity, after twice biasing, the brightness of the sub-pixel with negative polarity is biased to be bright.
When the polarity inversion method of the voltage of the pixel electrode adopted by the dual-gate display panel is the column inversion method, since the one column data line is electrically connected with the two columns of pixel circuits, the two columns of positive and two columns of negative polarity distribution is presented in the AA area (effective display area), brightness difference exists between the positive and negative polarities, taking the red sub-pixel as an example, the voltage polarity of the pixel electrode included in each column of red sub-pixel is periodically cycled in positive polarity, negative polarity and positive polarity in sequence within the display time of the same frame, and the adjacent brightness of the positive polarity and the negative polarity can be averaged, but when the same polarity is adjacent, the brightness cannot be averaged, and the brightness needs to be averaged through the brightness of two frames after the polarity of the next frame is inverted. When continuously observing, the polarity of each frame is reversed, and the superposition of the brightness of each column of sub-pixels between adjacent frames can be averaged; however, when the head moves, frames may be lost, which causes that the two spatially non-averaged columns of sub-pixels lose the time averaging effect, and a periodic vertical stripe is generated, which may result in poor moving-head stripe.
Disclosure of Invention
The invention mainly aims to provide a gate driving module, a gate driving method and a display device, which are used for improving the poor phenomenon of head shaking of the conventional display panel.
In order to achieve the above object, the present invention provides a gate driving module for providing gate driving signals to a plurality of rows of gate lines included in a display panel, wherein the display panel includes a plurality of rows of sub-pixels, and the sub-pixels are electrically connected to the two rows of gate lines; the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
In implementation, the gate driving circuit is configured to provide a 2a-1 gate driving signal for a 2a-1 th row of gate lines and provide a 2a gate driving signal for a 2 nd row of gate lines, so as to control the 2a-1 th row of gate lines to be opened before the 2a 2 nd row of gate lines, and control a time when the 2a-1 th row of gate lines is switched from an open state to a closed state to correspond to a time when the 2a th row of gate lines is switched from a closed state to an open state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
The invention also provides a gate driving method applied to the gate driving module, and the gate driving method comprises the following steps:
the grid driving circuit provides corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
In implementation, the gate driving method specifically includes: the gate driving circuit provides a 2a-1 gate driving signal for a 2a-1 row of gate lines, and provides a 2a gate driving signal for a 2a row of gate lines, so as to control the 2a-1 row of gate lines to be opened before the 2a row of gate lines, and control the time when the 2a-1 row of gate lines is switched from an open state to a closed state to correspond to the time when the 2a row of gate lines is switched from a closed state to an open state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
The invention also provides a display device, which comprises a display panel and the grid drive module;
the display panel comprises a plurality of rows of grid lines and a plurality of rows of sub-pixels, and the sub-pixels in one row are electrically connected with the grid lines in two rows respectively.
In the implementation process, the sub-pixels at the odd-numbered rows of the 2n-1 are electrically connected with the grid lines of the 2n-1 row, and the sub-pixels at the even-numbered rows of the 2n-1 row are electrically connected with the grid lines of the 2n row;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing mutually opposite grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In the implementation process, the sub-pixels at the odd-numbered rows of the 2n-1 are electrically connected with the grid lines of the 2n-1 row, and the sub-pixels at the even-numbered rows of the 2n-1 row are electrically connected with the grid lines of the 2n row;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for providing grid driving signals for the 2n-1 th grid line and the 2n th grid line respectively so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line respectively so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In the implementation process, the sub-pixels at the even rows and the even rows of the 2n-1 are electrically connected with the grid lines at the 2n-1 rows, and the sub-pixels at the odd rows and the odd rows of the 2n-1 are electrically connected with the grid lines at the 2n rows;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In the implementation process, the sub-pixels at the even rows and the even rows of the 2n-1 are electrically connected with the grid lines at the 2n-1 rows, and the sub-pixels at the odd rows and the odd rows of the 2n-1 are electrically connected with the grid lines at the 2n rows;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In operation, the gate drive circuit is further configured to control the 2n +1 th gate drive signal to be delayed by T/2 from the 2n-1 th gate drive signal, and to control the 2n +2 th gate drive signal to be delayed by T/2 from the 2n gate drive signal, and to control the 4m-2 th gate drive signal to be delayed by T/2 from the 4m-1 th gate drive signal; the controller is also used for controlling the delay of the 4m +1 th grid driving signal to be T/2 than the 4m grid driving signal and controlling the delay of the 4m +2 th grid driving signal to be T/2 than the 4m +3 th grid driving signal; m is a positive integer;
t is the time for which the grid line is opened for one time;
the 2n +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +1 th row of gate lines, the 2n-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n-1 th row of gate lines, the 2n +2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +2 th row of gate lines, the 2n th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n th row of gate lines, the 4m-2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-2 th row of gate lines, the 4m-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-1 th row of gate lines, and the 4m +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m +1 th row of gate lines, the 4 m-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4 m-th row, the 4m + 2-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 2-th row, and the 4m + 3-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 3-th row.
Compared with the prior art, the grid driving module, the grid driving method and the display device respectively provide corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels through the grid driving circuit, so that the pre-opened grid lines and the post-opened grid lines which provide the grid driving signals for the same row of sub-pixels are set to be opened in a time-sharing mode, the post-opened grid lines cannot have a coupling pull-down effect on the voltage of the pixel electrodes controlled by the pre-opened grid lines, the brightness difference of positive and negative polarities cannot be further increased, and the bad phenomenon of head shaking stripes is improved.
Drawings
Fig. 1 is a schematic diagram of three rows and three columns of sub-pixels, six rows of gate lines, and three columns of data lines included in a dual gate display panel;
fig. 2 is a waveform diagram of a first Gate driving signal provided by a Gate driving circuit to a Gate1, a waveform diagram of a second Gate driving signal provided by the Gate driving circuit to a Gate2, a waveform diagram of a third Gate driving signal provided by the Gate driving circuit to a Gate3, and a waveform diagram of a fourth Gate driving signal provided by the Gate driving circuit to a Gate4 in the Gate driving module according to the embodiment of the invention;
fig. 3 is a schematic diagram of the pixel voltage of R11 increased on the basis of fig. 2;
FIG. 4 is a diagram illustrating an embodiment of a dual gate display panel as shown in FIG. 1 when an arcuate scan is employed in the related art;
fig. 5 is a schematic diagram showing the positive and negative polarities of the voltages of the pixel electrodes (i.e., the pixel voltages) included in the sub-pixels in each row and each column in fig. 1;
fig. 6 is a waveform diagram of a first Gate driving signal supplied from a Gate1 and a waveform diagram of a second Gate driving signal supplied from a Gate2 when the double Gate display panel shown in fig. 1 is subjected to an arcuate scan in the related art;
fig. 7 is a diagram of the pixel voltage of R11 increased on the basis of fig. 6.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The switching tubes adopted in all the embodiments of the invention can be triodes, thin film switching tubes or field effect tubes or other devices with the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the switch except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In actual operation, when the switching tube is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In actual operation, when the switch tube is a thin film switch tube or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The gate driving module is used for respectively providing gate driving signals for a plurality of rows of grid lines of a display panel, the display panel comprises a plurality of rows of sub-pixels, and the sub-pixels are respectively electrically connected with the grid lines; the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
Aiming at the bad phenomenon of the shaking head of the existing Dual Gate display panel, the Gate drive circuit included in the Gate drive module of the embodiment of the invention respectively provides corresponding Gate drive signals for two rows of Gate lines electrically connected with the same row of sub-pixels, so that the line Gate lines which are firstly opened and the line Gate lines which are later opened and are used for providing the Gate drive signals for the same row of sub-pixels are set to be opened in a time-sharing way, the line Gate lines which are later opened can not have the coupling and pulling-down effect on the voltage of the pixel electrode controlled by the line Gate lines which are firstly opened, the brightness difference of positive and negative polarities can not be further increased, and the bad phenomenon of the shaking head can be improved.
In the embodiment of the present invention, the display panel may be a liquid crystal display panel, but is not limited thereto.
In the embodiment of the present invention, the Dual Gate display panel means that a row of sub-pixels included in the display panel is electrically connected to two rows of Gate lines, for example, odd columns of sub-pixels included in the row of sub-pixels included in the display panel are electrically connected to a row of Gate lines, and even columns of sub-pixels included in the row of sub-pixels included in the display panel are electrically connected to another column of Gate lines, but not limited thereto.
In a specific implementation, the sub-pixel may include a pixel electrode and a thin film transistor;
the thin film transistor can be an n-type thin film transistor, but is not limited thereto;
the grid electrode of the thin film transistor is electrically connected with the corresponding row grid line, the drain electrode of the thin film transistor is electrically connected with the pixel electrode, and the source electrode of the thin film transistor is electrically connected with the corresponding column data line.
Fig. 1 shows three rows and three columns of sub-pixels, six rows of gate lines, and three columns of data lines included in a dual gate display panel;
in fig. 1, a Gate1 is a first row of Gate lines, a Gate2 is a second row of Gate lines, a Gate3 is a third row of Gate lines, a Gate4 is a fourth row of Gate lines, a Gate5 is a fifth row of Gate lines, a Gate6 is a sixth row of Gate lines, a S1 is a first column of data lines, a S2 is a second column of data lines, a S3 is a second column of data lines, a TX1 is a first touch line, and a TX2 is a second touch line;
the reference numeral R11 is a first row and first column pixel electrode, the reference numeral G12 is a first row and second column pixel electrode, and the reference numeral G13 is a first row and third column pixel electrode;
the first row and first column of sub-pixels are red sub-pixels, the first row and first column of sub-pixels comprise R11 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate1, and R11 is electrically connected with S1 through the thin film transistors;
the first row and second column of sub-pixels are green sub-pixels, the first row and second column of sub-pixels comprise G12 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate2, and G12 is electrically connected with S1 through the thin film transistors;
the first row and the third column of the sub-pixels are blue sub-pixels, the first row and the third column of the sub-pixels comprise B13 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate1, and B13 is electrically connected with S2 through the thin film transistors;
the reference numeral R14 is a first row and fourth column pixel electrode, the reference numeral G15 is a first row and fifth column pixel electrode, and the reference numeral G16 is a first row and sixth column pixel electrode;
the first row and fourth column of sub-pixels are red sub-pixels, the first row and fourth column of sub-pixels comprise R14 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate2, and R14 is electrically connected with S2 through the thin film transistors;
the first row and the fifth column of sub-pixels are green sub-pixels, the first row and the fifth column of sub-pixels comprise G15 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate1, and G15 is electrically connected with S3 through the thin film transistors;
the first row and sixth column of sub-pixels are blue sub-pixels, the first row and sixth column of sub-pixels comprise B16 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate2, and B16 is electrically connected with S3 through the thin film transistors;
the reference numeral R21 denotes a pixel electrode of a first column in a second row, the reference numeral G22 denotes a pixel electrode of a second column in a second row, and the reference numeral G23 denotes a pixel electrode of a third column in a second row;
the second row and first column of sub-pixels are red sub-pixels, the second row and first column of sub-pixels comprise R21 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate3, and R21 is electrically connected with S1 through the thin film transistors;
the second row and second column of sub-pixels are green sub-pixels, the second row and second column of sub-pixels comprise G22 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate4, and G22 is electrically connected with S1 through the thin film transistors;
the second row and the third column of the sub-pixels are blue sub-pixels, the second row and the third column of the sub-pixels comprise B23 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate3, and B23 is electrically connected with S2 through the thin film transistors;
a pixel electrode labeled R24, a pixel electrode labeled G25, a pixel electrode labeled G26, a pixel electrode labeled C, a pixel electrode labeled G26, a pixel electrode labeled G;
the second row and the fourth column of the sub-pixels are red sub-pixels, the second row and the fourth column of the sub-pixels comprise R24 and corresponding thin film transistors, the grid electrodes of the thin film transistors are electrically connected with a Gate4, and R24 is electrically connected with S2 through the thin film transistors;
the second row and the fifth column of sub-pixels are green sub-pixels, the second row and the fifth column of sub-pixels comprise G25 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate3, and G25 is electrically connected with S3 through the thin film transistors;
the second row and sixth column of sub-pixels are blue sub-pixels, the second row and sixth column of sub-pixels comprise B26 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate4, and B26 is electrically connected with S3 through the thin film transistors;
a third row and first column of pixel electrodes denoted by the reference numeral R31, a third row and second column of pixel electrodes denoted by the reference numeral G32, and a third row and third column of pixel electrodes denoted by the reference numeral G33;
the third row and first column of sub-pixels are red sub-pixels, the third row and first column of sub-pixels comprise R31 and corresponding thin film transistors, the grid electrodes of the thin film transistors are electrically connected with a Gate5, and R31 is electrically connected with S1 through the thin film transistors;
the third row and second column of sub-pixels are green sub-pixels, the third row and second column of sub-pixels comprise G32 and corresponding thin film transistors, the grid electrodes of the thin film transistors are electrically connected with a Gate6, and G32 is electrically connected with S1 through the thin film transistors;
the third row and the third column of sub-pixels are blue sub-pixels, the third row and the third column of sub-pixels comprise B33 and corresponding thin film transistors, the grid electrodes of the thin film transistors are electrically connected with a Gate5, and B33 is electrically connected with S2 through the thin film transistors;
a pixel electrode labeled R34, a pixel electrode labeled G35, a pixel electrode labeled G36 and a pixel electrode labeled G36;
the third row and fourth column of sub-pixels are red sub-pixels, the third row and fourth column of sub-pixels comprise R34 and corresponding thin film transistors, the grid electrodes of the thin film transistors are electrically connected with a Gate6, and R34 is electrically connected with S2 through the thin film transistors;
the third row and fifth column of sub-pixels are green sub-pixels, the third row and fifth column of sub-pixels comprise G35 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate5, and G35 is electrically connected with S3 through the thin film transistors;
the third row and sixth column of sub-pixels are blue sub-pixels, and the third row and sixth column of sub-pixels comprise B36 and corresponding thin film transistors, the gates of the thin film transistors are electrically connected with a Gate6, and B36 is electrically connected with S3 through the thin film transistors.
In the embodiment of the present invention, the row of gate line open fingers may be: the row gate line provides an effective voltage signal to turn on the thin film transistor whose gate is electrically connected to the row gate line, so that the corresponding column data line electrically connected to the thin film transistor can be connected to the corresponding pixel electrode, but not limited thereto.
When the thin film transistor is an n-type thin film transistor, the effective voltage signal may be a high voltage signal.
For example, in the embodiment of the dual Gate display panel shown in fig. 1, the Gate1 being turned on means: the Gate1 provides a high voltage signal to turn on the thin film transistor whose Gate is electrically connected to the Gate 1.
When the gate driving module according to the embodiment of the present invention is applied to the embodiment of the dual gate display panel shown in fig. 1,
the Gate driving circuit included in the Gate driving module can provide a first Gate driving signal to the Gate1 and a second Gate driving signal to the Gate2, so that the Gate1 and the Gate2 are opened in a time-sharing manner, and the rear Gate2 cannot have a coupling pull-down effect on the voltage of a pixel electrode controlled by the Gate1, so that the brightness difference of positive and negative polarities cannot be further increased, and the bad shaking pattern phenomenon is improved;
the Gate1 controlled pixel electrode may include R11, B13 and G15, but is not limited thereto;
the Gate driving circuit included in the Gate driving module can provide a third Gate driving signal to the Gate3 and a fourth Gate driving signal to the Gate4, so that the Gate3 and the Gate4 are opened in a time-sharing manner, and the rear Gate4 cannot have a coupling pull-down effect on the voltage of a pixel electrode controlled by the Gate3, so that the brightness difference of positive and negative polarities cannot be further increased, and the bad shaking pattern phenomenon is improved;
the Gate3 controlled pixel electrode may include R21, B23 and G25, but is not limited thereto;
the Gate driving circuit included in the Gate driving module can provide a fifth Gate driving signal to the Gate5 and a sixth Gate driving signal to the Gate6, so that the gates 5 and 6 are opened in a time-sharing manner, and the rear Gate6 cannot have a coupling pull-down effect on the voltage of a pixel electrode controlled by the Gate5, so that the brightness difference of positive and negative polarities cannot be further increased, and the bad phenomenon of head shaking patterns is improved;
the Gate5 controlled pixel electrode may include R31, B33 and G35, but is not limited thereto.
Preferably, the gate driving circuit is configured to provide a 2a-1 th gate driving signal for the 2a-1 th row of gate lines, and provide a 2a gate driving signal for the 2a 2 nd row of gate lines, so as to control the 2a-1 th row of gate lines to be opened before the 2a 2 nd row of gate lines, and control a time when the 2a-1 th row of gate lines is switched from an open state to a closed state to correspond to a time when the 2a nd row of gate lines is switched from a closed state to an open state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
In a preferred case, the gate driving circuit can control the post-on row gate line to be turned on at the moment when the pre-on row gate line is switched from the on state to the off state, so that the voltage of the pixel electrode controlled by the pre-on row gate line is pulled down by the pre-on row gate line and simultaneously pulled up by the post-on row coupling, and the self offset voltage △ Vp is reduced, and the difference of positive and negative polarities is reduced, and the following results are obtained by establishing a circuit model simulation:
by adopting the gate driving module provided by the embodiment of the invention, the gray scale difference of the positive and negative polarity rows is 14 gray scales which are reduced to 1 gray scale, so that the wobbling phenomenon is obviously improved;
through practical debugging and verification of the display panel, when the timing sequence design of the embodiment of the invention is adopted, the shaking marks are really and obviously reduced and are matched with a simulation result.
A waveform diagram of a first Gate driving signal provided to the Gate1 by the Gate driving circuit, a waveform diagram of a second Gate driving signal provided to the Gate2 by the Gate driving circuit, a waveform diagram of a third Gate driving signal provided to the Gate3 by the Gate driving circuit, and a waveform diagram of a fourth Gate driving signal provided to the Gate4 by the Gate driving circuit may be as shown in fig. 2.
As shown in fig. 2, the falling edge of the first Gate driving signal corresponds to the rising edge of the second Gate driving signal, and the falling edge of the third Gate driving signal corresponds to the rising edge of the fourth Gate driving signal, i.e., the embodiment of the invention provides a new timing design, in which the Gate line is turned on in sequence, that is, Gate1, Gate3, Gate2 and Gate4 are turned on, so that the on time of Gate2 can be staggered from the on time of Gate1, for example, when Gate1 is turned off and the pixel voltage of R11 is pulled down by Gate1, because the pixel voltage of R11 is simultaneously pulled up by the Gate2 coupling for the rising edge of the second Gate driving signal provided by Gate2, the self-bias voltage △ is reduced, the difference between positive and negative polarities is reduced, and the phenomenon of shaking head is improved.
As shown in fig. 3, the pixel voltage of R11 is added on the basis of fig. 2, wherein the reference numeral △ Vp is the self offset voltage, and the reference numeral △ Vp' is the coupling offset voltage, and it can be seen that △ Vp is smaller, so that the brightness difference of positive and negative polarities is reduced, and the rolling phenomenon is improved.
In the related art, when the polarity inversion method of the voltages of the pixel electrodes employed in the embodiment of the dual-gate display panel shown in fig. 1 is a column inversion method, since the one-column data lines are electrically connected to the two-column pixel circuits, in an AA region (effective display region), two columns of positive polarities and two columns of negative polarities are present, and the positive and negative polarities have luminance differences, in the case of red sub-pixels, the voltage polarities of the pixel electrodes included in each column of red sub-pixels are periodically cycled in the positive polarity, the negative polarity, and the positive polarity in sequence within the same frame display time, and the luminances adjacent to the positive polarity and the negative polarity can be averaged. When continuously observing, the polarity of each frame is reversed, and the superposition of the brightness of each column of sub-pixels between adjacent frames can be averaged; and frame loss may occur when the head moves, which results in that the two spatially non-averageable columns of sub-pixels lose the time-averaging effect and generate periodic vertical stripes.
In the related art, when the dual-Gate display panel adopts the bow-scan mode (the direction indicated by the arrow is the bow-scan direction as shown in fig. 4), as shown in fig. 1, the Gate1 controls the R11, the B13 and the G15, and the Gate2 controls the G12, the R14 and the B16. due to the dual-Gate line design, the Gate2 is closer to the pixel electrode of the sub-pixel controlled by the Gate1, a coupling capacitance Cgp between the sub-pixels controlled by the Gate2 and the Gate1 exists, as for example, for the first row and the first column of red sub-pixels, the Gate Vp 1 controls the thin film transistor included in the first row and the first column of red sub-pixels to be turned on, when the Gate2 is turned on, the pixel voltage of the first row and the first column of red sub-pixels is pulled up, but the Gate1 is still turned on, the first row and the first column of red sub-pixels are pulled back to be charged, then the Gate1 is turned off, as the pixel voltage of the first row and the first column of red sub-pixel is pulled up, as shown by the positive polarity shifting voltage when the voltage of the Gate 466, the Gate 466 is shown in the first row and the first column of the pixel, the positive polarity shifting pixel, the pixel is shown by the positive polarity shifting voltage when the pixel 466, the voltage of the positive polarity of the pixel, the Gate 466, the pixel is shown in the first column of the positive polarity of the first column of the positive sub-pull-pixel, the positive-pixel is shown by the positive-pixel, and the positive-pixel, the positive-polarity shifting voltage of the positive-pixel 466, the positive-polarity shifting voltage is shown in the positive-polarity-.
The gate driving method provided by the embodiment of the invention is applied to the gate driving module, and comprises the following steps:
the grid driving circuit provides corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
Aiming at the bad phenomenon of the shaking head of the existing Dual Gate display panel, the grid driving method provided by the embodiment of the invention respectively provides corresponding grid driving signals for two rows of grid lines which are electrically connected with the same row of sub-pixels through the grid driving circuit so as to set the line of grid lines which are firstly opened and the line of grid lines which are later opened and are used for providing the grid driving signals for the same row of sub-pixels to be opened in a time-sharing way, so that the line of grid lines which are later opened can not have the coupling and pulling-down effect on the voltage of the pixel electrode controlled by the line of grid lines which are firstly opened, the difference of positive and negative polarities can not be further increased, and the bad phenomenon of the shaking head can be improved.
Preferably, the gate driving method may specifically include: the gate driving circuit provides a 2a-1 gate driving signal for a 2a-1 row of gate lines, and provides a 2a gate driving signal for a 2a row of gate lines, so as to control the 2a-1 row of gate lines to be opened before the 2a row of gate lines, and control the time when the 2a-1 row of gate lines is switched from an open state to a closed state to correspond to the time when the 2a row of gate lines is switched from a closed state to an open state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
Preferably, the gate driving circuit may control the last-on row gate line to be turned on at a time when the first-on row gate line is turned from the on state to the off state, so that when the voltage of the pixel electrode controlled by the first-on row gate line is pulled down by the first-on row gate line, the voltage is pulled up by the last-on row coupling at the same time, and thus the self offset voltage △ Vp is reduced, and the difference between positive and negative polarities is reduced.
The display device comprises a display panel and the grid drive module;
the display panel comprises a plurality of rows of grid lines and a plurality of rows of sub-pixels, and the sub-pixels in one row are electrically connected with the grid lines in two rows respectively.
According to a specific implementation mode, the sub-pixels in the odd-numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n-1 rows, and the sub-pixels in the even-numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n rows;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing mutually opposite grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In a specific implementation, the odd-numbered rows and the odd-numbered columns of sub-pixels can be electrically connected with the odd-numbered rows and the even-numbered columns of sub-pixels can be electrically connected with the even-numbered rows and the even-numbered columns of sub-pixels can be electrically connected with the odd-numbered rows and the even-numbered columns of sub-pixels can be electrically connected with the even-numbered rows and the grid lines.
According to another specific implementation mode, the sub-pixels in the odd-numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n-1 rows, and the sub-pixels in the even-numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n rows;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for providing grid driving signals for the 2n-1 th grid line and the 2n th grid line respectively so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line respectively so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In a specific implementation, the odd-numbered rows and the odd-numbered columns of sub-pixels can be electrically connected with the odd-numbered rows and the even-numbered columns of sub-pixels can be electrically connected with the even-numbered rows and the even-numbered columns.
According to another specific embodiment, the sub-pixels in the even numbered columns of the 2n-1 th row are electrically connected with the grid lines in the 2n-1 th row, and the sub-pixels in the odd numbered columns of the 2n-1 th row are electrically connected with the grid lines in the 2n th row;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In a specific implementation, the odd-numbered rows and even-numbered columns of sub-pixels may be electrically connected to the odd-numbered rows and the even-numbered columns of sub-pixels may be electrically connected to the even-numbered rows and the even-numbered columns.
According to another specific embodiment, the sub-pixels in the even numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n-1 rows, and the sub-pixels in the odd numbered rows of the 2n-1 are electrically connected with the grid lines in the 2n rows;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
In a specific implementation, the odd-numbered rows and even-numbered columns of sub-pixels may be electrically connected to the odd-numbered rows of gate lines, the odd-numbered rows and odd-numbered columns of sub-pixels may be electrically connected to the even-numbered rows of gate lines, the even-numbered rows and odd-numbered columns of sub-pixels may be electrically connected to the odd-numbered rows of gate lines, and the even-numbered rows and even-numbered columns of sub-pixels may be electrically connected to the even-.
Preferably, the gate driving circuit is further configured to control the 2n +1 th gate driving signal to be delayed by T/2 from the 2n-1 th gate driving signal, and to control the 2n +2 th gate driving signal to be delayed by T/2 from the 2n gate driving signal, and further configured to control the 4m-2 th gate driving signal to be delayed by T/2 from the 4m-1 th gate driving signal; the controller is also used for controlling the delay of the 4m +1 th grid driving signal to be T/2 than the 4m grid driving signal and controlling the delay of the 4m +2 th grid driving signal to be T/2 than the 4m +3 th grid driving signal; m is a positive integer;
t is the time for which the grid line is opened for one time;
the 2n +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +1 th row of gate lines, the 2n-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n-1 th row of gate lines, the 2n +2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +2 th row of gate lines, the 2n th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n th row of gate lines, the 4m-2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-2 th row of gate lines, the 4m-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-1 th row of gate lines, and the 4m +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m +1 th row of gate lines, the 4 m-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4 m-th row, the 4m + 2-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 2-th row, and the 4m + 3-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 3-th row.
For example, when the sub-pixels in the odd-numbered first row column are electrically connected with the grid line in the first row, the sub-pixels in the even-numbered first row column are electrically connected with the grid line in the second row, the sub-pixels in the odd-numbered second row column are electrically connected with the grid line in the third row, the sub-pixels in the odd-numbered third row column are electrically connected with the grid line in the fifth row, the sub-pixels in the even-numbered third row column are electrically connected with the grid line in the sixth row, the sub-pixels in the odd-numbered fourth row column are electrically connected with the grid line in the seventh row, the sub-pixels in the even-numbered fourth row column are electrically connected with the grid line in the eighth row, the sub-pixels in the odd-numbered fifth row column are electrically connected with the grid line in the ninth row, the sub-pixels in the even-numbered fifth row column are electrically connected with the grid line in the tenth row, the sub-pixels in;
the grid driving circuit scans a first row of grid lines, a third row of grid lines, a second row of grid lines, a fourth row of grid lines, a fifth row of grid lines, a seventh row of grid lines, a sixth row of grid lines, an eighth row of grid lines, a ninth row of grid lines, an eleventh row of grid lines, a tenth row of grid lines and a twelfth row of grid lines in sequence;
the third gate driving signal is delayed by T/2 from the first gate driving signal, the second gate driving signal is delayed by T/2 from the third gate driving signal, the fourth gate driving signal is delayed by T/2 from the second gate driving signal, the fifth gate driving signal is delayed by T/2 from the fourth gate driving signal, the seventh gate driving signal is delayed by T/2 from the fifth gate driving signal, the sixth gate driving signal is delayed by T/2 from the seventh gate driving signal, the eighth gate driving signal is delayed by T/2 from the sixth gate driving signal, the ninth gate driving signal is delayed by T/2 from the eighth gate driving signal, the eleventh gate driving signal is delayed by T/2 from the ninth gate driving signal, the tenth gate driving signal is delayed by T/2 from the eleventh gate driving signal, and the twelfth gate driving signal is delayed by T/2 from the tenth gate driving signal, t is the one-time opening duration time of the grid lines, and the one-time opening duration time of all the grid lines is the same;
the second gate driving signal is delayed by T/2 than the third gate driving signal, the sixth gate driving signal is delayed by T/2 than the seventh gate driving signal, and the tenth gate driving signal is delayed by T/2 than the eleventh gate driving signal;
the fifth gate driving signal is delayed by T/2 than the fourth gate driving signal, and the ninth gate driving signal is delayed by T/2 than the eighth gate driving signal;
the sixth gate driving signal is delayed by T/2 from the seventh gate driving signal and the tenth gate driving signal is delayed by T/2 from the eleventh gate driving signal.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display device, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A grid driving module is used for providing grid driving signals for a plurality of rows of grid lines of a display panel respectively, the display panel comprises a plurality of rows of sub-pixels, and the sub-pixels are electrically connected with the grid lines respectively; the grid driving module is characterized by comprising a grid driving circuit;
the grid driving circuit is used for respectively providing corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
2. The gate driving module of claim 1, wherein the gate driving circuit is configured to provide a 2a-1 gate driving signal to the gate line of row 2a-1 and a 2a gate driving signal to the gate line of row 2a, so as to control the gate line of row 2a-1 to be turned on before the gate line of row 2a, and control a time when the gate line of row 2a-1 is turned from an on state to an off state to correspond to a time when the gate line of row 2a is turned from an off state to an on state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
3. A gate driving method applied to the gate driving module as claimed in claim 1 or 2, wherein the gate driving method comprises:
the grid driving circuit provides corresponding grid driving signals for two rows of grid lines electrically connected with the same row of sub-pixels so as to control the two rows of grid lines to be opened in a time-sharing mode.
4. The gate driving method according to claim 3, wherein the gate driving method specifically comprises: the gate driving circuit provides a 2a-1 gate driving signal for a 2a-1 row of gate lines, and provides a 2a gate driving signal for a 2a row of gate lines, so as to control the 2a-1 row of gate lines to be opened before the 2a row of gate lines, and control the time when the 2a-1 row of gate lines is switched from an open state to a closed state to correspond to the time when the 2a row of gate lines is switched from a closed state to an open state;
a is a positive integer; the 2a-1 th row of grid lines is one row of grid lines electrically connected with the a th row of sub-pixels, and the 2a th row of grid lines is the other row of grid lines electrically connected with the a th row of sub-pixels.
5. A display device comprising a display panel and the gate driving module of claim 1 or 2;
the display panel comprises a plurality of rows of grid lines and a plurality of rows of sub-pixels, and the sub-pixels in one row are electrically connected with the grid lines in two rows respectively.
6. The display device of claim 5, wherein the odd column subpixels of row 2n-1 are electrically connected to the gate line of row 2n-1, and the even column subpixels of row 2n-1 are electrically connected to the gate line of row 2 n;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing mutually opposite grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
7. The display device of claim 5, wherein the odd column subpixels of row 2n-1 are electrically connected to the gate line of row 2n-1, and the even column subpixels of row 2n-1 are electrically connected to the gate line of row 2 n;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for providing grid driving signals for the 2n-1 th grid line and the 2n th grid line respectively so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and is used for providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line respectively so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
8. The display device of claim 5, wherein the even column subpixels of row 2n-1 are electrically connected to the gate line of row 2n-1, and the odd column subpixels of row 2n-1 are electrically connected to the gate line of row 2 n;
the 2n row even-numbered column sub-pixels are electrically connected with the 2n +1 row grid lines, and the 2n row odd-numbered column sub-pixels are electrically connected with the 2n +2 row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
9. The display device of claim 5, wherein the even column subpixels of row 2n-1 are electrically connected to the gate line of row 2n-1, and the odd column subpixels of row 2n-1 are electrically connected to the gate line of row 2 n;
the 2 nth row odd-numbered column sub-pixels are electrically connected with the 2n +1 th row grid lines, and the 2 nth row even-numbered column sub-pixels are electrically connected with the 2n +2 th row grid lines; n is a positive integer;
the grid driving module comprises a grid driving circuit;
the grid driving circuit is used for respectively providing grid driving signals for the 2n-1 th grid line and the 2n th grid line so as to control the 2n-1 th grid line and the 2n th grid line to be opened in a time-sharing mode, and respectively providing grid driving signals for the 2n +1 th grid line and the 2n +2 th grid line so as to control the 2n +1 th grid line and the 2n +2 th grid line to be opened in a time-sharing mode.
10. The display device according to any one of claims 6 to 9, wherein the gate driving circuit is further configured to control the 2n +1 th gate driving signal to be delayed by T/2 from the 2n-1 th gate driving signal, and to control the 2n +2 th gate driving signal to be delayed by T/2 from the 2n gate driving signal, and further configured to control the 4m-2 th gate driving signal to be delayed by T/2 from the 4m-1 th gate driving signal; the controller is also used for controlling the delay of the 4m +1 th grid driving signal to be T/2 than the 4m grid driving signal and controlling the delay of the 4m +2 th grid driving signal to be T/2 than the 4m +3 th grid driving signal; m is a positive integer;
t is the time for which the grid line is opened for one time;
the 2n +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +1 th row of gate lines, the 2n-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n-1 th row of gate lines, the 2n +2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n +2 th row of gate lines, the 2n th gate driving signal is a gate driving signal provided by the gate driving circuit to the 2n th row of gate lines, the 4m-2 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-2 th row of gate lines, the 4m-1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m-1 th row of gate lines, and the 4m +1 th gate driving signal is a gate driving signal provided by the gate driving circuit to the 4m +1 th row of gate lines, the 4 m-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4 m-th row, the 4m + 2-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 2-th row, and the 4m + 3-th gate driving signal is a gate driving signal provided by the gate driving circuit to the gate line of the 4m + 3-th row.
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Application publication date: 20200417 |
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