CN109785812B - Display panel driving method, display device, and storage medium - Google Patents
Display panel driving method, display device, and storage medium Download PDFInfo
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- CN109785812B CN109785812B CN201910098357.0A CN201910098357A CN109785812B CN 109785812 B CN109785812 B CN 109785812B CN 201910098357 A CN201910098357 A CN 201910098357A CN 109785812 B CN109785812 B CN 109785812B
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Abstract
The invention discloses a driving method of a display panel, display equipment and a storage medium, wherein gate switches of odd-numbered pixel units of a same row of pixel units and even-numbered pixel units of adjacent rows of pixel units share a first gate driving circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive line signal, and the adjacent sub-pixel units in the same row can form high-low equivalent voltage drive to achieve the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging, so that the problem of color cast of a visual angle is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, and the user experience is improved.
Description
Technical Field
The present invention relates to the field of liquid crystal displays, and in particular, to a driving method of a display panel, a display device, and a storage medium.
Background
Large-sized liquid crystal display panels mostly adopt a negative Vertical Alignment (VA) type or an in-plane switching (IPS) type. The VA liquid crystal technology has the advantages of higher production efficiency and lower manufacturing cost compared to the IPS liquid crystal technology, but has more obvious optical property defects compared to the IPS liquid crystal technology, for example, when a large-viewing-angle image is displayed, the VA liquid crystal display panel has color cast. When displaying an image, the luminance of the pixel should ideally change linearly with the voltage, so that the driving voltage of the pixel can accurately represent the gray scale of the pixel and be represented by the luminance. As shown in fig. 1a, when the VA mode liquid crystal technology is used, when the display surface is viewed with a small viewing angle (for example, front view), the brightness of the pixel can be in accordance with the ideal situation, i.e. it is linearly changed with the voltage, as shown by the ideal curve in fig. 1 a; however, when the display surface is viewed at a larger viewing angle (for example, over 160 degrees from the display surface), the brightness of the pixel exhibits a fast saturation with voltage and then a slow change due to the principle of the VA-mode liquid crystal technology, as shown in the actual curve of fig. 1 a. Thus, in a large viewing angle, the gray scale that the driving voltage should originally exhibit is greatly deviated, i.e., color shift occurs. The conventional way to improve color shift is to subdivide each sub-pixel into a main pixel and a sub-pixel, then drive the main pixel with a relatively high driving voltage and drive the sub-pixel with a relatively low driving voltage, and the main pixel and the sub-pixel together display one sub-pixel. And the relatively high driving voltage and the relatively low driving voltage can keep the relation between the brightness at the front viewing angle and the corresponding gray scale unchanged when the main pixel and the sub-pixel are driven. Generally, in the manner shown in fig. 1b, in the first half of the gray scale, the main pixel is driven to display by a relatively high driving voltage, the sub-pixel is not displayed, and the brightness of the whole sub-pixel is half of the brightness of the main pixel; in the second half of the gray scale, the main pixel is driven to display by a relatively high driving voltage, the sub-pixel is driven to display by a relatively low driving voltage, and the brightness of the whole sub-pixel is half of the sum of the brightness of the main pixel and the brightness of the sub-pixel. Thus, the luminance curve at large viewing angle is similar to the actual curve in fig. 1b, and the color shift is improved at large viewing angle.
However, the above method has a problem that new metal lines and Thin Film Transistors (TFTs) are required to be added to drive the sub-pixels, which results in the sacrifice of the light-permeable opening area, the influence on the light transmittance of the panel, and the direct increase of the backlight cost.
Disclosure of Invention
The invention mainly aims to provide a driving method of a display panel, display equipment and a storage medium, and aims to solve the problems that a light-permeable opening area is sacrificed, the light transmittance of the panel is influenced, and the backlight cost is higher in the prior art.
In order to achieve the above object, the present invention provides a driving method of a display panel, including:
the display panel comprises a display array, the display array comprises pixel units which are arranged in an array mode, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel in the row direction, and the three sub-pixels of each pixel unit are aligned in the column direction according to the arrangement sequence; the driving method includes:
the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share a first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal;
and taking the first gate driving circuit signal as a main gate driving signal, taking the second gate driving circuit signal as a secondary gate driving signal, controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the secondary gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a secondary gate driving time sequence, wherein the main gate driving time sequence is a time sequence of sequentially driving the original row gate, and the secondary gate driving time sequence is a gate driving time sequence corresponding to the previous adjacent high-voltage sub-pixel.
Optionally, the controlling the charging amount of each sub-pixel by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing and controlling the sub-gate driving signal in combination with the data driving signal in the sub-gate driving timing to control the charging amount of each sub-pixel in combination with the data driving signal in the sub-gate driving timing, with the first gate driving line signal as the main gate driving signal and the second gate driving line signal as the sub-gate driving signal, specifically includes:
using the first gate driving line signal as a main gate driving signal and the second gate driving line signal as a sub gate driving signal;
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
when receiving a data driving signal input by a data driving circuit and carrying out time sequence inversion, periodically inverting the first gate driving circuit signal and the second gate driving circuit signal;
and when the current time sequence is a second preset time sequence, driving the high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to the first gate drive line signal, and driving the low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to the second gate drive line signal.
Optionally, before the using the first gate driving line signal as a main gate driving signal, using the second gate driving line signal as a sub gate driving signal, and controlling the charge amount of each sub-pixel by controlling the main gate driving signal in combination with a data driving signal in a main gate driving timing, and controlling the charge amount of each sub-pixel by controlling the sub gate driving signal in combination with the data driving signal in a sub gate driving timing, the driving method of the display panel further includes:
selecting any two adjacent pixel units in the row direction, and acquiring the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit;
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal;
and when the voltage state of the first adjacent sub-pixel unit is low voltage and the voltage state of the second adjacent sub-pixel unit is high voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal.
Optionally, after selecting any two adjacent pixel units in the column direction and obtaining the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit, the driving method of the display panel further includes:
and when the preset voltage meets a preset condition, driving the equivalent driving voltage of the high-voltage sub-pixel and the low-voltage sub-pixel in the selected sub-pixels by adopting a preset data driving signal, wherein the preset data driving signal is an average signal of the driving signals of two adjacent sub-pixels in the original same column.
Optionally, after the first gate driving line signal is used as a main gate driving signal, the second gate driving line signal is used as a sub gate driving signal, the charging amount of each sub-pixel is controlled by controlling the main gate driving signal in combination with a data driving signal in a main gate driving timing, and the charging amount of each sub-pixel is controlled by controlling the sub gate driving signal in combination with the data driving signal in a sub gate driving timing, the driving method of the display panel further includes:
two adjacent sub-pixels in the same row are respectively selected, and the equivalent driving voltage of the high-voltage sub-pixel in the selected sub-pixels is driven by the equivalent driving voltage which is larger than that of the low-voltage sub-pixel in the selected sub-pixels.
Optionally, after the first gate driving line signal is used as a main gate driving signal and the second gate driving line signal is used as a sub gate driving signal, the driving method further includes:
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
optionally, after selecting any two adjacent pixel units in the column direction and obtaining the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit, the driving method of the display panel further includes:
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, driving a first sub-pixel and a third sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a first sub-pixel and a third sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal;
when the voltage state of the first adjacent sub-pixel unit is low voltage, and the voltage state of the second adjacent sub-pixel unit is high voltage, driving the second sub-pixel in the first adjacent sub-pixel unit by using a negative polarity driving signal, driving the first sub-pixel and the third sub-pixel in the first adjacent sub-pixel unit by using a positive polarity driving signal, driving the second sub-pixel in the second adjacent sub-pixel unit by using a positive polarity driving signal, and driving the first sub-pixel and the third sub-pixel in the second adjacent sub-pixel unit by using a negative polarity driving signal.
Further, to achieve the above object, the present invention also proposes a display device characterized by comprising: the display panel comprises a display array, the display array comprises pixel units which are arranged in an array, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel in the row direction, and the three sub-pixels of each pixel unit are aligned in the column direction according to the arrangement sequence; the driver of the display panel is configured to implement the steps of the driving method of the display panel as described above.
In addition, in order to achieve the above object, the present invention further provides a computer-readable storage medium, wherein a driver of a display panel is stored on the computer-readable storage medium, and the driver of the display panel, when executed by a processor, implements the steps of the driving method of the display panel as described above.
The invention provides a driving method of a display panel, which shares a first gate driving circuit signal by gate switches of odd-numbered rows of pixel units of the same row of pixel units and even-numbered rows of pixel units of adjacent rows of pixel units; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal; the first gate drive circuit signal is used as a main gate drive signal, the second gate drive circuit signal is used as a secondary gate drive signal, the main gate drive signal is controlled in a main gate drive time sequence to be combined with a data drive signal to control the charging amount of each sub-pixel, the secondary gate drive signal is controlled in a secondary gate drive time sequence to be combined with the data drive signal to control the charging amount of each sub-pixel, adjacent sub-pixel units in the same row can form high-low equivalent voltage drive, the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging is achieved, further, the visual angle color cast is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, and the user experience is improved.
Drawings
FIG. 1a is a graph showing the relationship between an improved front color shift curve and an ideal curve;
FIG. 1b is a graph showing the relationship between the improved color shift curve and the ideal curve;
fig. 2 is a schematic structural diagram of a display device of a hardware operating environment according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a driving method of a display panel according to a first embodiment of the present invention;
FIG. 4 is a schematic diagram of a pixel driving arrangement of a driving method of a display panel according to the present invention;
FIG. 5 is a schematic diagram of a first predetermined timing sequence of pixel driving according to the driving method of the display panel of the present invention;
FIG. 6 is a diagram illustrating a second predetermined timing of pixel driving according to the driving method of the display panel of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The solution of the embodiment of the invention is mainly as follows: sharing a first gate drive circuit signal by gate switches of odd-numbered rows of pixel units of the same row of pixel units and even-numbered rows of pixel units of adjacent rows of pixel units; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal; the first gate drive circuit signal is used as a main gate drive signal, the second gate drive circuit signal is used as a secondary gate drive signal, the main gate drive signal is controlled in a main gate drive time sequence to be combined with a data drive signal to control the charging amount of each sub-pixel, the secondary gate drive signal is controlled in a secondary gate drive time sequence to be combined with the data drive signal to control the charging amount of each sub-pixel, adjacent sub-pixel units in the same row can form high-low equivalent voltage drive to achieve the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging, further the visual angle color cast is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, the user experience is improved, the problem that the light transmittance of a panel is influenced by sacrificing a light-permeable opening area in the prior art is solved, the cost of the backlight is also higher.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a display device in a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 2, the display apparatus may include: the processor 1001 includes, for example, a CPU, a communication bus 1002, a user interface 1003, a display panel 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The memory 1005 may be a high-speed RAM memory or a non-volatile memory (non-memory) such as a disk memory. The memory 1005 may also be a storage device independent of the processor 1001, and the display panel 1004 may be a liquid crystal display panel, or other display panels capable of implementing the same or similar functions.
Those skilled in the art will appreciate that the display device configuration shown in fig. 2 does not constitute a limitation of the display device and may include more or fewer components than shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 2, a memory 1005, which is a kind of computer storage medium, may include a driver of the display panel therein.
The processor 1001 and the memory 1005 in the display device of the present invention may be provided in a display device which calls a driver of a display panel stored in the memory 1005 through the processor 1001 and performs the following operations:
the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share a first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal;
and taking the first gate driving circuit signal as a main gate driving signal, taking the second gate driving circuit signal as a secondary gate driving signal, controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the secondary gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a secondary gate driving time sequence, wherein the main gate driving time sequence is a time sequence of sequentially driving the original row gate, and the secondary gate driving time sequence is a gate driving time sequence corresponding to the previous adjacent high-voltage sub-pixel.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
using the first gate driving line signal as a main gate driving signal and the second gate driving line signal as a sub gate driving signal;
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
when receiving a data driving signal input by a data driving circuit and carrying out time sequence inversion, periodically inverting the first gate driving circuit signal and the second gate driving circuit signal;
and when the current time sequence is a second preset time sequence, driving the high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to the first gate drive line signal, and driving the low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to the second gate drive line signal.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
selecting any two adjacent pixel units in the row direction, and acquiring the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit;
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal;
and when the voltage state of the first adjacent sub-pixel unit is low voltage and the voltage state of the second adjacent sub-pixel unit is high voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
and when the preset voltage meets a preset condition, driving the equivalent driving voltage of the high-voltage sub-pixel and the low-voltage sub-pixel in the selected sub-pixels by adopting a preset data driving signal, wherein the preset data driving signal is an average signal of the driving signals of two adjacent sub-pixels in the original same column.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
two adjacent sub-pixels in the same row are respectively selected, and the equivalent driving voltage of the high-voltage sub-pixel in the selected sub-pixels is driven by the equivalent driving voltage which is larger than that of the low-voltage sub-pixel in the selected sub-pixels.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; the charge control of each sub-pixel is performed by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing, and the charge control of each sub-pixel is performed by controlling the sub-gate driving signal in combination with the data driving signal in the first sub-gate driving timing and the second sub-gate driving timing, wherein the first sub-gate driving timing is less than the main gate driving timing and the second sub-gate driving timing.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, driving a first sub-pixel and a third sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a first sub-pixel and a third sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal;
when the voltage state of the first adjacent sub-pixel unit is low voltage, and the voltage state of the second adjacent sub-pixel unit is high voltage, driving the second sub-pixel in the first adjacent sub-pixel unit by using a negative polarity driving signal, driving the first sub-pixel and the third sub-pixel in the first adjacent sub-pixel unit by using a positive polarity driving signal, driving the second sub-pixel in the second adjacent sub-pixel unit by using a positive polarity driving signal, and driving the first sub-pixel and the third sub-pixel in the second adjacent sub-pixel unit by using a negative polarity driving signal.
In the embodiment, the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share the first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal; the first gate drive circuit signal is used as a main gate drive signal, the second gate drive circuit signal is used as a secondary gate drive signal, the main gate drive signal is controlled in a main gate drive time sequence to be combined with a data drive signal to control the charging amount of each sub-pixel, the secondary gate drive signal is controlled in a secondary gate drive time sequence to be combined with the data drive signal to control the charging amount of each sub-pixel, adjacent sub-pixel units in the same row can form high-low equivalent voltage drive, the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging is achieved, further, the visual angle color cast is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, and the user experience is improved.
Based on the above hardware structure, an embodiment of a driving method of a display panel according to the present invention is provided.
Referring to fig. 3, fig. 3 is a flowchart illustrating a driving method of a display panel according to a first embodiment of the present invention.
In a first embodiment, the driving method of the display panel includes the steps of:
step S10, the gate switches of the odd-numbered rows of pixel units in the same row and the even-numbered rows of pixel units in the adjacent row share the first gate driving line signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share the second gate drive line signal.
It should be noted that, in the pixel design of the liquid crystal display panel in this embodiment, a red sub-pixel, a green sub-pixel, and a blue sub-pixel are a pixel unit, that is, the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively corresponding to a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and the red sub-pixel, the green sub-pixel, and the blue sub-pixel are heteropolarity sub-pixels, and each pixel unit adopts a high-low voltage alternating driving arrangement mode to drive the gate switches of the odd-numbered pixel units of the same row of pixel units and the even-numbered pixel units of the adjacent row of pixel units according to the first gate driving signal; driving the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units according to the second gate driving signal; the polarity of the driving signal of the sub-pixel corresponding to the first gate scanning line is opposite to the polarity of the driving signal of the sub-pixel corresponding to the second gate scanning line, and in implementation, a white sub-pixel may be added, and four sub-pixels are used as a pixel unit and are alternately arranged according to high and low voltages, which is not limited in this embodiment.
Step S20, using the first gate driving circuit signal as a main gate driving signal, using the second gate driving circuit signal as a sub-gate driving signal, controlling the main gate driving signal in combination with a data driving signal to control the charging amount of each sub-pixel in a main gate driving timing, and controlling the sub-gate driving signal in combination with the data driving signal to control the charging amount of each sub-pixel in a sub-gate driving timing, wherein the main gate driving timing is a timing at which the previous row gate is sequentially driven, and the sub-gate driving timing is a gate driving timing corresponding to the previous adjacent high voltage sub-pixel.
It is understood that the main gate driving timing and the sub gate driving timing are preset timings, and generally, the charge amount of each sub pixel is controlled by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing, and the charge amount of each sub pixel is controlled by controlling the sub gate driving signal in combination with the data driving signal in the sub gate driving timing; the driving timing of the main gate driving signal is the timing of the sequential driving of the original column gate, the data signal corresponding to the main gate driving is the data driving signal corresponding to the sub-pixel, and the driving timing of the sub-gate is the same as the gate driving timing and the data driving timing corresponding to the previous adjacent high voltage sub-pixel. Firstly, using the sub-gate driving switch to apply a data driving signal of the previous high-voltage sub-pixel to the low-voltage sub-pixel, and then turning on the main gate driving switch to apply a corresponding driving signal of the sub-pixel to the low-voltage sub-pixel; the data polarity of the low voltage sub-pixel is opposite to the data driving polarity of the high voltage sub-pixel; the storage amount of the charge charges of the sub-pixels on the first and second gate drive circuits is different to the same drive voltage compared with the charge charges of the sub-pixels on the high-voltage sub-pixels, and the problem of color cast of the visual angle can be solved by the drive of the alternating arrangement of the high-voltage pixel units and the low-voltage pixel units.
Further, the step S20 specifically includes the following steps:
using the first gate driving line signal as a main gate driving signal and the second gate driving line signal as a sub gate driving signal;
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
when receiving a data driving signal input by a data driving circuit and carrying out time sequence inversion, periodically inverting the first gate driving circuit signal and the second gate driving circuit signal;
and when the current time sequence is a second preset time sequence, driving the high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to the first gate drive line signal, and driving the low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to the second gate drive line signal.
Referring to fig. 4 and 5, fig. 4 is a schematic diagram illustrating a pixel driving arrangement of a driving method of a display panel according to the present invention; FIG. 5 is a schematic diagram of a first predetermined timing sequence of pixel driving according to the driving method of the display panel of the present invention; the first preset time is Frame1, the second preset time is Frame2, the data charging signal is Vgd, the first gate driving signal is Vg1, and the second gate driving signal is Vg 2; vg1 is a common gate driving circuit and driving signal for a row of odd-numbered row unit pixels and an adjacent row of even-numbered row unit pixels; vg2 is the same Vg1, i.e. a common gate driving circuit and driving signal for a row of odd-numbered row unit pixels and an adjacent row of even-numbered row unit pixels, R represents a red sub-pixel, B represents a blue sub-pixel, G represents a green sub-pixel, and + represents that the polarity of the sub-pixel is positive, VL represents that the sub-pixel is a low voltage pixel, and VH represents that the sub-pixel is a high voltage pixel.
It should be understood that, referring to fig. 5, the sub-pixel positive polarity driving signals Vgd ═ VG1, VG2, vg3.. of the G rows, and the sub-pixel negative polarity driving signals Vgd ═ VG1 ', VG2 ', VG3 ' …. The data driving signals are sequentially sub-pixels VGd _1, VGd _2, VGd _3 …, the sub-pixel voltage driving signals are VG1, VG1 ', VG2, VG 2' …, the gate voltage sequentially turns on and charges the sub-pixels VGd _1, VGd _2, VGd _3 …, the gate voltage of the high-voltage sub-pixel VGd _1 is VG1, the gate voltage of the low-voltage sub-pixel VGd _2 is VG2 and VG2 ', the gate voltage of the high-voltage sub-pixel VGd _1 is VG1, wherein the gate voltage of the high-voltage sub-pixel VGd _1 is VG1 and the gate voltage of the low-voltage sub-pixel VGd _2 is VG 2' and is also simultaneously turned on; the gate voltages of the low-voltage sub-pixel VGd _2 are Vg2 and Vg 2' with different turn-on times, the gate voltage of the low-voltage sub-pixel VGd _2 is Vg2 with the turn-on time T2 being the same as the gate voltage Vg1 of the high-voltage sub-pixel VGd _1 with the turn-on time T1, i.e., T1 is T2, the gate turn-on time of T2 being different from T1 can be adjusted according to the amount of the charged charges stored in the device; when the gate precharge voltage of the low voltage sub-pixel VGd _2 is Vg2 'on, T2' is less than the gate voltage Vg1 on time T1 of the high voltage sub-pixel VGd _1 and the gate voltage of the low voltage sub-pixel VGd _2 is Vg2 on time T2, i.e., T2 '< T1 and T2' < T2.
It can be understood that, referring to fig. 5, in the frame G, the gate driving voltage of the high voltage sub-pixels VGd _1, VGd _3, VGd _5 corresponding to the green row sub-pixels (R red and B blue row sub-pixels are the same) is Vg1, and the gate driving voltage of the low voltage sub-pixels VGd _2, VGd _4, VGd _6 is Vg2, wherein the gate switching timing of Vg1 is T1 for the data driving signal charging time, and the gate switching timing of Vg2 is two periods, one period is corresponding to the gate voltage Vg1 period of the previous adjacent sub-pixel, the gate charging time of Vg2 ' is T2 ', wherein T2 ' is less than the charging period of T1 and T2. The other time period is that the charging time for the data driving signal is T2 and the gate switch timing of Vg1 is the same as the charging time for the data driving signal is T1, and the gate switch time of T2 not equal to T1 can be adjusted according to the charge storage amount of the device.
It can be understood that, referring to fig. 6, fig. 6 is a schematic diagram of a second preset timing diagram of the driving method of the display panel according to the present invention, where the positive polarity driving signals Vgd of the subpixels in the G row are VG1, VG2, and VG3.. the negative polarity driving signals Vgd of the subpixels are VG1 ', VG 2', and VG3 '…, the data driving signals are sequentially subpixels VGd _1, VGd _2, and VGd _3 …, the subpixel voltage driving signals are VG 1', VG1, VG2 ', and VG2.. the gate voltage sequentially turns on and charges the subpixels VGd _1, VGd _2, and VGd _3 …, the gate voltage of the low-voltage subpixel VGd _3 is VG1 and VG 1', and the gate voltage of the high-voltage subpixel VGd _2 is VG2. The gate voltages of the low voltage sub-pixel VGd _3 are Vg1 and Vg 1' with different turn-on times, the gate voltage of the low voltage sub-pixel VGd _3 is Vg1 turn-on time T2 and the gate voltage Vg2 turn-on time T1 of the high voltage sub-pixel VGd _2, i.e. T1 is T2, or the gate turn-on time of T2 not equal to T1 can be adjusted according to the amount of the charged charges stored in the device. When the gate voltage of the low voltage sub-pixel VGd _3 is Vg1 ' turned on, T2 ' is less than the gate voltage Vg2 turn-on time T1 of the high voltage sub-pixel VGd _2, i.e., T2 ' < T1. Wherein the gate voltage of the low voltage sub-pixel VGd _3 is Vg 1' turned on.
It should be appreciated that the high voltage sub-pixel VGd _2 is charged with the positive polarity data driving signal Vgd VG1 and VG2 gate switch timing T1 charges the high voltage sub-pixel VGd _ 2. The next adjacent low-voltage sub-pixel VGd _3 is charged in two periods, the first charging period is the same as the previous high-voltage sub-pixel VGd _2 charging gate turn-on timing T1, when the data driving signal is the high-voltage sub-pixel VGd _2 charged with the positive polarity data driving signal Vgd ═ VG1, the sub-pixel VGd _3 turns on the gate driving voltage VG1 'to precharge the sub-pixel VGd _3, the gate driving voltage VG 1' and the gate driving voltage VG2 corresponding to the high-voltage sub-pixel VGd _2 are turned on simultaneously to charge the sub-pixel VGd _2, and the sub-pixel VGd _3 is precharged, and the turn-on time T2 'of the gate driving voltage VG 1' is designed to be smaller than the gate driving voltages VG1, VG2 turn-on times T1 and T2. The second charging period is the negative polarity driving voltage Vgd VG 2' and the gate switch timing T2 of VG1 to charge the sub-pixel VGd _ 3. The charging voltage of the low-voltage sub-pixel VGd _3 during the first charging time is positive polarity voltage VG1, the charging time T2 'of the gate voltage Vg 1' is controlled to be less than the charging time T2 of the gate voltage Vg1, so that the equivalent positive polarity charging voltage VG1 "< VG for the equivalent low-voltage sub-pixel VGd _3, i.e., the equivalent charging voltage | VG 1" -Vcom | of the low-voltage sub-pixel VGd _3 is less than | VG1-Vcom |. The charging voltage of the low-voltage sub-pixel VGd _3 during the second charging time is the negative polarity voltage VG2 ', and the charging time T2 of the charging control gate voltage Vg1 during the second charging time is determined by precharging the positive polarity voltage VG ", so that the equivalent charging voltage of the low-voltage sub-pixel VGd _3 is smaller than | VG 2' -Vcom |, and the charging voltage of the low-voltage sub-pixel VGd _3 is ensured to be smaller than the sub-pixel VGd _4 high-voltage sub-pixel | VG2-Vcom |. The adjacent sub-pixel units in the same row can form high-low equivalent voltage driving to achieve the difference between the charging of the high-voltage sub-pixel and the charging of the low-voltage sub-pixel, thereby achieving the effect of improving color cast while the gate voltage of the high-voltage sub-pixel VGd _2 is Vg2.
Further, the step S20 is preceded by the following steps:
selecting any two adjacent pixel units in the row direction, and acquiring the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit;
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, driving a first sub-pixel and a third sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a first sub-pixel and a third sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal;
when the voltage state of the first adjacent sub-pixel unit is low voltage, and the voltage state of the second adjacent sub-pixel unit is high voltage, driving the second sub-pixel in the first adjacent sub-pixel unit by using a negative polarity driving signal, driving the first sub-pixel and the third sub-pixel in the first adjacent sub-pixel unit by using a positive polarity driving signal, driving the second sub-pixel in the second adjacent sub-pixel unit by using a positive polarity driving signal, and driving the first sub-pixel and the third sub-pixel in the second adjacent sub-pixel unit by using a negative polarity driving signal.
It can be understood that, referring to the pixel driving timing of fig. 5, Vcom is the original common electrode voltage; VGd _1 sub-pixel is high voltage positive polarity driving signal VG1, the sub-pixel corresponds to gate driving signal VG1, data charging signal VG 1; VGd _2 sub-pixel is low voltage negative polarity driving signal, the sub-pixel charge is divided into two timings, first one timing corresponds to the gate driving signal VG2 ', the data charge signal is the positive polarity charging voltage VG1 of the previous sub-pixel VGd _1, the sub-pixel is charged with positive polarity voltage in advance, the next timing corresponds to the gate driving signal VG2, the data charge signal is the negative polarity charging voltage VG1 ' of the low voltage sub-pixel VGd _2, wherein the polarity of VG1 ' is opposite to that of VG1, namely VG1 ' is smaller than the common electrode voltage Vcom, VG1 is larger than the common electrode voltage Vcom, and | VG1-Vcom | VG1 ' -Vcom |.
It should be understood that, by pre-positive charging, the target negative polarity charging signal VG1 'is changed to VG1 ", since the data charging signal is changed from positive polarity to negative polarity, the gate driving voltage VG 2' switch T2 'for positive polarity charging is controlled to be smaller than the gate driving voltage VG2 switch T2 for negative polarity charging, so that the final negative polarity charging signal VG 1" of the low-voltage sub-pixel is smaller than | VG 1' -Vcom | with respect to the common electrode voltage Vcom | VG1 "-Vcom | i.e. the low-voltage sub-pixel charging equivalent voltage | VG 1" -Vcom | is smaller than the high-voltage sub-pixel charging equivalent voltage | VG1-Vcom |. The adjacent sub-pixel units in the same row can form high-low equivalent voltage drive to achieve the difference between the charging of the high-voltage sub-pixel and the charging of the low-voltage sub-pixel, thereby achieving the effect of improving color cast.
Further, after selecting any two adjacent pixel units in the column direction and obtaining the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit, the driving method of the display panel further includes:
and when the preset voltage meets a preset condition, driving the equivalent driving voltage of the high-voltage sub-pixel and the low-voltage sub-pixel in the selected sub-pixels by adopting a preset data driving signal, wherein the preset data driving signal is an average signal of the driving signals of two adjacent sub-pixels in the original same column.
It is understood that the preset condition is a state when the preset voltage is driven, for example, when the preset voltage is a positive polarity driving voltage, the preset voltage may also be a negative polarity driving voltage, and when the data driving signal input by the data driving circuit is received to perform timing inversion, the polarities of the preset voltages are opposite.
It should be noted that, in fig. 6, the gate switch switches the data driving signal charging timing, that is, the gate switch timing Vg1 is switched for two periods, one period corresponds to the previous adjacent sub-pixel data driving signal period, and the gate precharge voltage time Vg1 ' is T2 ', where T2 ' is less than the charging period T1/T2. The other time interval is that the charging time for the data driving signal is T2 and the gate switch timing of Vg2 is the same as the charging time for the data driving signal is T1, and the gate switch time of T2 not equal to T1 can be adjusted according to the charge storage amount of the device. Therefore, different high-low voltage signal sub-pixels of different picture frame time sequences can be realized, the difference between the high-voltage sub-pixels and the low-voltage sub-pixels can not be obviously seen by naked eyes, and the defect of reduced resolution can not be caused. The equivalent voltages of the subpixels VGd _1 and VGd _2 in the G row are driven by a positive driving voltage Vgd (VG 1) and a negative driving voltage Vgd (VG 1 '), respectively, and the positive driving voltage VG1 and the negative driving voltage VG1 ' can be selected as an average signal of Gd1 and Gd2 signals (0-255 signals in the case of an 8-bit driving signal), i.e., G1 (Gd (1 + Gd 2)/2), and the positive driving voltage VG1 and the negative driving voltage VG1 ' corresponding to the G1 signals. VGd _3 and VGd _4 equivalent voltages are respectively driven by the positive polarity driving voltage Vgd (VG 2) and the negative polarity driving voltage Vgd (VG 2 '), which can be selected as the average signal of the original frame pixel signals Gd3 and Gd4 (0-255 signals in the case of an 8-bit driving signal), that is, G2 (Gd3+ Gd4)/2, and the positive polarity driving voltage VG2 and the negative polarity driving voltage VG 2' corresponding to the G2 signals.
Further, after the step S20, the method for driving a display panel further includes:
two adjacent sub-pixels in the same row are respectively selected, and the equivalent driving voltage of the high-voltage sub-pixel in the selected sub-pixels is driven by the equivalent driving voltage which is larger than that of the low-voltage sub-pixel in the selected sub-pixels.
It should be appreciated that the high voltage sub-pixel VGd _1 is charged with the positive polarity data driving signal Vgd VG1 and VG1 gate switch timing T1 charges the high voltage sub-pixel VGd _ 1. The next adjacent low-voltage sub-pixel VGd _2 is charged in two periods, the first charging period is the same as the previous high-voltage sub-pixel VGd _1 charging gate turn-on timing T1, when the data driving signal is the high-voltage sub-pixel VGd _1 charged with the positive polarity data driving signal Vgd ═ VG1, the sub-pixel VGd _2 turns on the gate driving voltage VG2 'to charge the sub-pixel VGd _2, the gate driving voltage VG 2' and the gate driving voltage VG1 corresponding to the high-voltage sub-pixel VGd _1 are simultaneously turned on to charge the sub-pixel VGd _1, and the sub-pixel VGd _2 is precharged, and the turn-on time T2 'of the gate driving voltage VG 2' is designed to be smaller than the gate driving voltage VG1/VG2 turn-on time T1/T2. The second charging period is the negative polarity driving voltage Vgd VG 1' and the gate switch timing T2 of VG2 to charge the sub-pixel VGd _ 2. The charging voltage of the low-voltage sub-pixel VGd _2 during the first charging time is positive polarity voltage VG1, the charging time T2 'of the gate voltage Vg 2' is controlled to be less than the charging time T2 of the gate voltage Vg2, so that the equivalent low-voltage sub-pixel VGd _2 is positive polarity charging voltage VG1 "< VG, i.e., the equivalent charging voltage | VG 1" -Vcom | of the low-voltage sub-pixel VGd _2 is less than | VG1-Vcom |. The charging voltage of the low-voltage sub-pixel VGd _2 during the second charging time is the negative polarity voltage VG1 ', and the charging time T2 of the charging control gate voltage Vg2 during the second charging time is determined by precharging the positive polarity voltage VG ", so that the equivalent charging voltage of the low-voltage sub-pixel VGd _2 is smaller than | VG 1' -Vcom |, and the charging voltage of the low-voltage sub-pixel VGd _2 is ensured to be smaller than the sub-pixel VGd _1 high-voltage sub-pixel | VG1-Vcom |. The adjacent sub-pixel units in the same row can form high-low equivalent voltage drive to achieve the difference between the charging of the high-voltage sub-pixel and the charging of the low-voltage sub-pixel, thereby achieving the effect of improving color cast.
In the embodiment, the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share the first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal; the first gate drive circuit signal is used as a main gate drive signal, the second gate drive circuit signal is used as a secondary gate drive signal, the main gate drive signal is controlled in a main gate drive time sequence to be combined with a data drive signal to control the charging amount of each sub-pixel, the secondary gate drive signal is controlled in a secondary gate drive time sequence to be combined with the data drive signal to control the charging amount of each sub-pixel, adjacent sub-pixel units in the same row can form high-low equivalent voltage drive, the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging is achieved, further, the visual angle color cast is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, and the user experience is improved.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, where a driver of a display panel is stored on the computer-readable storage medium, and when executed by a processor, the driver of the display panel implements the following operations:
the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share a first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal;
and taking the first gate driving circuit signal as a main gate driving signal, taking the second gate driving circuit signal as a secondary gate driving signal, controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the secondary gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a secondary gate driving time sequence, wherein the main gate driving time sequence is a time sequence of sequentially driving the original row gate, and the secondary gate driving time sequence is a gate driving time sequence corresponding to the previous adjacent high-voltage sub-pixel.
Further, the driver of the display panel when executed by the processor further implements the following operations:
using the first gate driving line signal as a main gate driving signal and the second gate driving line signal as a sub gate driving signal;
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
when receiving a data driving signal input by a data driving circuit and carrying out time sequence inversion, periodically inverting the first gate driving circuit signal and the second gate driving circuit signal;
and when the current time sequence is a second preset time sequence, driving the high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to the first gate drive line signal, and driving the low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to the second gate drive line signal.
Further, the driver of the display panel when executed by the processor further implements the following operations:
and when the preset voltage meets a preset condition, driving the equivalent driving voltage of the high-voltage sub-pixel and the low-voltage sub-pixel in the selected sub-pixels by adopting a preset data driving signal, wherein the preset data driving signal is an average signal of the driving signals of two adjacent sub-pixels in the original same column.
Further, the driver of the display panel when executed by the processor further implements the following operations:
two adjacent sub-pixels in the same row are respectively selected, and the equivalent driving voltage of the high-voltage sub-pixel in the selected sub-pixels is driven by the equivalent driving voltage which is larger than that of the low-voltage sub-pixel in the selected sub-pixels.
Further, the processor 1001 may call a driver of the display panel stored in the memory 1005, and also perform the following operations:
selecting any two adjacent pixel units in the row direction, and acquiring the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit;
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, driving a first sub-pixel and a third sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a first sub-pixel and a third sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal;
when the voltage state of the first adjacent sub-pixel unit is low voltage, and the voltage state of the second adjacent sub-pixel unit is high voltage, driving the second sub-pixel in the first adjacent sub-pixel unit by using a negative polarity driving signal, driving the first sub-pixel and the third sub-pixel in the first adjacent sub-pixel unit by using a positive polarity driving signal, driving the second sub-pixel in the second adjacent sub-pixel unit by using a positive polarity driving signal, and driving the first sub-pixel and the third sub-pixel in the second adjacent sub-pixel unit by using a negative polarity driving signal.
In the embodiment, the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share the first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal; the first gate drive circuit signal is used as a main gate drive signal, the second gate drive circuit signal is used as a secondary gate drive signal, the main gate drive signal is controlled in a main gate drive time sequence to be combined with a data drive signal to control the charging amount of each sub-pixel, the secondary gate drive signal is controlled in a secondary gate drive time sequence to be combined with the data drive signal to control the charging amount of each sub-pixel, adjacent sub-pixel units in the same row can form high-low equivalent voltage drive, the difference between high-voltage sub-pixel charging and low-voltage sub-pixel charging is achieved, further, the visual angle color cast is solved, the difference between the high-voltage sub-pixel and the low-voltage sub-pixel cannot be obviously distinguished by naked eyes, the defect of reduced resolution is avoided, and the user experience is improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a device, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. The driving method of the display panel is characterized in that the display panel comprises a display array, the display array comprises pixel units which are arranged in an array mode, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel in the row direction, three sub-pixels of each pixel unit are aligned in the column direction according to the arrangement sequence, and each pixel unit is arranged in a high-voltage and low-voltage alternating driving mode; the driving method includes:
the gate switches of the odd-numbered rows of pixel units in the same row of pixel units and the even-numbered rows of pixel units in the adjacent row of pixel units share a first gate drive circuit signal; the gate switches of the even-numbered pixel units of the same row of pixel units and the odd-numbered pixel units of the adjacent row of pixel units share a second gate drive circuit signal;
using the first gate driving line signal as a main gate driving signal and the second gate driving line signal as a sub gate driving signal;
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to the main gate driving signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to the secondary gate driving signal; controlling the main gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a main gate driving time sequence, and controlling the sub-gate driving signal and the data driving signal to control the charging amount of each sub-pixel in a first sub-gate driving time sequence and a second sub-gate driving time sequence, wherein the first sub-gate driving time sequence is smaller than the main gate driving time sequence and the second sub-gate driving time sequence;
when receiving a data driving signal input by a data driving circuit and carrying out time sequence inversion, periodically inverting the first gate driving circuit signal and the second gate driving circuit signal;
when the current time sequence is a second preset time sequence, driving the high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving the low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal;
the main gate driving time sequence is the time sequence of the original row gate driving in sequence, the sub-gate driving time sequence is divided into two time sequences, one time sequence is the gate driving time sequence corresponding to the previous adjacent high-voltage sub-pixel, and the other time sequence is the time sequence of the original row gate driving in sequence.
2. The method of claim 1, wherein before the step of controlling the charge amount of each sub-pixel by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing and the step of controlling the charge amount of each sub-pixel by controlling the sub-gate driving signal in combination with the data driving signal in the sub-gate driving timing, the step of using the first gate driving line signal as the main gate driving signal and the second gate driving line signal as the sub-gate driving signal, the method further comprises:
selecting any two adjacent pixel units in the row direction, and acquiring the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit;
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal;
and when the voltage state of the first adjacent sub-pixel unit is low voltage and the voltage state of the second adjacent sub-pixel unit is high voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal.
3. The method for driving a display panel according to claim 2, wherein after selecting any two adjacent pixel units in the column direction and obtaining the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit, the method for driving a display panel further comprises:
and when the preset voltage meets a preset condition, driving the equivalent driving voltage of the high-voltage sub-pixel and the low-voltage sub-pixel in the selected sub-pixels by adopting a preset data driving signal, wherein the preset data driving signal is an average signal of the driving signals of two adjacent sub-pixels in the original same column.
4. The method for driving a display panel according to any one of claims 1 to 3, wherein the method for driving a display panel, after controlling the charge amount of each sub-pixel by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing and controlling the charge amount of each sub-pixel by controlling the sub-gate driving signal in combination with the data driving signal in the sub-gate driving timing, using the first gate driving line signal as the main gate driving signal and the second gate driving line signal as the sub-gate driving signal, further comprises:
two adjacent sub-pixels in the same row are respectively selected, and the equivalent driving voltage of the high-voltage sub-pixel in the selected sub-pixels is driven by the equivalent driving voltage which is larger than that of the low-voltage sub-pixel in the selected sub-pixels.
5. The method for driving a display panel according to claim 3, wherein after the first gate driving line signal is used as a main gate driving signal and the second gate driving line signal is used as a sub gate driving signal, the method further comprises:
when the current time sequence is a first preset time sequence, driving high-voltage sub-pixels in each row of pixel units by adopting a first preset voltage corresponding to a first gate drive line signal, and driving low-voltage sub-pixels in each row of pixel units by adopting a second preset voltage corresponding to a second gate drive line signal; the charge control of each sub-pixel is performed by controlling the main gate driving signal in combination with the data driving signal in the main gate driving timing, and the charge control of each sub-pixel is performed by controlling the sub-gate driving signal in combination with the data driving signal in the first sub-gate driving timing and the second sub-gate driving timing, wherein the first sub-gate driving timing is less than the main gate driving timing and the second sub-gate driving timing.
6. The method for driving a display panel according to claim 5, wherein after selecting any two adjacent pixel units in the column direction and obtaining the voltage states of the first adjacent sub-pixel unit and the second adjacent sub-pixel unit, the method for driving a display panel further comprises:
when the voltage state of the first adjacent sub-pixel unit is high voltage and the voltage state of the second adjacent sub-pixel unit is low voltage, driving a second sub-pixel in the first adjacent sub-pixel unit by adopting a positive polarity driving signal, driving a first sub-pixel and a third sub-pixel in the first adjacent sub-pixel unit by adopting a negative polarity driving signal, driving a second sub-pixel in the second adjacent sub-pixel unit by adopting a negative polarity driving signal, and driving a first sub-pixel and a third sub-pixel in the second adjacent sub-pixel unit by adopting a positive polarity driving signal;
when the voltage state of the first adjacent sub-pixel unit is low voltage, and the voltage state of the second adjacent sub-pixel unit is high voltage, driving the second sub-pixel in the first adjacent sub-pixel unit by using a negative polarity driving signal, driving the first sub-pixel and the third sub-pixel in the first adjacent sub-pixel unit by using a positive polarity driving signal, driving the second sub-pixel in the second adjacent sub-pixel unit by using a positive polarity driving signal, and driving the first sub-pixel and the third sub-pixel in the second adjacent sub-pixel unit by using a negative polarity driving signal.
7. A display device, characterized in that the display device comprises: the display panel comprises a display array, the display array comprises pixel units which are arranged in an array, each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel in the row direction, and the three sub-pixels of each pixel unit are aligned in the column direction according to the arrangement sequence; the driver of the display panel is configured to implement the steps of the driving method of the display panel according to any one of claims 1 to 6.
8. A storage medium having a driver of a display panel stored thereon, the driver of the display panel implementing the steps of the driving method of the display panel according to any one of claims 1 to 6 when executed by a processor.
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| KR20080044397A (en) * | 2006-11-16 | 2008-05-21 | 엘지디스플레이 주식회사 | A liquid crystal display device |
| CN107741660A (en) * | 2017-11-30 | 2018-02-27 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving framework, display panel and display device |
| CN108831405A (en) * | 2018-09-13 | 2018-11-16 | 重庆惠科金渝光电科技有限公司 | Driving method, device, equipment and the storage medium of display panel |
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| KR20080044397A (en) * | 2006-11-16 | 2008-05-21 | 엘지디스플레이 주식회사 | A liquid crystal display device |
| CN107741660A (en) * | 2017-11-30 | 2018-02-27 | 深圳市华星光电半导体显示技术有限公司 | Pixel driving framework, display panel and display device |
| CN108831405A (en) * | 2018-09-13 | 2018-11-16 | 重庆惠科金渝光电科技有限公司 | Driving method, device, equipment and the storage medium of display panel |
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