KR20120033689A - Array substrate for liquid crystal display device and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate for a liquid crystal display device and a manufacturing method thereof are provided to form a dual shorting bar of first and second shorting bars by interposing an insulating layer and connect a lower part of a panel part of a unit panel and a DIC pad part with the first and second shorting bars. CONSTITUTION: First and second shorting bars(120,122) are separated by interposing an insulating layer. A plurality of second pads are formed on an FPC(Flexible Printed Circuit) pad part of a non display area. The second pads are connected to the second shorting bar and first pads connected to the first shorting bar. A plurality of fourth pads are formed in a DIC(Driving Integrated Circuit) pad part of the non display area. A lower part of a panel part is connected to the first pads.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device including a dual shorting bar for preventing electrostatic defects and a manufacturing method thereof.

In general, the liquid crystal display device is driven by using the optical anisotropy and polarization properties of the liquid crystal, the liquid crystal molecules are oriented in the arrangement because the structure is thin and long, and artificially applies the electric field to the liquid crystal to control the direction of the molecular arrangement can do.

That is, when the arrangement of the liquid crystal molecules is changed using an electric field, light may be refracted in the arrangement direction of the liquid crystal molecules due to optical anisotropy of the liquid crystal, thereby displaying an image.

Such a liquid crystal display includes a TFT process of forming a gate wiring, a data wiring, a thin film transistor (TFT) and a pixel electrode on an array substrate, and forming a black matrix, a color filter, and a common electrode on a color filter substrate; A cell process of joining an array substrate and a color filter substrate, cutting them into cells, and injecting liquid crystal between the array substrate and the color filter substrate in a cell unit to form a unit panel, and driving a driving integrated circuit in the unit panel. It is completed through a module process of attaching an IC and a printed circuit board (PCB) and assembling with a backlight unit.

Here, a plurality of array substrates constituting the liquid crystal display device may be formed on a large mother substrate, also called a mother substrate or an array mother substrate, and a plurality of array substrates formed on the mother substrate are a plurality of cells. Also called.

In the manufacturing process of such a mother substrate may generate static electricity, the generated static electricity may have a fatal adverse effect on the characteristics of the plurality of devices formed on the mother substrate.

For example, an insulating layer between two conductive wires electrically insulated from each other may be destroyed by static electricity, and the two conductive wires may be electrically shorted, thereby preventing the liquid crystal display device from operating normally.

In order to prevent device deterioration due to static electricity, a shorting bar is formed in the outer portion of the mother substrate and the non-display area of each cell, which will be described with reference to the accompanying drawings.

1 is a diagram illustrating a conventional mother substrate, and FIG. 2 is an enlarged view of the cell region of FIG. 1.

As shown in FIGS. 1 and 2, the mother substrate 10 includes a plurality of cell areas CA, each of which is an array of unit panels of a unit panel completed in a subsequent process. Corresponds to.

The size of each of the plurality of cell regions CA may be changed according to the size of the liquid crystal display. In FIG. 1, 32 cells are formed on one mother substrate 10.

In addition, a shorting bar 20 is formed on the mother substrate 10. For example, two shorting bars 20 electrically separated from the left side and the right side of the mother substrate 10 may be formed. The shorting bar 20 may include a plurality of horizontal parts formed for each row of the plurality of cell areas CA, and a border part connecting the plurality of horizontal parts and surrounding the edges of the entire cell areas CA.

Each of the cell areas CA includes a non-display area NDA and a display area DA. The non-display area NDA includes a flexible printed circuit (FPC) pad part 30 and a driving integrated circuit (DIC). The pad portion 40 is included, and the display area DA includes a panel load portion 50.

A plurality of first pads 32 are formed in the FPC pad unit 30, and a plurality of second pads 42 and a plurality of third pads 44 are formed in the DIC pad unit 40.

The plurality of first pads 32 of the FPC pad unit 30 are portions to which the flexible printed circuit (FPC) is attached in a subsequent module process. The plurality of first pads 32 may include a plurality of first link wirings 25. It is electrically connected to the shorting bar 20 through the).

Some of the plurality of first pads 32 are electrically connected to the panel load portion 50 of the display area DA through the plurality of second link wires 35, and the plurality of first pads 32 are remaining. ) Is electrically connected to the plurality of second pads 42 of the DIC pad unit 40 through the plurality of third link wires 37.

The plurality of second pads 42 and the plurality of third pads 44 of the DIC pad unit 40 are portions to which a driving integrated circuit is attached in a subsequent module process, in particular, a drive integrated circuit on an array substrate. May be a chip on glass (COG) type liquid crystal display device directly connected thereto.

The plurality of third pads 44 may be connected to the panel load portion 50 of the display area DA through the plurality of third link wires 45.

Although not shown, the panel load unit 50 may include electrical elements such as a plurality of gate lines, a plurality of data lines, and a plurality of thin film transistors formed in the display area DA.

Here, since the shorting bar 20 is formed with a much larger width than other wirings, the shorting bar 20 may serve as a reservoir for charge, and the stage where the mother substrate 10 is placed in the TFT process is mostly grounded. The charge accumulated in the putting bar 20 may be discharged through the stage.

Accordingly, while the electrical element is formed on the mother substrate 10 through the TFT process, the generated static electricity is discharged to the shorting bar 20, thereby protecting the electrical element of the mother substrate 10 from static electricity.

That is, the static electricity generated in the panel load part 50 may be discharged to the shorting bar 20 through the plurality of second link wires 35, the plurality of first pads 32, and the plurality of first link wires 25. The static electricity generated in the plurality of second pads 42 of the DIC pad unit 40 may include a plurality of third link wires 37, a plurality of first pads 32, and a plurality of first link wires 25. Through the shorting bar 20 can be discharged through.

However, the plurality of second pads 42 and the plurality of first pads 32 connected to the DIC pad unit 40 are electrically connected to other parts such as the panel load unit 50 except for the shorting bar 20. Since the power signal is mainly applied to the floating portion instead of being connected to the floating portion, the conductive layer is formed to have a relatively large area for low resistance.

Accordingly, the probability of generating static electricity in the plurality of second pads 42 of the DIC pad part 40 is relatively high, and the static electricity generated in the plurality of second pads 42 of the DIC pad part 40 is shorted. It is preferable to be discharged to an extinction), but rather it is accumulated in the shorting bar 20, and the plurality of first link wires 25, the plurality of first pads 32, and the plurality of second link wires 35 are close to each other. A problem occurs that flows into the display area DA and causes a failure of an electrical element of the panel load part 50.

According to the present invention, by forming the first and second shorting bars electrically insulated from each other on the mother substrate and connecting the panel load portion and the DIC pad portion of the unit panel to the first and second shorting bars, respectively, SUMMARY OF THE INVENTION An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can prevent a defect of an electrical element of a panel load.

In addition, the present invention is formed in the TFT process and the cell process by forming the first and second shorting bars electrically insulated from the mother substrate and connecting the panel load portion and the DIC pad portion of the unit panel to the first and second shorting bars, respectively. Another object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which can prevent a defect of an electric element of a panel load part and a DIC pad part caused by static electricity.

In order to achieve the above object, the present invention includes a substrate comprising a plurality of cell areas each consisting of a non-display area and a display area; First and second shorting bars formed in the non-display area and spaced apart from each other via an insulating layer; A plurality of first pads formed in the FPC pad portion of the non-display area and connected to the first shorting bar and a plurality of second pads connected to the second shorting bar; A plurality of third pads formed in the DIC pad portion of the non-display area and electrically connected to the plurality of third pads and the plurality of third pads; An array substrate for a liquid crystal display device is formed in the display area and includes a panel load portion connected to the plurality of first pads.

In this case, the first and second shorting bars are respectively formed in each row of the plurality of cell regions, and are connected to the first and second edge portions surrounding the edges of the entire plurality of cell regions, respectively, and electrically connected to each other. It can be insulated.

The first and second shorting bars may be formed of the same layer and the same material to be spaced apart from each other in a plane, or may be formed of different layers and different materials to be spaced apart from each other and to overlap each other in a plane. .

Alternatively, the first and second shorting bars may be formed for each row of the plurality of cell regions, and may be electrically connected to each other by being connected to an edge portion surrounding the edges of the entire plurality of cell regions.

The plurality of first pads and the plurality of second pads may be pads for a flexible printed circuit (FPC), and the plurality of third pads and the plurality of fourth pads may be pads for a driving integrated circuit (DIC). have.

The array substrate for a liquid crystal display device may include a plurality of first link wires connecting the first shorting bar and the plurality of first pads; A plurality of second link wires connecting the second shorting bar and the plurality of second pads; A plurality of third link wires connecting the plurality of first pads to the panel load; A plurality of fourth link wires connecting the plurality of second pads and the plurality of third pads; The apparatus may further include a plurality of fifth link wires connecting the plurality of fourth pads to the panel load part.

The panel load unit may include a gate wiring, a data wiring crossing the gate wiring to define a pixel region, a thin film transistor connected to the gate wiring and the data wiring, and a pixel electrode connected to the thin film transistor. .

On the other hand, the present invention comprises the steps of forming a first and a second shorting bar spaced apart from each other via an insulating layer in the non-display area above the substrate including a plurality of cell areas each consisting of a non-display area and a display area; ; Forming a plurality of first pads connected to the first shorting bar and a plurality of second pads connected to the second shorting bar, in the FPC pad portion of the non-display area; Forming a plurality of third pads connected to the plurality of second pads and a plurality of fourth pads electrically floating with the plurality of third pads in the DIC pad portion of the non-display area; A method of manufacturing an array substrate for a liquid crystal display device, the method comprising forming a panel load portion connected to the plurality of first pads in the display area.

The method of manufacturing an array substrate for a liquid crystal display device may include a plurality of first link wires connecting the first shorting bar and the plurality of first pads, and the second shorting bar and the plurality of second pads. A plurality of second link wires, a plurality of third link wires connecting the plurality of first pads and the panel load portion, and a plurality of fourth links connecting the plurality of second pads and the plurality of third pads The method may further include forming a plurality of fifth link wires connecting the plurality of fourth pads and the panel load unit.

On the other hand, the present invention comprises the steps of forming a first and second shorting bar spaced apart from each other via an insulating layer in a non-display area on the array mother substrate including a plurality of cell regions; Forming a plurality of first pads connected to the first shorting bar and a plurality of second pads connected to the second shorting bar, in the FPC pad portion of the non-display area; Forming a plurality of third pads connected to the plurality of second pads and a plurality of fourth pads electrically floating with the plurality of third pads in the DIC pad portion of the non-display area; Forming a panel load portion connected to the plurality of first pads in a display area above the array mother substrate; Forming a black matrix on the color filter mother substrate; Forming a color filter layer on the black matrix; Forming a common electrode on the color filter layer; Bonding the array mother substrate and the color filter mother substrate together; Cutting the bonded mother motherboard and the color filter mother substrate into the plurality of cell regions; Forming a unit panel by injecting liquid crystal between the bonded and cut array mother substrate and the color filter mother substrate; Attaching a flexible printed circuit to the plurality of first pads and the plurality of second pads of the unit panel, and attaching a driving integrated circuit to the plurality of third pads and the plurality of fourth pads. A method of manufacturing a display device is provided.

The cutting of the bonded array mother substrate and the color filter mother substrate in units of the plurality of cell regions may include removing the first and second shorting bars from the unit panel.

In a mother substrate for an array substrate for a liquid crystal display according to the present invention, a dual shorting bar of first and second shorting bars spaced apart from each other through an insulating layer is formed, and a panel load portion of a unit panel is provided. By connecting the DIC pad unit and the first and second shorting bars, respectively, the static electricity generated from the DIC pad unit can be prevented from directly flowing into the panel load unit, and the electrical components of the panel load unit can be prevented due to the static electricity generated from the DIC pad unit. Can be.

In addition, by connecting the panel load portion and the DIC pad portion of the unit panel to the first and second shorting bars, respectively, it is possible to prevent defects in the panel load portion and the DIC pad portion due to static electricity generated in the TFT process and the cell process. .

1 is a view showing a conventional mother substrate.
FIG. 2 is an enlarged view of the cell region of FIG. 1; FIG.
3 illustrates a mother substrate including an array substrate according to a first embodiment of the present invention.
4 is an enlarged view of the cell region of FIG. 3;
FIG. 5 is a circuit diagram of a portion of the display area of FIG. 4. FIG.
6 is a cross-sectional view of a portion of the display area of FIG. 4.
FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 4. FIG.
8 is a cross-sectional view taken along the line VIII-VIII of FIG. 4.
9 is a view showing a mother substrate including an array substrate according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a mother substrate including an array substrate according to a first embodiment of the present invention, and FIG. 4 is an enlarged view of the cell region of FIG. 3.

As shown in FIG. 3 and FIG. 4, the mother substrate 110 includes a plurality of cell areas CA, each of which is an array substrate of unit panels completed in a subsequent process. Corresponds to.

The size of each of the plurality of cell regions CA may be changed according to the size of the liquid crystal display. In FIG. 3, 32 cells are formed on one mother substrate 110.

The mother substrate 110 is provided with first and second shorting bars 120 and 122 spaced apart from each other through an insulating layer. For example, the mother substrate 110 is electrically separated from the left and right portions of the mother substrate 110. Two first shorting bars 120 may be formed, and each of the first shorting bars 120 may include an upper end of a horizontal row of a plurality of cell regions CA on each of a left side and a right side of the mother substrate 110. It may be formed in the lower non-display area NDA, and may be connected to the first edge portion 121 surrounding the edges of the entire cell area CA.

In addition, two second shorting bars 122 electrically separated from the left side and the right side of the mother substrate 110 may be formed, respectively, and the second shorting bar 122 may include the left side and the left side of the mother substrate 110. The second edge portion 123 may be formed in the non-display area NDA at the top or the bottom of the horizontal column of the plurality of cell areas CA, and surrounds the edges of the entire cell areas CA. It can be connected with.

Here, since the first and second edge portions 121 and 123 are electrically insulated from each other, the first and second shorting bars 120 and 122 connected to the first and second edge portions 121 and 123, respectively, Are electrically insulated from each other.

3 and 4, the second shorting bar 122 is formed below the first shorting bar 120 to be spaced apart from each other in planar manner, and the second edge part 123 of the first edge part 121 is formed. Although illustrated as being formed therein, in another embodiment, the second shorting bar 122 is formed on the first shorting bar 120 to be spaced apart from each other in planar manner, or the second shorting bar 122 is formed in the first shorting bar ( It may be formed so as to overlap the cross-sectional area 120 and spaced apart from each other, the second edge portion 123 may be formed on the outside of the first edge portion 121, or may overlap the first edge portion 121, In any of the embodiments, the first and second shorting bars 120 and 122 may be spaced apart from each other in plan or cross section through an insulating layer.

That is, the first and second shorting bars 120 and 122 may be formed of the same layer and the same material to be spaced apart from each other in a plane, or formed of different layers and different materials to overlap each other in a plane and to be spaced apart from each other in a cross-section. Can be formed.

The first and second shorting bars 120 and 122 are formed between the plurality of cell regions CA, and are removed by cutting in a subsequent cell process.

Each of the cell areas CA includes a non-display area NDA and a display area DA. The non-display area NDA includes a flexible printed circuit (FPC) pad unit 130 and a driving integrated circuit (DIC). The pad unit 140 is included, and the display area DA includes a panel load unit 150.

The display area DA may be an area where a liquid crystal layer is formed corresponding to the color filter substrate.

A plurality of first pads 132 and a plurality of second pads 134 are formed in the FPC pad unit 130, and a plurality of third pads 142 and a plurality of fourth pads (DIC pad unit 140). 144 is formed.

The plurality of first pads 132 and the plurality of second pads 134 of the FPC pad unit 130 are portions to which the flexible printed circuit (FPC) is attached in a subsequent module process, and the plurality of first pads 132. Is electrically connected to the first shorting bar 120 through the plurality of first link wires 125, and the plurality of second pads 134 are connected to the second shorting bar through the plurality of second link wires 127. And electrical connection with 122).

In addition, the plurality of first pads 132 are electrically connected to the panel load portion 150 of the display area DA through the plurality of third link wires 135, and the plurality of second pads 134 are provided in plurality. It is electrically connected to the plurality of third pads 142 of the DIC pad unit 140 through the fourth link wiring 137 of the.

The plurality of third pads 142 and the plurality of fourth pads 144 of the DIC pad unit 140 are portions to which a driving integrated circuit is attached in a subsequent module process, wherein the liquid crystal display is an array substrate. It may be a COG (chip on glass) type liquid crystal display device directly connected to the driving integrated circuit.

That is, the plurality of third pads 142 may be connected to an input lead of the driving integrated circuit, the plurality of fourth pads 144 may be connected to an output lead of the driving integrated circuit, and the driving integrated circuit may be attached. Previously, the plurality of third pads 142 and the plurality of fourth pads 144 may be in an electrically floating state (electrically open).

The plurality of fourth pads 144 may be connected to the panel load part 150 of the display area DA through the plurality of fifth link wires 145.

The panel load unit 150 may include electrical elements such as a plurality of gate lines, a plurality of data lines, and a plurality of thin film transistors formed in the display area DA.

Although not shown, in the unit panel completed through the TFT process and the cell process, the first and second shorting bars 120 and 122 may be removed so that the plurality of first pads 132 and the plurality of second pads 134 may be removed. The array panel may be electrically floating, and the unit panel may be attached to the flexible printed circuit and the driving integrated circuit through a module process, and the flexible printed circuit may be connected to an external circuit such as a timing controller.

The external circuit unit transmits a plurality of power signals, a plurality of control signals, and RGB data to the plurality of first pads 132 and the plurality of second pads 134 of the FPC pad unit 130 through a flexible printed circuit. Some of these signals are transmitted to the panel load unit 150 through the plurality of third link wires 135, and some of the signals are transmitted to the panel load unit 150 through the plurality of fourth link wires 137. The third pad 142 may be transmitted to the third pad 142 to be input to the driving integrated circuit.

The driving integrated circuit may generate a gate signal and a data signal using a plurality of control signals and RGB data, and supply the gate signal and the data signal to the gate wiring and the data wiring of the panel load unit 150, respectively.

Here, since the first and second shorting bars 120 and 122 and the first and second border portions 121 and 123 are formed to be significantly wider than other wirings such as gate wiring, data wiring, and link wiring, respectively, Since the stage where the mother substrate 110 is placed during the TFT process and the cell process is mostly grounded, charges accumulated in the first and second shorting bars 120 and 122 may be charged. It may be discharged through the stage.

Therefore, by discharging the static electricity generated from the mother substrate 110 to the first and second shorting bars 120 and 122 during the TFT process and the cell process, it is possible to protect the electrical element of the mother substrate 110 from static electricity.

In particular, the static electricity generated in the panel load unit 150 is transferred to the first shorting bar 120 through the plurality of third link wires 135, the plurality of first pads 132, and the plurality of first link wires 125. Discharged and extinguished, the static electricity generated in the plurality of third pad 142 of the DIC pad unit 140 is a plurality of fourth link wiring 137, a plurality of second pad 134 and a plurality of second links. The second shorting bar 122 may be discharged and dissipated through the wiring 127.

That is, the static electricity generated in the panel load unit 150 and the static electricity generated in the plurality of third pads 142 of the DIC pad unit 140 are spaced apart from each other through an insulating layer and electrically insulated from the first and second shorting bars. Each of the plurality of DIC pad portions 140, which are discharged to 120 and 122, has a high degree of integration of a conductive layer, a power signal is mainly applied, and is a portion that is floating without being electrically connected to the panel load portion 150. The static electricity generated from the third pad 142 and the plurality of second pads 134 connected thereto may be prevented from flowing back into the panel load unit 150, and as a result, the panel load unit 150 may not be electrically charged. The defect of an element can be prevented.

Specifically, in the conventional mother substrate including a single shorting bar, the device defect rate due to static electricity reached about 2% to about 7%, but in the mother substrate of the present invention including the first and second shorting bars, the device defect rate due to static electricity This improved to about 0.5% or less.

The structure of the first and second shorting bars 120 and 122 spaced apart from each other via the insulating layer will be described with reference to the drawings.

5 is a circuit diagram of a portion of the display area of FIG. 4, and FIG. 6 is a cross-sectional view of a portion of the display area of FIG. 4, which will be described with reference to FIGS. 3 and 4.

As shown in FIG. 5, the display area DA of the array substrate corresponding to the cell area CA includes a plurality of pixel areas P, and one pixel area P crosses the gate wiring ( GL) and data wiring (DL).

In the pixel region P, a thin film transistor T connected to the gate line GL and the data line DL, a liquid crystal capacitor Clc and a storage capacitor Cst connected to the thin film transistor T are formed.

The liquid crystal capacitor Clc includes a pixel electrode (174 of FIG. 6) and a common electrode (not shown) of the color filter substrate and the liquid crystal layer formed between the pixel electrode 174 and the common electrode facing each other. The transmittance of the liquid crystal layer is changed according to the data signal applied to the pixel electrode 174, thereby displaying an image.

The storage capacitor Cst keeps the data signal constant for one frame.

As illustrated in FIG. 6, a gate line GL and a gate electrode 160 are formed in the pixel area P of the display area DA on the mother substrate 110, and the gate line GL is formed. The gate insulating layer 162 is formed on the gate electrode 160.

The gate line GL is formed along one direction, and the gate electrode 160 is connected to the gate line GL.

The gate wiring GL and the gate electrode 160 may be made of a conductive metal material such as aluminum (Al), aluminum alloy, molybdenum (Mo), copper (Cu), tungsten (W), and the like, and the gate insulating layer 162. ) May be made of an inorganic insulating material or an organic insulating material.

The semiconductor layer 164 includes an active layer 164a acting as a channel and an ohmic contact layer 164b over the active layer 164a on the gate insulating layer 162 corresponding to the gate electrode 160. The active layer 164a and the ohmic contact layer 164 may be formed of intrinsic amorphous silicon and impurity-doped amorphous silicon, respectively.

In addition, source and drain electrodes 166 and 168 spaced apart from each other are formed on the ohmic contact layer 164b, and data wirings connected to the source electrode 166 on the gate insulating layer 162 (DL of FIG. 5). ) Is formed, and the data line DL intersects the gate line GL to define the pixel area P.

The gate electrode 160, the gate insulating layer 162, the semiconductor layer 164, the source electrode 166, and the drain electrode 168 constitute a thin film transistor T.

The data wiring DL, the source electrode 166 and the drain electrode 168 may be made of a conductive metal material such as aluminum (Al), aluminum alloy, molybdenum (Mo), copper (Cu), tungsten (W), or the like. .

A passivation layer 170 is formed on the data line DL and the thin film transistor T. The passivation layer 170 includes a drain contact hole 172 exposing the drain electrode 168 and includes an inorganic insulating material or It may be made of an organic insulating material.

The pixel electrode 174 is formed in the pixel region P on the passivation layer 170. The pixel electrode 174 is connected to the drain electrode 168 through the drain contact hole 172 and is indium-tin. -oxide) or indium-zinc-oxide (IZO).

FIG. 7 is a cross-sectional view taken along the cutting line VII-VII of FIG. 4, and FIG. 8 is a cross-sectional view taken along the cutting line VIII-VIII of FIG. 4, and will be described with reference to FIGS. 3 to 6.

As shown in FIGS. 7 and 8, a first shorting bar 120 and a plurality of first link wires 125 are formed between the plurality of cell regions CA on the mother substrate 110 and the mother substrate. A plurality of first pads 132, a plurality of third link wires 135, a plurality of fourth link wires 137, and a plurality of third pads 142 may be disposed in the non-display area NDA on the upper portion of the upper portion 100. Is formed.

The first shorting bar 120, the plurality of first link wires 125, the plurality of first pads 132, and the plurality of third link wires 135 are connected to each other, and the plurality of fourth link wires 137. And a plurality of third pads 142 are connected to each other, the first shorting bar 120, the plurality of first link wires 125, the plurality of first pads 132, and the plurality of third link wires 135. The plurality of fourth link lines 137 and the plurality of third pads 142 may be formed of the same layer and the same material as the gate line GL and the gate electrode 160.

The first shorting bar 120, the plurality of first link wires 125, the plurality of first pads 132, the plurality of third link wires 135, the plurality of fourth link wires 137, and the plurality of first link wires 125. The gate insulating layer 162 is formed on the third pad 142 of FIG.

A second shorting bar 122 is formed between the plurality of cell regions CA on the gate insulating layer 162, and a plurality of second link wirings is formed on the non-display area NDA on the gate insulating layer 162. 127 and a plurality of second pads 134 are formed.

The second shorting bar 122, the plurality of second link wirings 127, and the plurality of second pads 134 are connected to each other, and the data wiring DL, the source electrode 166, and the drain electrode 168 are connected to each other. The same layer may be made of the same material.

In addition, the plurality of second pads 134 may contact the plurality of fourth link wires 137 through contact holes formed in the gate insulating layer 162.

A protective layer 170 is formed on the second shorting bar 122, the plurality of second link wires 127, and the plurality of second pads 134.

The plurality of first pads 132 and the plurality of third pads 142 may be exposed through contact holes formed in the protective layer 170 and the gate insulating layer 162, and the plurality of second pads 134 may be exposed. It may be exposed through the contact hole formed in the protective layer 170.

A plurality of first pad terminals 132a, a plurality of second pad terminals 134a, and a plurality of third pad terminals 142a are formed on the passivation layer 170, and a plurality of first pad terminals 132a, The plurality of second pad terminals 134a and the plurality of third pad terminals 142a may be formed of the same layer and the same material as the pixel electrode 174, and may include a plurality of first pads 132 and a plurality of first pads. It serves to prevent and protect the corrosion of the second pad 134 and the plurality of third pads 142.

The plurality of first pad terminals 132a may contact the plurality of first pads 132 through contact holes, respectively, and the plurality of second pad terminals 134a may contact the plurality of second pads 134 through contact holes. ), And the plurality of third pad terminals 142a may contact the plurality of third pads 142 through contact holes, respectively.

Here, the second shorting bar 122 made of the same layer and the same material as the source electrode 166 and the drain electrode 168 may have the first shorting bar 120 made of the same layer and the same material as the gate electrode 160. And spaced apart from each other in a planar and cross-sectional area through the gate insulating layer 162 and are electrically insulated from each other, the second shorting bar may be generated from the plurality of third pads 142 and the plurality of second pads 134 connected thereto. The static electricity discharged to 122 is not transferred to the first shorting bar 120 and is prevented from flowing back into the panel load unit 150.

Therefore, it is possible to prevent defects of the electrical elements of the panel load unit 150 due to the static electricity of the electrically floating portions, such as the plurality of third pads 142 and the plurality of second pads 134.

7 and 8 illustrate that the first and second shorting bars 120 and 122 are spaced apart from each other without being overlapped in a planar manner, but the first and second shorting bars 120 and 122 may form the gate insulating layer 162. It may be disposed so as to overlap in the plane through the plane and to be spaced apart from each other in the cross section.

In another embodiment, the first shorting bar 120 may be formed of the same layer and the same material as the source electrode 166 and the drain electrode 168, and the second shorting bar 122 may be formed of the gate electrode 160. The same layer and the same material may be used. In another embodiment, the first and second shorting bars 120 and 122 may be the same as one of the gate electrode 160, the source electrode 166, and the drain electrode 168. Layer and the same material, and the first and second link wirings 125 and 127 are made of the same layer and the same material as the other one, and the first and second shorting bars 120 and 122 and the same material. The first and second link wires 125 and 127 may be connected through contact holes.

Meanwhile, in another embodiment, the first and second shorting bars may be connected to the same edge portion, which will be described with reference to the drawings.

9 is a diagram illustrating a mother substrate including an array substrate according to a second embodiment of the present invention, and descriptions of the same parts as those of the first embodiment are omitted.

As shown in FIG. 9, the mother substrate 210 includes a plurality of cell areas CA, each of which corresponds to an array substrate of a unit panel completed in a subsequent process. .

The size of each of the plurality of cell regions CA may be changed according to the size of the liquid crystal display. In FIG. 9, 32 cells are formed on one mother substrate 210.

The mother substrate 210 is provided with first and second shorting bars 220 and 222 spaced apart from each other via an insulating layer. For example, the mother substrate 210 is electrically separated from the left and right portions of the mother substrate 210. Two first shorting bars 220 may be formed, respectively, and the first shorting bars 220 may be formed at the upper end of the horizontal rows of the plurality of cell regions CA on the left side and the right side of the mother substrate 210, respectively. It may be formed in the lower non-display area NDA, and may be connected to the edge portion 221 surrounding the edges of the entire cell area CA.

In addition, two second shorting bars 222 electrically separated from the left side and the right side of the mother substrate 210 may be formed, respectively, and the second shorting bar 222 may include the left side and the left side of the mother substrate 210. Each of the right parts may be formed in the non-display area NDA at the top or the bottom of the horizontal column of the plurality of cell areas CA, and may be connected to the edge portion 221 surrounding the edges of the entire cell areas CA. Can be.

That is, the first and second shorting bars 120 and 122 are formed to be spaced apart from each other via an insulating layer in the non-display area NDA at the top or the bottom of the row of the plurality of cell areas CA. The edges of the entire cell area CA are connected to one edge 221 and electrically shorted with each other.

In FIG. 9, the second shorting bar 222 is formed below the first shorting bar 220 to be spaced apart from each other in plan view. In another embodiment, the second shorting bar 222 is the first shorting bar. The second shorting bar 222 overlaps with the first shorting bar 220 and may be formed to be spaced apart from each other in cross-section, and may be formed to be spaced apart from each other in plan view. It is the same that the shorting bars 220 and 222 are spaced apart from each other in plan or cross section through the insulating layer.

That is, the first and second shorting bars 220 and 222 may be formed of the same layer and the same material to be spaced apart from each other in a plane, or formed of different layers and different materials to overlap each other in a plane and to be spaced apart from each other in a cross-section. Can be formed.

The first and second shorting bars 220 and 222 are formed between the plurality of cell regions CA, and are removed by cutting in a subsequent cell process.

Here, since the first and second shorting bars 220 and 222 and the edge portion 221 are formed to be significantly wider than other wirings such as gate wiring, data wiring, and link wiring, respectively, the reservoir for charge Since the stage in which the mother substrate 210 is placed during the TFT process and the cell process is mostly grounded, charges accumulated in the first and second shorting bars 220 and 222 may be discharged through the stage. .

Therefore, by discharging the static electricity generated from the mother substrate 210 to the first and second shorting bars 220 and 222 during the TFT process and the cell process, the electrical element of the mother substrate 210 can be protected from static electricity.

In particular, the static electricity generated at the panel load portion 150 (FIG. 4) may be discharged and dissipated to the first shorting bar 220. Can be discharged and destroyed.

Of course, the first and second shorting bars 220 and 222 may be electrically connected to each other through the edge portion 221, but the insulating layer may be formed in the non-display area NDA at the top or bottom of each cell area CA. Since they are spaced apart from each other, the static electricity generated in the DIC pad part 140 in FIG. 4 in each cell area CA does not directly flow into the panel load part 150 in FIG. 4 through the second shorting bar 222. Discharged to the edge portion 221.

In addition, the static electricity discharged to the edge portion 221 is not introduced into the panel load portion 150 of FIG. 4 again through the first shorting bar 220.

That is, the static electricity generated at the panel load portion 150 (FIG. 4) and the static electricity generated at the DIC pad portion 140 (FIG. 4) are respectively separated by the first and second shorting bars 120 and 122 spaced apart from each other through the insulating layer. Since the discharge layer has a high degree of integration, a power signal is mainly applied, and static electricity generated in the DIC pad part (140 of FIG. 4), which is a portion that floats without being electrically connected to the panel load part (150 of FIG. 4), is discharged. It can be prevented from flowing back to the panel load portion 150 (FIG. 4), and as a result, it is possible to prevent a failure of the electrical element of the panel load portion 150 (FIG. 4) due to static electricity.

As described above, in the array substrate for a liquid crystal display device according to the exemplary embodiment of the present invention, a panel load portion including a gate wiring, a data wiring, a thin film transistor, and the like, and a plurality of pads electrically floating and to which a driving integrated circuit is attached are provided. By connecting to the first and second shorting bars that are electrically insulated from each other, the failure of the electrical elements of the array substrate due to the static electricity generated from the panel load portion and the plurality of pads is prevented, and the static electricity generated from the plurality of pads is transferred to the panel load portion. It is possible to prevent the reflow and to prevent the failure of the electrical elements of the panel load.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

110, 210: Mother board 120, 220: First shorting bar
122, 222: second shorting bar 130: FPC pad portion
140: DIC pad portion 150: panel load portion

Claims (11)

A substrate comprising a plurality of cell regions each comprising a non-display region and a display region;
First and second shorting bars formed in the non-display area and spaced apart from each other via an insulating layer;
A plurality of first pads formed in the FPC pad portion of the non-display area and connected to the first shorting bar and a plurality of second pads connected to the second shorting bar;
A plurality of third pads formed in the DIC pad portion of the non-display area and electrically connected to the plurality of third pads and the plurality of third pads;
A panel load portion formed in the display area and connected to the plurality of first pads
Array substrate for a liquid crystal display device comprising a.
The method of claim 1,
The first and second shorting bars are respectively formed in each row of the plurality of cell regions, and are connected to the first and second edge portions surrounding the edges of the entire plurality of cell regions, respectively, and electrically insulated from each other. Array substrate for liquid crystal display device.
The method of claim 2,
The first and second shorting bars may be formed of the same layer and the same material to be spaced apart from each other in a plane, or may be formed of different layers and different materials to be spaced apart from each other in a cross section and overlapped with each other in a plane. Array substrate.
The method of claim 1,
The first and second shorting bars may be formed in horizontal rows of the plurality of cell regions, respectively, and connected to an edge portion surrounding the edges of the entire plurality of cell regions, and electrically shorted to each other. .
The method of claim 1,
The plurality of first pads and the plurality of second pads are pads for a flexible printed circuit (FPC), and the plurality of third pads and the plurality of fourth pads are pads for a driving integrated circuit (DIC). Array substrate.
The method of claim 1,
A plurality of first link wires connecting the first shorting bar and the plurality of first pads;
A plurality of second link wires connecting the second shorting bar and the plurality of second pads;
A plurality of third link wires connecting the plurality of first pads to the panel load;
A plurality of fourth link wires connecting the plurality of second pads and the plurality of third pads;
And a plurality of fifth link wires connecting the plurality of fourth pads to the panel load portion.
The method of claim 1,
The panel load part includes a gate wiring, a data wiring defining a pixel area crossing the gate wiring, a thin film transistor connected to the gate wiring and the data wiring, and a pixel electrode connected to the thin film transistor. Array substrate.
Forming first and second shorting bars spaced apart from each other via an insulating layer in the non-display area above the substrate, each cell including a non-display area and a plurality of cell areas;
Forming a plurality of first pads connected to the first shorting bar and a plurality of second pads connected to the second shorting bar, in the FPC pad portion of the non-display area;
Forming a plurality of third pads connected to the plurality of second pads and a plurality of fourth pads electrically floating with the plurality of third pads in the DIC pad portion of the non-display area;
Forming a panel load portion connected to the plurality of first pads in the display area
Method of manufacturing an array substrate for a liquid crystal display device comprising a.
The method of claim 8,
A plurality of first link wires connecting the first shorting bar and the plurality of first pads, a plurality of second link wires connecting the second shorting bar and the plurality of second pads, and the plurality of first pads. And a plurality of third link wires connecting the panel loads, a plurality of fourth link wires connecting the plurality of second pads and the plurality of third pads, and the plurality of fourth pads and the panel loads. A method of manufacturing an array substrate for a liquid crystal display device further comprising the step of forming a plurality of fifth link wirings to be connected.
Forming first and second shorting bars spaced apart from each other via an insulating layer in a non-display area above the array mother substrate including a plurality of cell areas;
Forming a plurality of first pads connected to the first shorting bar and a plurality of second pads connected to the second shorting bar, in the FPC pad portion of the non-display area;
Forming a plurality of third pads connected to the plurality of second pads and a plurality of fourth pads electrically floating with the plurality of third pads in the DIC pad portion of the non-display area;
Forming a panel load portion connected to the plurality of first pads in a display area above the array mother substrate;
Forming a black matrix on the color filter mother substrate;
Forming a color filter layer on the black matrix;
Forming a common electrode on the color filter layer;
Bonding the array mother substrate and the color filter mother substrate together;
Cutting the bonded mother motherboard and the color filter mother substrate into the plurality of cell regions;
Forming a unit panel by injecting liquid crystal between the bonded and cut array mother substrate and the color filter mother substrate;
Attaching a flexible printed circuit to the plurality of first pads and the plurality of second pads of the unit panel, and attaching a driving integrated circuit to the plurality of third pads and the plurality of fourth pads.
Method of manufacturing a liquid crystal display device comprising a.
The method of claim 10,
The cutting of the bonded array mother substrate and the color filter mother substrate in units of the plurality of cell regions includes removing the first and second shorting bars from the unit panel.

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