JP5602281B2 - Display device substrate and liquid crystal display device using the same - Google Patents

Description

  The present invention relates to a display device substrate, and in particular, breakdown due to static electricity generated in a manufacturing process of an active matrix type liquid crystal display device (Liquid Crystal Display) including a thin film transistor (hereinafter referred to as TFT) as a switching element. In addition, the present invention relates to a display device substrate that can easily repair (repair) defects such as interlayer short circuit.

  An active matrix type liquid crystal display device is widely used in electronic devices such as computers and large-sized televisions as a flat panel display capable of obtaining excellent image quality.

  The liquid crystal display device includes an array substrate, a counter substrate facing the array substrate, and a liquid crystal layer sealed between the array substrate and the counter substrate. On the array substrate, pixel electrodes formed for each of a plurality of pixel regions and TFTs connected to the pixel electrodes as switching elements are formed. A counter electrode is formed on the entire surface of the counter substrate. The liquid crystal display device performs liquid crystal display by applying a voltage to the liquid crystal layer from the pixel electrode and the counter electrode.

  FIG. 10 is a schematic view of a part of the array substrate as viewed from the substrate plane side. As shown in the figure, on the array substrate 1001, a plurality of gate bus lines 1010 to which scanning signals for selecting pixel electrodes to be driven are sequentially input are arranged in parallel to each other. On the array substrate 1001, a plurality of drain bus lines 1020 that are substantially orthogonal to the plurality of gate bus lines 1010 and to which gradation signals are input are disposed.

  Here, each rectangular region partitioned in a matrix by a plurality of gate bus lines 1010 and a plurality of drain bus lines 1020 orthogonal to each other is a pixel region. A plurality of the pixel areas are arranged to constitute a display area (a). In each pixel region, a TFT 1040, a pixel electrode 1030, and a storage capacitor element (or storage capacitor forming portion) 1050 that suppresses potential fluctuations of the pixel electrode 1030 are provided.

  The array substrate 1001 is provided with a plurality of storage capacitor bus lines 1060 that are connected to a plurality of storage capacitor elements 1050 along the horizontal direction in the drawing and formed in parallel with the gate bus lines 1010. Further, the storage substrate common electrode portion that is formed on the array substrate 1001 so as to extend in a direction (vertical direction in the drawing) intersecting with each gate bus line 1010 and functions as a common electrode by bundling a plurality of storage capacitor bus lines 1060. 1070 is provided. The storage capacitor common electrode portion 1070 is stacked on each gate bus line 1010 via an insulating film (not shown).

  Further, connection terminal portions such as a plurality of TAB terminals are arranged along the end portion of the array substrate 1001. A predetermined signal is supplied to the gate bus line 1010 and the drain bus line 1020 from these connection terminal portions.

By the way, since the gate bus line 1010, the drain bus line 1020, and the like are formed on an insulating glass substrate, they are basically vulnerable to static electricity. For example, when static electricity is generated on the array substrate 1001 during the manufacturing process and the static electricity flows through the gate bus line 1010 (in the direction of arrow E1 in the figure), the gate bus line 1010 and the storage capacitor common electrode portion 1070 overlap each other. Discharge occurs, causing an interlayer short circuit S. This static electricity may enter from the outside in addition to the peeling charge from the stage during substrate manufacture.

  The gate bus line 1010 in which the interlayer short-circuit S has occurred has a problem that a line defect in the bus line extending direction occurs, and the manufacturing yield of the panel is significantly reduced. In particular, static electricity easily enters from the connection terminal portion, and the static electricity entered from here discharges to the capacitive component in the path and destroys the capacitive portion. In this case, in order to remove the short-circuited portion S by laser repair or the like, it is necessary to cut the gate bus line 1010 and the like, and repair (repair) is impossible.

  As the liquid crystal display device is increased in size and definition, it is necessary to increase the wiring width of the storage capacitor common electrode portion 1070 in order to reduce the resistance. As a result, since the area of the overlapping portion where the gate bus line 1010 and the storage capacitor common electrode portion 1070 overlap is increased, the failure of the capacitor portion is also increased.

JP 2003-156663 A

  An object of the present invention is to provide a substrate for a display device that can be easily repaired even if a failure such as an interlayer short circuit due to electrostatic inflow occurs.

  The object is to form a first wiring part that is drawn out from the inside of the display area on the substrate to the outside, and the first wiring part outside the display area through an insulating film. A second wiring portion formed on the second wiring portion, an opening opening at least in a region overlapping with the first wiring portion intersecting, and formed at both ends of the opening, and the insulating film And a superimposing portion where the first and second wiring portions overlap each other through a display device substrate.

  According to the present invention, since a plurality of overlapping portions having a redundant configuration are provided, even if an interlayer short circuit failure due to static electricity occurs in one of the overlapping portions, the second overlapping portion causes the second overlapping portion to In addition to securing the conduction path of the wiring portion, it is possible to easily repair an interlayer short-circuit defect and improve the manufacturing yield.

It is a top view which shows an example of the schematic structure of the whole liquid crystal display device by the 1st Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 1st Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 2nd Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 3rd Embodiment of this invention. It is a figure which shows an example of a one part structure of the board | substrate plane of the board | substrate for display apparatuses by the 4th Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 5th Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 6th Embodiment of this invention. It is a figure which shows an example of a structure of a part of board | substrate plane of the board | substrate for display apparatuses by the 7th Embodiment of this invention. It is a figure which shows an example of a partial structure of the board | substrate plane of the board | substrate for display apparatuses by the 8th Embodiment of this invention. It is a figure which shows an example of a structure of a part of substrate plane of the conventional substrate for display apparatuses.

Hereinafter, an example of a preferred embodiment of the present invention will be specifically described with reference to the drawings. [First Embodiment]
(Overall schematic configuration)
First, an overall schematic configuration of a liquid crystal display device to which a display device substrate of the present invention is applied will be described with reference to FIG. FIG. 1 shows an overall schematic configuration of the liquid crystal display device according to the present embodiment, and shows a state in which the array substrate of the liquid crystal display device is viewed from the substrate plane side.

  In the present embodiment, a case where storage capacitor common electrode portions are provided at both ends on the array substrate is shown, and the storage capacitor common electrode portion on one end side is provided at an intersection region of the storage capacitor common electrode and the gate bus line. An opening is provided. The basic configuration of the liquid crystal display device according to this embodiment will be described below.

  As shown in FIG. 1, the liquid crystal display device according to the present embodiment has an array substrate (display device substrate) 1 in which TFTs, pixel electrodes, and the like are formed for each pixel region, and is opposed to the array substrate 1 so that the color A counter substrate 2 on which a filter, a counter electrode for forming a vertical electric field, and the like are formed, and a liquid crystal layer (not shown) sealed between the array substrate 1 and the counter substrate 2 are configured. Here, an area where pixel electrodes (not shown) are arranged in the horizontal direction and the vertical direction is the display area 3.

  As shown in FIG. 1, the array substrate 1 includes a gate bus line (first bus line) 10 for supplying a scanning signal to each pixel electrode formed in the display region 3 at a predetermined timing, and each pixel electrode. A plurality of storage capacitor bus lines 60 that are alternately connected in parallel with each gate bus line 10, and a plurality of storage capacitor bus lines that are connected to a storage capacitor element for suppressing display potential fluctuation and improving display quality. One storage capacitor common electrode portion (Cs common electrode) 70 formed on one end side of the substrate to be connected to each other end side of the substrate 60 and driven on both sides, and each one end of the plurality of storage capacitor bus lines 60 And the other storage capacitor common electrode portion 80 formed on the other end side of the substrate, and the plurality of gate bus lines 10 and the plurality of storage capacitor bus lines 60 are formed substantially orthogonal to each other at a predetermined timing. so Configured to include a drain bus line for supplying a tone signal (a second bus line) (not shown in FIG. 1), the.

  The gate bus line 10 corresponds to the “first wiring portion” according to the present invention, and the one storage capacitor common electrode portion 70 corresponds to the “second wiring portion” according to the present invention. However, the “first wiring portion” referred to in the present invention may include the gate bus line 10 and the drain bus line (not shown in FIG. 1), or the “second wiring portion” referred to in the present invention. Can also include the storage capacitor bus line 60 and the storage capacitor common electrode portions 70 and 80.

  The array substrate 1 is formed to be larger than the counter substrate 2, and drive circuit arrangement regions are formed in two protruding regions protruding from the counter substrate 2. A plurality of gate automated bonding (TAB) terminals (external connection terminals) 4 for bundling a plurality of gate bus lines 10 are formed at one end 1a of the protruding region, and a plurality of drains are formed at the other end 1b. A plurality of drain TAB terminals (external connection terminals) 5 for binding the bus lines are formed.

  Further, the drain TAB terminal 5 positioned on both ends of the array substrate 1 has connection lines 6a and 6b formed extending from the one and other storage capacitor common electrode portions 70 and 80 in addition to the drain bus line. It is connected.

  A part of the plurality of gate bus lines 10 is connected to the gate TAB terminal 4 by forming a lead-out portion that is bent and inclined from the gate bus line 10.

  The storage capacitor common electrode portions 70 and 80 are formed at both ends when a voltage is supplied from both sides of the storage capacitor bus line 60 so that the wiring length of the storage capacitor bus line 60 is long or the number of wirings is large. This is to be able to cope with this.

  The gate bus line 10 and one of the storage capacitor common electrode portions 70 overlap with each other via an insulating film. The storage capacitor common electrode portion 70 has a configuration in which an opening is provided in the overlapping region. This will be specifically described below.

(Detailed configuration of array substrate 1 of the present embodiment)
Here, the feature of the present embodiment, that is, the specific configuration of the storage capacitor common electrode portion 70 of the array substrate 1 will be described with reference to FIG. FIG. 2 is a diagram showing a configuration of the array substrate 1 on which the pixel electrodes of the active matrix liquid crystal display device according to the present embodiment are formed, and shows a plurality of image regions as viewed toward the substrate surface. It is a figure which expands and shows the part enclosed with the circle A of the broken line. In FIG. 2, the external connection terminals shown in FIG. 1 are not shown.

  On the array substrate 1, as shown in FIG. 2, a plurality of gate bus lines 10 (two are shown in FIG. 2) extending in parallel with each other in the horizontal direction of the drawing, and a plurality of gate bus lines 10 are abbreviated. A plurality of drain bus lines 20 (two are shown in FIG. 2) extending in the vertical direction in parallel with each other are formed so as to be orthogonal to each other.

  In addition, on the array substrate 1, pixel electrodes 30 and TFTs (driving elements) 40 disposed at intersections intersecting the plurality of gate bus lines 10 and the plurality of drain bus lines 20, and the pixel electrodes 30. Are formed corresponding to the storage capacitor element 50.

  The storage capacitor element 50 includes a storage capacitor electrode (intermediate electrode) connected to the pixel electrode 30 through a contact hole at the center position of the pixel electrode 30, an insulating film formed under the storage capacitor electrode, and a lower layer of the insulating film. And a storage capacitor counter electrode portion which is a partial region facing the storage capacitor electrode of the storage capacitor bus line 60 formed on the storage capacitor. The storage capacitor element 50 forms a storage capacitor using the storage capacitor electrode as one electrode and the storage capacitor counter electrode portion of the storage capacitor bus line 60 as the other electrode.

  In the array substrate 1, when the TFT 40 is turned on, a predetermined potential is written for each pixel electrode 30, and the voltage applied to the liquid crystal layer is controlled for each pixel region. The voltage applied to the liquid crystal layer needs to be maintained until the next frame even when the TFT 40 is turned off. However, the potential of the pixel electrode 30 varies within one frame period due to parasitic capacitance generated in the TFT 40, leakage current generated between the pixel electrode 30 and the common electrode, and the like. Therefore, the storage capacitor element 50 suppresses the fluctuation of the potential of the pixel electrode 30 so that the voltage applied to the liquid crystal layer is maintained for one frame period.

A part of the plurality of gate bus lines 10 has a bent portion 11 that is bent so as to be inclined from the display region (a) toward the gate TAB terminal 4 (not shown in FIG. 2). The bent portion 11 is formed across the width region (b) of the storage capacitor common electrode portion 70. A gate TAB terminal 4 is formed in the outer region (c) from the position where the storage capacitor common electrode portion 70 is disposed. Depending on the position where the gate bus line 20 is formed, there is a gate bus line 20 that does not require the bent portion 11 to be connected to the gate TAB terminal 4.

  The storage capacitor bus line 60 is electrically connected to the storage capacitor common electrode portion 70 via the connection electrode 61 and the connection portions 62a and 62b.

  The storage capacitor common electrode portion 70 is laminated on each gate bus line 10 via an insulating film (not shown) at a position outside the display region (a), and an opening is formed in a region overlapping each gate bus line 10. 72 is formed.

  The opening 72 opens along the bent portion 11 of the gate bus line 10. The length of the opening 72 is L1, the length from one end in the width direction of the storage capacitor common electrode portion 70 to one end of the opening 72 is L2, and the length from the other end in the width direction of the storage capacitor common electrode portion 70 is opened. The length to the other end of the part 72 is L3.

  As a result, two overlapping portions 74 constituting the lengths L2 and L3 are formed for one gate bus line 10. The overlapping portion 74 includes a storage capacitor common electrode portion 70, an insulating film formed under the storage capacitor common electrode portion 70, and a gate bus line 10 formed under the insulating film.

  Conventionally, since no opening is formed in the storage capacitor common electrode portion 70, when the interlayer short circuit occurs and repair is performed by laser cutting or the like, the conduction of the storage capacitor common electrode portion 70 is interrupted. On the other hand, in the storage capacitor common electrode portion 70 of the present embodiment, since the opening 72 is configured, a redundant configuration including at least two overlapping portions 74 per gate bus line 10 can be formed. For this reason, even if the short circuit location S occurs in one of the two overlapping portions 74, the conduction path of the storage capacitor common electrode portion 70 can be secured by the other overlapping portion 74. This improves the manufacturing yield.

  Further, the length d of the opening 72 in the direction in which the storage capacitor common electrode portion 70 extends is formed slightly larger than the width of the gate bus line 10. Except for the region overlapping the gate bus line 10, no interlayer short circuit can occur, so there is no need to provide an opening. In this way, the opening area of the opening 72 can be made as small as possible, and the storage capacitor common electrode portion 70 can be configured as a ladder structure to minimize the resistance of the storage capacitor common electrode portion 70 from becoming unnecessarily high. it can. For this reason, the storage capacitor common electrode part 70 can be formed so that the resistance hardly changes due to the ladder structure.

  On the other hand, it is preferable that the length L1 of the opening 74 is formed as long as possible, and the lengths L2 and L3 of each overlapping portion 74 are configured as short as possible. In other words, since the overlapping area between the gate bus line 10 and the storage capacitor common electrode portion 70 can be reduced, the capacitance component related to the gate bus line 10 can be reduced, so that an additional effect of suppressing the waveform dullness of the gate pulse is also produced. is there. In particular, the storage capacitor common electrode portion 70 requires a thick wiring width of 500 to 1500 μm when the resolution is, for example, XGA (1024 × 768) or higher. Even when such a wiring width is required, the opening 72 is formed. By forming, the capacitance in the overlapping region with the storage capacitor common electrode portion 70 which is a part of the capacitance component of the gate bus line 10 can be reduced, and the waveform dullness of the gate pulse can be reduced. Further, if the lengths L2 and L3 of the overlapping portion 74 are short, the short-circuit portion S formed in the overlapping portion 74 can be easily cut by laser cutting or the like, so that the repair is easy.

The gate electrode, the gate bus line 10 and the storage capacitor bus line 60 of the TFT 40 are formed in the same conductive layer (first conductive layer), and the source electrode and drain electrode of the TFT 40, the drain bus line 60, the storage capacitor common electrode. The portion 70 is formed in the same conductive layer (second conductive layer), and the pixel electrode 30 and the connection electrode 61 are formed in the same conductive layer (third conductive layer). An insulating film is formed between the conductive layers to prevent a short circuit between the conductive layers.

(About the repair method of the short-circuited part)
The liquid crystal display device of the present embodiment has the above-described configuration and operates as follows. First, it is assumed that static electricity E1 generated during the manufacturing process of the array substrate 1 enters through the gate bus line 10 from the gate TAB terminal 4 side outside the display area toward the position where the storage capacitor common electrode portion 70 is disposed.

  When the static electricity E1 enters, for example, an interlayer short circuit occurs at the short circuit location S of the overlapping portion 74 on the left side of FIG. And in order to repair the short circuit location S, a short circuit location is specified by the test | inspection by pattern recognition etc., for example.

  Next, in the storage capacitor common electrode part 70, the cutting positions C1 and C2 on both ends of the short-circuited part S are irradiated with laser light and cut by laser cutting. At this time, since the length L2 of the overlapping portion 74 to be cut is short, it can be easily cut. In this way, by cutting the storage capacitor common electrode portion 70 of the overlapping portion 74, the storage capacitor common electrode portion 70 and the gate bus line 10 can be electrically separated at the short-circuit portion S.

  Thereby, the interlayer short circuit can be repaired, and the array substrate 1 does not become a defect. In this way, defect repair is completed. Note that when the repair is performed, the repair on the gate bus line 10 side is not necessary.

  Further, due to the redundant configuration of the two overlapping portions 74, even if a short-circuit portion S occurs in one overlapping portion 74 formed on the gate TAB terminal 4 side, the other overlapping portion 74 has the storage capacitor common electrode 70. A conduction path can be secured.

  As described above, according to the present embodiment, the redundant configuration of the two overlapping portions 74 can be formed in the storage capacitor common electrode portion 70. For this reason, even if an interlayer short circuit failure due to static electricity generated during the manufacturing process or the like occurs in one of the two overlapping portions 74, the other overlapping portion 74 causes the storage capacitor common electrode portion 70. Thus, the repair can be performed while securing the conduction path of the semiconductor device, and the manufacturing yield is improved.

  Further, by forming the storage capacitor common electrode portion 70 as a ladder structure by the opening 72 and making the opening area of the opening 72 as small as possible, the storage capacitor common electrode portion 70 can be formed with almost no change in resistance.

  Furthermore, since the area of the overlapping portion 74 is reduced, the waveform dullness of the gate pulse flowing through the gate bus line 10 can be reduced. In particular, even when a thick wiring width is required, the waveform dullness can be reduced by forming the opening 72. Further, the short-circuit portion S formed in the overlapping portion 74 is easily cut by laser cutting or the like.

  Furthermore, since a short-circuit location cannot occur in the opening 72, the short-circuit location can be limited to an overlapping portion other than the opening in the intersecting region. For this reason, the short circuit scale per one bus line (area area of the short circuit part) can be minimized.

Further, when the projecting region, which is the region where the drive circuit is arranged, is made small due to the demand for narrowing the frame, there is a portion having a wiring where the inclination angle of the bent portion 11 of the gate bus line 10 becomes steep. In this case, the overlapping region between the storage capacitor common electrode part 70 and the gate bus line 10 increases. However, in this embodiment, the overlapping region is reduced by forming the opening 72, thereby reducing the waveform of the gate pulse. Can be suppressed.

  In addition, in the present embodiment, since only the shape of the storage capacitor common electrode portion is different from that of the conventional array substrate, it can be carried out without increasing the number of manufacturing steps.

[Second Embodiment]
Next, a second embodiment according to the present invention will be described with reference to FIG. In the following, description of the configuration substantially similar to that of the first embodiment will be omitted, and only different parts will be described. FIG. 3 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the second embodiment of the present invention.

  In the first embodiment described above, one opening 72 of the storage capacitor common electrode portion 70 is provided for each gate bus line 10, but in this embodiment, one gate bus is provided. A plurality of, for example, two openings 172 and 174 are provided per line 110, and three overlapping portions 176 are provided to further increase the redundancy.

  Specifically, as shown in FIG. 3, the array substrate 100 included in the liquid crystal display device includes a gate bus line 110, a drain bus line 120, a pixel electrode 130, a thin film transistor 140, as in the first embodiment. The storage capacitor bus line 160 and the storage capacitor common electrode unit 170 are included.

  The storage capacitor common electrode portion 170 has two openings 172 and 174 and three overlapping portions 176 along the bent portion 111 of one gate bus line 110. Here, the opening width L3 of the opening 172 and the opening width L6 of the opening 174 are formed to be substantially equal. Moreover, the width L4 and the width L7 of the overlapping portion 176 are formed to be substantially equal, and the width L5 of the overlapping portion 176 is formed to be longer than the width L4 and the width L7.

  The entire opening area of the two openings 172 and 174 is formed to be smaller than the opening area of one opening 72 (FIG. 2) of the first embodiment. That is, the width obtained by adding the width L3 and the width L6 in FIG. 3 is smaller than the width L2 in FIG.

  In the array substrate 100 configured as described above, when static electricity enters from the direction of the arrow E1, the following effects are obtained. That is, when an interlayer short circuit occurs at the short circuit location S, the periphery of the short circuit location S is cut using a laser.

  Here, by configuring the opening 172 and the opening 174, even if one current path is cut by laser cutting among the three current paths, the remaining two current paths are secured.

  Further, it is conceivable that the interlayer short circuit is formed in order from the penetration direction E1 along the gate bus line 110. That is, a short circuit may occur between the overlapping portion 176 having the width L4 and the overlapping portion 176 having the width L5. In this case, since the current path can be secured by the overlapping portion 176 having the width L7, even if the overlapping portion 176 having the width L4 and the overlapping portion 176 having the width L5 are cut and repaired by laser cutting or the like, the storage capacitor common electrode portion 170 is used. Can be used as is.

  As described above, according to the present embodiment, two openings 172 and 174 are provided, and three overlapping portions 176 where the storage capacitor common electrode portion 170 and the gate bus line 110 overlap are formed. Even if one or two of the current paths are cut by laser cutting, other current paths can be secured.

[Third Embodiment]
Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 4 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially similar to that of the first and second embodiments will be omitted, and only different parts will be described.

  In the first and second embodiments described above, the opening 72 is formed along the direction in which one gate bus line 10 extends. However, in this embodiment, the storage capacitor common electrode portion 270 The opening 272 is formed along the extending direction.

  Specifically, as shown in FIG. 4, the array substrate 200 of the present embodiment has a gate bus line 210 including a bent portion 211, a drain bus line 220, and a pixel electrode 230, as in the first embodiment. , The thin film transistor 240, the storage capacitor bus line 260, and the storage capacitor common electrode portion 270.

  The vertically long opening 272 of the storage capacitor common electrode part 270 has a long opening in the direction in which the storage capacitor common electrode part 270 extends. A plurality of, for example, four openings 272 are formed and arranged along the direction in which the gate bus lines 210 extend. As a result, five overlapping portions 274 are formed.

  Such a configuration of the opening 272 has the following effects. That is, in the first and second embodiments, it is necessary to form the openings 72 in accordance with the 10 wiring patterns of the gate bus lines. On the other hand, in the present embodiment, the opening 272 of the storage capacitor common electrode portion 270 is formed so as to open long in the wiring direction in which the storage capacitor common electrode portion 270 extends. Even when there is a design change in the pattern, it is not necessary to redesign the storage capacitor common electrode portion 272.

  For example, the interval between the gate bus lines 210 arranged in parallel to each other is different from the pitch in the display area and the arrangement pitch on the side of the external connection terminal drawn from the display area. There may also be places where it is necessary to form. At this time, the inclination of each bent portion is different for each gate bus line 210. For this reason, in the case of the first and second embodiments, the position and shape of each opening 72 are arranged in accordance with the wiring pattern of the gate bus line 10 such as the inclination angle of the bent portion 11 of the gate bus line 10. However, as in the present embodiment, the openings 272 of the storage capacitor common electrode portion 272 can be easily configured by design as in the present embodiment, and a burden in designing the layout. Can be reduced.

  In particular, in a liquid crystal display panel having a narrow protruding area, a portion where the inclination angle of the gate bus line 210 is much steeper than that of a liquid crystal display panel having a wide protruding area occurs. In such a case, since the vertically long opening 272 can be formed uniformly without depending on the layout of the gate bus line 210, the storage capacitor common electrode 272 including the opening 272 can be easily manufactured. In addition, it is easy to repair when an interlayer short-circuit occurs.

[Fourth Embodiment]
Next, a fourth embodiment according to the present invention will be described with reference to FIG. FIG. 5 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially similar to that of the first embodiment will be omitted, and only different parts will be described.

  In this embodiment, the bypass wiring 380 is arranged along the same direction so as to overlap with each other through the insulating film along the wiring direction of the storage capacitor common electrode portion 370. Specifically, as shown in FIG. 5, the array substrate 300 of this embodiment includes a gate bus line 310, a drain bus line 320, a pixel electrode 330, a thin film transistor 340, a storage capacitor bus line 360, and a storage capacitor common electrode section. 370 and a bypass wiring 380. The bypass wiring 380 corresponds to the “third wiring portion” in the present invention.

  The storage capacitor common electrode portion 370 forms an opening 372 that opens in a direction along the gate bus line 310. As a result, two overlapping portions 374 are formed.

  The bypass wiring 380 is formed along the wiring direction of the storage capacitor common electrode portion 370 so as to straddle the plurality of openings 372, and is stacked on the storage capacitor common electrode portion 370 with an insulating film interposed therebetween.

  The connection portions 382 and 384 are formed by electrically connecting the bypass wiring 380 and the storage capacitor common electrode portion 370 and melting by laser light irradiation in the repairing process of the storage capacitor common electrode portion 380. In FIG. 5, for example, four connection portions 382 and 384 are formed for one opening 372. Thereby, the bypass wiring 380 can have the same function as the storage capacitor common electrode portion 370.

  The configuration of the array substrate 300 as described above operates as follows. That is, external static electricity does not always enter through the gate bus line 310, and the direction indicated by the arrow E2 from the drain TAB terminal side (upper side in FIG. 5), which is one end in the direction in which the storage capacitor common electrode portion 370 is wired. It is possible that static electricity will flow in.

  In this case, the interlayer short-circuit may extend to a plurality of locations, and short-circuit locations S1 and S2 are generated in each overlapping portion 374. And while cut | disconnecting both short circuit location S1 and S2 by laser cut etc., the connection parts 382 and 384 are formed by irradiating the bypass wiring 380 with a laser beam.

  Thereby, even if both of the short-circuited portions S1 and S2 are cut by laser cutting or the like, a conduction path can be secured by the bypass wiring 380 and the connection portions 382 and 384, and the storage capacitor common electrode portion 370 is repaired. be able to.

  Moreover, the connecting portions 382 and 384 can be easily formed by using the laser beam irradiation position used at the time of cutting in the repair process of the short-circuited portions S1 and S2. Further, the formation positions of the connection portions 382 and 384 can be freely determined according to the shorted position.

Note that the bypass wiring 380 is a transparent electrode (ITO: Induu) used for a pixel electrode or the like.
The m Tin Oxide) layer is preferably formed by patterning on the insulating film on the storage capacitor common electrode portion 370.

  That is, outside the display region, the gate bus line 310 (first layer), the insulating film (second layer), the storage capacitor common electrode portion 370 (third layer), the second insulating film (fourth layer) are formed on the insulating substrate. ), Bypass wiring 380 (fifth layer) is laminated in this order. In a part of the display area (pixel area), the storage capacitor bus line 360 (first layer), the insulating film (second layer), the storage capacitor electrode (third layer), and the second insulation are formed on the insulating substrate. A film (fourth layer) and a pixel electrode 330 (fifth layer) are stacked in this order.

Therefore, the fifth-layer bypass wiring 380 can be simultaneously formed of the same material and in the same layer as the pixel electrode 330. Thereby, it is not necessary to form using other materials specially, it is possible to use the same material as the transparent electrode layer, and it is not necessary to add a new process.

  Further, even if the opening 372 is formed in the storage capacitor common electrode portion 370, by configuring the bypass wiring 380, the resistance can be reduced by the sum of the areas of the bypass wiring 380 and the storage capacitor common electrode portion 370. Can do.

[Fifth Embodiment]
Next, a fifth embodiment according to the present invention will be described with reference to FIG. FIG. 6 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially the same as that of each of the first to fourth embodiments will be omitted, and only different parts will be described.

  In the above-described fourth embodiment, one bypass wiring 380 is disposed on the storage capacitor common electrode portion 370. However, in this embodiment, a plurality of bypass wirings 480 are disposed on the storage capacitor common electrode portion 470. It is set as the structure arrange | positioned above. Specifically, the array substrate 400 of the liquid crystal display device of this embodiment includes a gate bus line 410, a drain bus line 420, a pixel electrode 430, a thin film transistor 440, a storage capacitor bus line 460, a storage, as shown in FIG. The capacitor common electrode portion 470 and a plurality of bypass wirings 480 (three in FIG. 6) are included.

  The storage capacitor common electrode portion 470 has an opening 472 along the gate bus line 410. Each of the plurality of bypass wirings 480 is formed along the wiring direction of the storage capacitor common electrode part 470 so as to cover the plurality of openings 472, and is laminated on the storage capacitor common electrode part 470 via an insulating film. Is done.

The central bypass wiring 480 includes connection portions 482 and 484 that are electrically connected to the storage capacitor common electrode portion 370. The connection portions 482 and 484 are formed by being melted by irradiating laser light in the repairing process of the storage capacitor common electrode portion 370.
In FIG. 6, two connection portions 482 and 484 are formed in the central bypass wiring 480.

  The array substrate 400 having the above-described configuration operates as follows. That is, the inflow of static electricity also occurs from the direction in which the storage capacitor common electrode portion 470 is wired from the external storage capacitor TAB terminal side (upper side in FIG. 6) as indicated by the arrow E2.

  When an interlayer short-circuit occurs at the short-circuited locations S1 and S2 due to static electricity from the inflow direction E2, even if the location is cut by laser cutting, the conduction path is connected via the connection portions 482 and 484 by the bypass wiring 480. Can be secured.

  By the way, the interlayer short-circuit due to the inflow of static electricity from the gate bus line 410 is not limited to the short-circuit locations S1 and S2, but the storage capacitor common electrode portion 470 forms the opening 472, so that the gate bus line 410 and the bypass wiring 480 are formed. A short circuit between the layers can also be considered. Even in such a case, the storage capacitor common electrode portion 470 can be easily repaired by forming a plurality of bypass wirings 480.

As described above, according to the present embodiment, by forming a plurality of bypass wirings 480, even if all the overlapping portions of the storage capacitor common electrode portion 470 are short-circuited due to static electricity flowing from each direction, a plurality of bypass wirings are provided. Any one of 480 can be used. Thereby, the conduction of the storage capacitor common electrode portion 470 can be ensured, and the entire panel can be repaired only by using the laser beam for the repair of the short circuit portion and the connection of the bypass wiring 480.

[Sixth Embodiment]
Next, a sixth embodiment according to the present invention will be described with reference to FIG. FIG. 7 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially similar to that of the first to fifth embodiments will be omitted, and only different parts will be described.

  In the fifth embodiment described above, the electrical connection means between the storage capacitor common electrode portion 470 and the plurality of bypass wirings 480 is configured by laser connection. However, in this embodiment, the contact hole portion is formed in advance. It has a configuration to keep. Specifically, the array substrate 500 of the liquid crystal display device of this embodiment includes a gate bus line 510, a drain bus line 520, a pixel electrode 530, a thin film transistor 540, a storage capacitor bus line 560, a storage, as shown in FIG. The configuration includes a common capacitor electrode portion 570 and a plurality of bypass wirings 580 (three examples are shown in the figure).

  The storage capacitor common electrode portion 570 has openings 572 a and 572 b along the gate bus line 510.

  A plurality of, for example, three bypass wirings 580 are formed, and are formed along the wiring direction of the storage capacitor common electrode portion 570 so as to straddle the plurality of openings 572a and 572b. It is laminated on the second insulating film.

  Each bypass wiring 580 is configured to be electrically connected to the storage capacitor common electrode portion 570 via connection portions 582, 584, 585, and 586. A description will be given of one bypass wiring 580. An upper connecting portion 582 and a lower connecting portion 582 in the drawing are configured with respect to one opening 572a to secure a conduction path, and another opening 572b is connected to the other opening 572b. In contrast, an upper connecting portion 586 in the drawing and a lower connecting portion 588 in the drawing are configured. Three bypass wirings 580 are provided side by side with respect to one opening 572a.

  The connection portions 582, 584, 585, and 586 electrically connect the bypass wiring 580 and the storage capacitor common electrode portion 570 through a contact hole portion that is formed by opening an insulating film (not shown).

  In this embodiment, with respect to one gate bus line 510, a plurality of bypass wiring portions 580 and a storage capacitor common electrode portion 570 are connected in advance by connection portions 582, 584, 585, and 586.

  For this reason, even if a short circuit occurs between one bypass wiring 580 and the gate bus line 510 in addition to the short circuit locations S1 and S2 due to the inflow of static electricity from each direction, another bypass wiring 580 can be used. Therefore, the conduction of the storage capacitor common electrode portion 570 can be ensured through the other bypass wiring 580, and the entire panel can be repaired.

  In addition, since the storage capacitor common electrode portion 570 can include the area of the bypass wiring 580, the resistance can be reduced.

Further, since the layer thickness between the gate bus line 510 and the storage capacitor common electrode portion 570 is different from the layer thickness between the gate bus line 510 and the bypass wiring 580, the bypass wiring 580 is less affected by static electricity. Bypass wiring 580 and gate bus line 510
It is preferable because an interlayer short circuit is difficult to occur. Note that the interlayer film thickness between the bypass wiring 580 and the storage capacitor common electrode portion 570 may be increased.

[Seventh Embodiment]
Next, a seventh embodiment according to the present invention will be described with reference to FIG. FIG. 8 is a diagram showing an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially similar to that of the first to sixth embodiments will be omitted, and only different parts will be described.

  In the first to sixth embodiments described above, the repair by the interlayer short circuit between the gate bus line 10 and the storage capacitor common electrode portion 70 is facilitated. However, in the present embodiment, ESD (Electro Static) is employed. (Discharge) shows a case where a short circuit is formed between the common electrode portion 670 for electrostatic protection that bundles the wiring for the protective portion and the gate bus line 610.

  FIG. 8 shows a structural example of the electrostatic protection unit 620 in which the electrostatic protection common electrode unit 670 is formed. Specifically, as shown in FIG. 8, the array substrate 600 includes a gate bus line 610, an electrostatic protection unit 620 that is connected to the gate bus line 610 and prevents the TFT from being destroyed by static electricity, and an electrostatic protection unit. And an electrostatic protection bus line 660 extending from 620.

  Furthermore, the array substrate 600 has a common electrode part 670 for electrostatic protection that bundles a plurality of bus lines 660 for electrostatic protection. The common electrode portion for electrostatic protection 670 extends between the display region and the gate TAB terminal (not shown) in a direction intersecting with the gate bus line 610 (vertical direction in the drawing).

  The gate bus line 610 corresponds to the “first wiring portion” according to the present invention, and the common electrode portion 670 for electrostatic protection corresponds to the “second wiring portion” according to the present invention. However, the “first wiring portion” according to the present invention may include the gate bus line 10 and the drain bus line (not shown in FIG. 1), or the “second wiring portion” according to the present invention. In addition, the bus line 660 for electrostatic protection and the common electrode part 670 for electrostatic protection can be included, and in addition, the storage capacitor bus line 60 and the storage capacitor common electrode parts 70 and 80 of the first embodiment can be included. it can.

  The electrostatic protection unit 620 is an electrostatic protection circuit, for example, a first TFT 622 that is a first switching element connected to the gate bus line 610 and a second switching element that is also connected to the gate bus line 610. A second TFT 624, a first TFT 622, a second TFT 624, and a third TFT 626 connected to the electrostatic protection bus line 660 are included.

  The gate electrodes G of the first to third TFTs 622, 624, and 626 are simultaneously formed on the glass substrate when the gate bus line 610 and the gate electrode of the TFT in the pixel region are formed. The gate electrodes G of the first and third TFTs 622 and 626 are formed electrically isolated from other wiring structures.

The source electrode S / drain electrode D of the first to third TFTs 622, 624, and 626 are formed of the same forming material simultaneously with the formation of the electrostatic protection bus line 660 and the electrostatic protection common electrode portion 670. The source electrode S of the first TFT 622 and the source electrode S of the second TFT 624 are connected to the gate bus line 610 through contact hole portions 630 and 632, respectively. The source electrode S / drain electrode D between the first and third TFTs 622 and 626 functions as a conductor and forms a capacitance with the gate electrode G of the second TFT 624. The drain electrode D of the second TFT 624 and the drain electrode D of the third TFT 626 are connected to the electrostatic protection common electrode portion 670 via the electrostatic protection bus line 660.

  In this example, the channel lengths of the first and third TFTs 622 and 626 are shorter than the channel length of the second TFT 624. Thus, when static electricity is generated in the gate bus line 610 with a very sharp pulse voltage, the first or third TFT 622, 626 is first destroyed before the second TFT 624 is destroyed. Two TFTs 624 can be protected. Therefore, even if one of the first or third TFTs 622 and 626 is destroyed, the gate bus line 610 and the electrostatic protection common electrode portion 670 are not directly short-circuited. There is no problem in the process.

  In addition, the channel widths of the first and third TFTs 622 and 626 are made equal to each other, and the channel width of the second TFT 624 is approximately the same. Therefore, the conductivity of the second TFT 624 and the conductivity when the first and third TFTs 622 and 626 are viewed in series are substantially the same, and the current sharing in the electrostatic protection is shared between the second TFT 624 and the first and third TFTs. The TFTs 622 and 626 can be separated.

  The common electrode part 670 for electrostatic protection is laminated on the gate bus line 610 via an insulating film (not shown). Further, as shown in FIG. 8, the electrostatic protection common electrode portion 670 has an opening 672 formed along the bent portion 611 of the gate bus line 610 in a region overlapping with the gate bus line 610. .

  One opening 672 is formed for each gate bus line 610, and overlapping portions 674 are formed on both edges of the opening 672.

  In the array substrate 600 of the liquid crystal display device configured as described above, when static electricity E1 flows from the outside of the gate bus line 610, an interlayer short-circuit occurs between the static protection common electrode portion 670 and the gate bus line 610. Occurs in S.

  Then, in the common electrode portion 670 for electrostatic protection, the interlayer short circuit can be repaired by laser cutting the cutting positions C1 and C2 which are both ends of the short circuit portion S. Thereby, even if one superimposition part 674 is cut | disconnected, the conduction | electrical_connection path | route can be ensured by the other superimposition part 674. FIG. For this reason, the common electrode part 670 for electrostatic protection can be repaired easily. At this time, it is not necessary to repair the gate bus line 610 side.

  As described above, in addition to the common wiring portions of the embodiments, the static electricity protection bus line 660 connected to the static electricity protection portion (static electricity protection circuit or static electricity protection element) 620 for preventing static electricity of the gate bus line 610. The electrostatic protection common electrode portion 670 for bundling can also employ a configuration in which an opening 672 is formed in a region overlapping with the gate bus line 610, thereby facilitating repair.

  In the present embodiment, the electrostatic protection unit 620 is formed on the gate bus line 610. However, the electrostatic protection unit 620 may be provided on the drain bus line (not shown). Furthermore, it goes without saying that an electrostatic protection unit 620 may be provided in each of the gate bus line 610 and the drain bus line. And even if it is a case where the common electrode part 670 for electrostatic protection is comprised as a common line by the side of a rain bus line, you may provide an opening part in the common electrode part 670 for electrostatic protection.

  The structure of the electrostatic protection circuit described above is applied to a liquid crystal display device in which a channel etching type TFT is formed in a pixel region, but is not limited to this, and a liquid crystal display provided with an etching stopper type TFT. You may apply the electrostatic protection circuit by this Embodiment to an apparatus. In addition, instead of the first TFT 622 and the third TFT 626, first and second resistors may be configured.

  Further, the configuration of the electrostatic protection unit 620 is not limited to the electrostatic protection circuit disclosed in this embodiment, and may be an electrostatic protection element. At this time, by electrically connecting the bus lines to each other with a high resistance element, a common wiring portion that serves to diffuse the current flowing through one bus line is disposed. Since this common wiring overlaps the gate or drain bus line, the electrode can be repaired by partially removing one of the overlapping portions as in the first and second embodiments.

  Further, a set of electrostatic protection units 620 may be formed on each bus line, and the elements formed in the electrostatic protection unit 620 may be shared as much as possible to reduce the total number of elements. By doing this, the number of constituent elements can be reduced by reducing the defect occurrence rate of the constituent elements, the area occupied by the elements, and the like.

[Eighth Embodiment]
Next, an eighth embodiment according to the present invention will be described with reference to FIG. FIG. 9 is a diagram illustrating an example of a partial configuration of the substrate plane of the display device substrate according to the present embodiment. In the following, description of the configuration substantially similar to that of the first embodiment will be omitted, and only different parts will be described.

  In the above-described first to sixth embodiments, the repair is facilitated by the interlayer short circuit between the gate bus line 10 and the storage capacitor common electrode portion 70. However, in the present embodiment, the IPS (In In a plane switching type (horizontal electric field type) liquid crystal display device, a counter for forming a horizontal electric field (other than the pixel electrode, each source electrode, gate electrode, drain electrode, and storage capacitor element) formed on the array substrate 700 is used. The configuration is such that each line of electrodes (different from the counter electrode for forming a vertical electric field on the counter substrate side in the TN or VA system) is used as an electrode unit bundled.

  In this horizontal electric field type liquid crystal display device, an array substrate 700 (display device substrate) in which TFTs, pixel electrodes, a counter electrode for forming a horizontal electric field, and the like are formed for each pixel region, and the array substrate 700 are arranged to face each other. It includes a counter substrate (not shown) and a liquid crystal layer (not shown) sealed between the array substrate 700 and the counter substrate. Here, a display region is a region in which the pixel electrode 730 and the counter electrode 750 for forming a horizontal electric field face each other and are arranged in a comb shape.

  FIG. 9 shows a substrate plane when the array substrate of the horizontal electric field type liquid crystal display device is viewed from the liquid crystal layer side. In the figure, the external connection terminal area of the gate bus line is not shown in the middle, and only the vicinity of the display area is shown.

  Specifically, the array substrate 700 is used in a horizontal electric field type liquid crystal display device. As shown in FIG. 9, a plurality of gate bus lines 710 (first bus lines) and a plurality of gate bus lines 710 orthogonal to each other are provided. Drain bus lines 720 (second bus lines), and source electrodes and pixel electrodes 730 of the respective TFTs 740 respectively disposed at intersections of the plurality of gate bus lines 710 and the plurality of drain bus lines 720. .

Further, the array substrate 700 is arranged corresponding to each pixel electrode 730 and forms a horizontal electric field with the pixel electrode 730, and each of the horizontal field forming counter electrodes 750 has a horizontal electric field. A plurality of counter electrode bus lines (third bus lines) 760 formed between the gate bus lines 710 and connected to each other and function as a bundling unit for bundling the plurality of counter electrode bus lines 760. And a common electrode portion 770 for electrodes.

  The gate bus line 710 corresponds to the “first wiring portion” according to the present invention, and the common electrode portion 770 for the counter electrode corresponds to the “second wiring portion” according to the present invention. However, the “first wiring portion” according to the present invention can include the gate bus line 710 and the drain bus line 720, and the “second wiring portion” according to the present invention includes the above-described embodiments. The storage capacitor bus line / storage capacitor common electrode section, the electrostatic protection bus line, and the electrostatic protection common wiring section can be included.

  As shown in FIG. 9, the drain bus line 720 extends in the vertical direction in the figure, and is supplied with a gradation signal. The gate bus line 710 is formed to extend in the left-right direction in the drawing orthogonal to the drain bus line 720 and is supplied with a scanning signal. A region defined by the drain bus line 720 and the gate bus line 710 is a pixel region.

  Note that one end of the drain bus line 720 is provided with an external connection terminal (not shown) for electrical connection with an external element. Similarly, one end of the gate bus line 710 is provided with an external connection terminal for electrical connection with an external element.

  The TFT 740 is formed, for example, in a channel etch type, and is formed in the vicinity of the intersection position of each drain bus line 720 and the gate bus line 710. The drain electrode of the TFT 740 is formed so as to be drawn from the drain bus line 720 and its end is located on one end side on the operating semiconductor layer (not shown) on the gate bus line 710. The source electrode of the TFT 740 is formed on the other side of the operating semiconductor layer so as to face the drain electrode. In such a configuration, the gate bus line 710 region immediately below the operating semiconductor layer functions as the gate electrode of the TFT 740.

  Although not shown, a gate insulating film is formed on the gate bus line 710, and an operating semiconductor layer that forms a channel is formed on the gate insulating film. The operating semiconductor layer is formed along the gate bus line 710 above the gate bus line 710, and is electrically isolated from the operating semiconductor layer of the TFT in another adjacent pixel region. In the TFT structure shown in FIG. 9, the gate electrode is not formed by being drawn out from the gate bus line 710, and a part of the gate bus line 710 formed in a linear shape is used as the gate electrode.

  The pixel electrode 730 is directly drawn into the pixel region from the source electrode of the TFT 740 to form a substantially comb-shaped first concavo-convex portion extending downward from the upper side in the drawing.

The horizontal electric field forming counter electrode 750 is formed in the pixel region on the array substrate 700, and is opposed to the first concavo-convex portion of the pixel electrode 730 so as to oppose and extend up and down in the figure. Concave and convex portions are formed.

  In the IPS system, an electric field is applied to the liquid crystal layer in the horizontal direction (lateral direction). Therefore, the array substrate 700 is provided on the array substrate 700 together with the pixel electrode 730 and the gate electrode / drain electrode / source electrode of the TFT 740. A horizontal electric field is formed by the pixel electrode 730 and the counter electrode 750 for forming a horizontal electric field.

  Incidentally, the horizontal electric field forming counter electrode 750 is a counter electrode in the IPS system. In each of the first to seventh embodiments, the counter electrode on the counter substrate side in the vertical electric field system (TN system or VA system) ( This is different from the vertical electrode forming counter electrode).

  In the general IPS pixel configuration of FIG. 9, the transverse electric field forming counter electrode 750 is formed in parallel with the pixel electrode 730 at an appropriate interval.

The counter electrode bus lines 760 are respectively connected to the horizontal electric field forming counter electrodes 750 and arranged in parallel with the gate bus lines 710. The counter electrode bus line 760 is bundled outside the display area to form a counter electrode common electrode portion 770, and is extended to an external electrode portion to which a predetermined potential is separately applied. For this reason, the bundled counter electrode common electrode portions 770 intersect with the lead portions of the gate bus lines 710.

  The counter electrode common electrode portion 770 is stacked on each gate bus line 710 via an insulating film (not shown), and an opening 772 is formed in a region overlapping with each gate bus line 710. The opening 772 opens along the bent portion 711 of the gate bus line 710. Therefore, an overlapping portion 774 that overlaps with the gate bus line 710 is formed.

  In the array substrate 700 of the liquid crystal display device configured as described above, when static electricity E1 flows from the gate TAB terminal side of the gate bus line 710, an interlayer short circuit occurs between the common electrode portion 770 for the counter electrode and the gate bus line 710. Occurs at the short circuit location S. This is because one of the two overlapping portions 774 overlaps the gate bus line 710.

  And in the common electrode part 770 for counter electrodes, repair of an interlayer short circuit can be performed by carrying out laser cutting of the cutting positions C1 and C2 which are the both ends of the short circuit location S. Thereby, even if one superimposition part 774 is cut | disconnected, the conduction | electrical_connection path | route can be ensured by the other superimposition part 774. FIG. For this reason, the common electrode part 770 for counter electrodes can be repaired easily. At this time, it is not necessary to repair the gate bus line 710 by laser cutting or the like.

  As described above, according to the present embodiment, the configuration of the opening can be adopted not only for each common electrode of each embodiment but also for an IPS-type array substrate. It can also be used in the common wiring portion for the counter electrode that bundles the connected bus lines, and while having the same operational effects as the first embodiment, the IPS display substrate can be easily repaired. Yes.

[Various modifications]
Although the display device substrate and the liquid crystal display device using the same according to the present invention have been described according to some specific embodiments, various modifications can be made to each embodiment.

  For example, in each of the above embodiments, the gate bus line and the storage capacitor common electrode portion, the gate bus line and the common electrode portion for the counter electrode, and the gate bus line and the common electrode portion for electrostatic protection have been described. It goes without saying that the same method can be applied to the bus line and the storage capacitor common electrode part, the drain bus line and the common electrode part for the counter electrode, and the drain bus line and the common electrode part for electrostatic protection.

In the second embodiment, two openings are provided for each gate bus line. However, three or more openings may be provided. In this case, static electricity from the gate bus line flows from the external connection terminal side, but an interlayer short circuit is formed in the first overlapping portion between the first opening and the edge, and then the second opening and the second In some cases, the second overlapping portion between the first opening portion and the first overlapping portion may be sequentially generated. Even in such a case, even if the first overlapping portion and the second overlapping portion are laser-cut, the second opening portion and the third overlapping portion are formed. Since conduction can be ensured at the third overlapping portion between the opening and the fourth overlapping portion between the third opening and the other edge, the entire liquid crystal display panel can be repaired more easily. .

  Furthermore, in the first to sixth embodiments, the storage capacitor common electrode portion is disposed at both ends of the array substrate. However, the storage capacitor common electrode portion is disposed only at one end side. The case may be configured.

  The common electrode unit for bundling lines according to the configuration of the ESD of the seventh embodiment and the configuration of the IPS of the eighth embodiment is the common electrode according to any one of the first to sixth embodiments. Needless to say, the electrode portion may have a configuration (opening shape, bypass wiring, etc.).

  In addition to the configuration of the storage capacitor common electrode portion of the first to sixth embodiments, the array substrate may have a configuration in which an opening is provided in the electrostatic protection common electrode portion of the seventh embodiment. Furthermore, a configuration of an array substrate in which an electrostatic protection common electrode portion provided with the opening portion of the seventh embodiment is added to the storage capacitor common electrode portion where no opening portion is formed may be employed. In addition to the configuration of the storage capacitor common electrode portion of the first to sixth embodiments, the array substrate may have a configuration in which an opening is provided in the common electrode portion for the counter electrode of the eighth embodiment. . Furthermore, the configuration of the array substrate in which the common electrode portion for the counter electrode provided with the opening portion of the eighth embodiment is added to the storage capacitor common electrode portion where the opening portion is not formed may be employed.

  In addition to the configuration of the storage capacitor common electrode portion of the first to sixth embodiments, the array substrate includes an electrostatic protection common electrode portion having an opening portion of the seventh embodiment, and an eighth embodiment. The common electrode part for counter electrodes which has the opening part of the form may be provided. In this case, the configuration of the common electrode portion for electrostatic protection may adopt the configuration of the common electrode portion of each of the first to sixth embodiments, and the configuration of the common electrode portion for the counter electrode may be the first to You may employ | adopt the structure of the common electrode part of each 6th embodiment. Moreover, the structure which does not provide an opening in any one of a storage capacitor common electrode part, a common electrode part for electrostatic protection, and a common electrode part for a counter electrode may be used.

  Furthermore, the configuration of one common wiring portion on the side intersecting with the gate bus line is the same as that of any one of the first to sixth embodiments, and the other common on the side intersecting with the drain bus line is common. The configuration of the wiring section may be any of the configurations of the first to sixth embodiments. In addition to this case, the configuration of the ESD of the seventh embodiment, the configuration of arranging common electrodes for bundling the lines according to the configuration of the IPS of the eighth embodiment, and additionally the ESD configuration or the IPS configuration. An opening or a bypass wiring may be formed.

  In each of the above embodiments, an example in which a TAB terminal is configured as an external connection terminal has been disclosed. However, a COG (Chip On Glass) type configuration may be used. In this case, it is preferable that the IC chip connected to the external connection terminal is formed in advance in the same process as the array substrate at the manufacturing stage.

  Furthermore, it is preferable that a plurality of TCP (Tape Carrier Package) mounted with a driver IC for driving the gate bus line is mounted on the left side of the exposed frame region of the array substrate. Also, a plurality of TCPs mounted with driver ICs for driving the drain bus lines are preferably mounted on the upper side of the exposed area of the array substrate 1. The plurality of TCPs are connected to a peripheral circuit board (not shown).

  In addition, at the four corner ends of the array substrate, there are transfer formation regions electrically connected to the counter electrode for vertical electric field formed on the counter substrate side through the transfer portion when bonded to the counter substrate. It is preferable to arrange. At this time, in the transfer formation region, for example, it is preferable to form connection pads each including a lower electrode made of the same forming material as the storage capacitor bus line and an upper electrode made of the same forming material as the pixel electrode. . The connection pad is electrically connected to the storage capacitor common wiring portion, and the transfer formation region is at least one end portion of one side along the extending direction of the gate bus line of the array substrate, or at least near one pair of the array substrate. It is desirable to arrange in the vicinity. Further, a larger number of transfer formation regions may be arranged substantially evenly around the display region, for example.

  In addition, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, an active matrix liquid crystal display device using TFTs as switching elements has been described as an example. However, the present invention is not limited to this, and other display devices such as a diode element (MIM) are used. It can be applied to substrates for various display devices such as active matrix liquid crystal display devices using passive elements, passive liquid crystal display devices, EL (electroluminescence) display devices, and PDP (plasma display devices). is there.

  In addition, the above-described display device substrate may be used in various liquid crystal display devices. In this case, the liquid crystal display device includes a drive circuit and the like, and the drive circuit drives the liquid crystal display device. In addition to the gate line drive circuit and the drain line drive circuit, the power supply circuit and the display information processing circuit This includes an inspection circuit used for inspection after manufacturing. The display information processing circuit processes and outputs display information, and can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like.

  Furthermore, the above embodiment includes various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. That is, it goes without saying that examples include combinations of the above-described embodiments, or any one of them and any of the modifications. In this case, even if not specifically described in the present embodiment, the operational effects obvious from the respective configurations disclosed in the respective embodiments and modifications can of course be exhibited in the present example as well. . Moreover, the structure by which some structural requirements were deleted from all the structural requirements shown by embodiment may be sufficient.

  The above description discloses only one example of the embodiment of the present invention, and can be appropriately modified and / or changed within a predetermined range. However, each embodiment is illustrative. , Not limiting.

The display device substrates and the liquid crystal display devices using the same according to the first to eighth embodiments of the present invention described above can be summarized as follows.
(Appendix 1)
A first wiring portion that is drawn out from the inside of the display area on the substrate to the outside;
A second wiring portion formed so as to intersect the first wiring portion outside the display region via an insulating film;
An opening formed in a region overlapping with at least the first wiring portion formed in the second wiring portion and intersecting;
An overlapping portion that is formed at both ends of the opening and the first and second wiring portions overlap with each other through the insulating film;
A substrate for a display device, comprising:
(Appendix 2)
In the display device substrate according to attachment 1,
The display device substrate, wherein the opening is formed along a direction in which the first wiring portion extends.
(Appendix 3)
In the display device substrate according to attachment 1,
The display device substrate, wherein the opening is opened along a direction in which the second wiring portion extends.
(Appendix 4)
In the display device substrate according to appendix 2 or 3,
A plurality of the openings are formed. A substrate for a display device, wherein:
(Appendix 5)
In the display device substrate according to appendix 1 or 2,
A display device substrate, further comprising a third wiring portion formed across the opening and stacked with the second wiring portion and a second insulating film interposed therebetween.
(Appendix 6)
In the display device substrate according to attachment 5,
The display device substrate, wherein the third wiring portion has a connection portion electrically connected to the second wiring portion.
(Appendix 7)
In the display device substrate according to appendix 5 or 6,
A display device substrate, wherein a plurality of the third wiring portions are formed.
(Appendix 8)
In the display device substrate according to any one of appendices 1 to 7,
The display device substrate, wherein the second wiring portion includes a storage capacitor common electrode portion commonly connected to a plurality of storage capacitor elements formed in the display region.
(Appendix 9)
In the display device substrate according to any one of appendices 1 to 8,
A plurality of electrostatic protection units disposed on the substrate and connected to the respective bus lines constituting the first wiring unit;
The display device substrate, wherein the second wiring portion includes one electrostatic protection common wiring portion that is commonly connected to each of the plurality of electrostatic protection portions.
(Appendix 10)
In the display device substrate according to any one of appendices 1 to 9,
A counter electrode for forming a horizontal electric field, which is arranged to form a horizontal electric field with the pixel electrode in the display region, and is formed corresponding to the pixel electrode;
The display device substrate, wherein the second wiring portion includes one counter electrode common electrode portion that is connected in common to the plurality of lateral electric field forming counter electrodes.
(Appendix 11)
In a display device including a substrate having a plurality of bus lines,
A liquid crystal display device, wherein the display device substrate according to any one of appendices 1 to 10 is used as the substrate.

1, 100, 200, 300, 400, 500, 600, 700, 1001 Array substrate 1a End 1b End 2 Counter substrate 3 Display area 4 Gate TAB terminal 5 Drain TAB terminal 10, 110, 210, 310, 410, 510 , 610, 710,
1010 Gate bus line 11, 111, 211, 311, 411, 511, 611, 711 Bent part 20, 120, 220, 320, 420, 520, 620, 720,
1020 Drain bus line 30, 130, 230, 330, 430, 530, 630, 730, 1030 Pixel electrode 40, 140, 240, 340, 440, 540, 640, 740, 1040 TFT
42 Source electrode 50, 150, 250, 350, 450, 550, 1050 Storage capacitor element 60, 160, 260, 360, 560, 1060 Storage capacitor bus line 70, 170, 270, 370, 470, 1070 Storage capacitor common electrode section 72, 172, 174, 272, 372, 472, 572a, 572b, 672,
772 Opening part 380, 480, 580 Bypass wiring 382, 384, 482, 484, 582, 584 Connection part 620 Static electricity protection part 660 Static electricity protection bus line 670 Static electricity protection common electrode part 740 Horizontal electric field forming common electrode part 750 Common electrode Bus line 770 Common electrode for counter electrode S Short-circuited point

Claims (5)

A first wiring portion that is drawn out from the inside of the display area on the substrate to the outside;
A second wiring portion formed so as to intersect the first wiring portion outside the display region via an insulating film;
A rectangular opening formed in the second wiring portion and opened in a region overlapping with the first wiring portion;
The second wiring portion in either one of the two regions formed on both sides of the opening and where the first and second wiring portions overlap with each other through the insulating film is formed on the first wiring. An overlapping portion that can be cut on both outer sides of the overlapping portion along the extending direction of the wiring portion;
A horizontal electric field forming counter electrode disposed to form a horizontal electric field with the pixel electrode in the display region and formed corresponding to the pixel electrode;
The second wiring portion, viewed contains a single common electrode portion for a counter electrode in which a plurality of the transverse electric field forming counter electrode and each common connection,
The opening is long in the extending direction of the second wiring portion,
A plurality of the first wiring portions;
The display device substrate , wherein the opening section straddles a plurality of the first wiring sections . In the display device substrate according to claim 1 Symbol placement,
The display device substrate, wherein a plurality of the openings are formed in parallel. The display device substrate according to claim 1 or 2 ,
The display device substrate, wherein the second wiring portion includes a storage capacitor common electrode portion commonly connected to a plurality of storage capacitor elements formed in the display region. The display device substrate according to any one of claims 1 to 3 ,
A plurality of electrostatic protection units disposed on the substrate and connected to the respective bus lines constituting the first wiring unit;
The display device substrate, wherein the second wiring portion includes one electrostatic protection common wiring portion that is commonly connected to each of the plurality of electrostatic protection portions. In a display device including a substrate having a plurality of bus lines,
The substrate, a liquid crystal display device, characterized in that are used the display device substrate according to any one of claims 1 to 4.

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