KR20120026005A - Thin film transistor, method of manufacturing the same, and device having the thin film transistor - Google Patents

Abstract

PURPOSE: A thin film transistor, a method of manufacturing the same, and a device having the thin film transistor are provided to improve electric field effect mobility by increasing the density of a carrier without changing the composition ratio of a first region and the amount of oxygen deficit. CONSTITUTION: An active layer(12) consisting of an oxide semiconductor layer is formed on a substrate(11). The active layer comprises a first area(A1) and a second area(A2) comprising a well-shaped potential. A source electrode(13) and a drain electrode(14) are formed on the substrate while having the active layer between them. A gate insulating layer(15) is formed on the active layer. The gate electrode(16) is formed on the gate insulating layer.

Description

Thin film transistors, methods for manufacturing the same, and devices having the thin film transistors {THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND DEVICE HAVING THE THIN FILM TRANSISTOR}

The present invention relates to a thin film transistor having an oxide semiconductor film and a method of manufacturing the same. Moreover, this invention relates to apparatuses, such as a display apparatus, an imaging sensor, and an X-ray digital imaging apparatus using the thin film transistor.

Recently, research and development of thin film transistors using oxide semiconductor thin films of In—Ga—Zn—O based (IGZO) as channel layers have been actively conducted. The oxide thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light, and thus it is possible to form a flexible transparent thin film transistor on a substrate such as a plastic plate or a film.

Table 1 shows a comparison table of mobility of various transistor characteristics, process temperature and the like.

Conventional polysilicon thin film transistors can achieve a mobility of about 100 cm 2 / Vs, but since the process temperature is very high at 450 ° C. or higher, only substrates having high heat resistance can be formed, which is suitable for low cost, large area, and flexibility. Not. In addition, since the amorphous silicon thin film transistor can be formed at a relatively low temperature of about 300 ° C., the selectivity of the substrate is wider than that of polysilicon, but only mobility of about 1 cm 2 / Vs is obtained, which is not suitable for high precision display applications. On the other hand, since the organic thin film transistor can be formed at 100 ° C. or lower from the viewpoint of low temperature film formation, it is expected to be applied to a flexible display application using a plastic film substrate or the like having low heat resistance, and the mobility is the same as that of amorphous silicon. Only results of degree are obtained.

That is, it is difficult to realize a thin film transistor having a relatively low temperature of about 300 ° C. or less and having a high mobility of about 100 cm 2 / Vs or more.

As a method of improving the carrier mobility of a transistor, there has been proposed a HEMT (High Electron Mobility Transistor) structure in which heterogeneous semiconductors having different electron affinity are bonded to each other and a quantum well is used as a channel of the transistor. In oxide semiconductor thin film transistors, there is a literature report in which a HEMT structure device having ZnO sandwiched between ZnMgO is produced and a high mobility of 140 cm 2 / Vs is obtained (Non-Patent Document 1).

Moreover, in the thin film transistor using the IGZO-type oxide semiconductor thin film, the thin film transistor which uses an IGZO film | membrane in which physical quantity differs as a multilayered structure, and uses it as an active layer is proposed. In patent document 1, the active layer containing an amorphous oxide has a 2 layer structure containing a 1st area | region and the 2nd area | region which is closer to a gate insulating film than a 1st area | region, and the oxygen concentration of a 2nd area | region is 1st area | region The substrate has been described for a field effect transistor which is higher than the oxygen concentration of. By such a structure, since the electrical resistance of the active layer on the gate insulating film side becomes high, it has been described that a channel is formed inside the amorphous oxide, thereby reducing the leakage current.

In addition, Patent Document 2 proposes a thin film transistor having an IGZO-based oxide semiconductor thin film and an active layer having a multilayer structure of an a-Si thin film. By placing an a-Si film with a small energy band gap between IGZO films with a larger energy gap, carriers are concentrated in the a-Si portion of the center of the active layer in the direction of the layer thickness, so that the field effect mobility is conventional. There is a description that it rose compared with the membrane.

Patent Document 3 describes a field effect transistor using an amorphous oxide semiconductor having high field effect mobility and exhibiting a high ON / OFF ratio, wherein a Ga content between an active layer and a source / drain electrode is higher than a Ga content of an oxide of the active layer. The structure provided with the resistive layer containing an oxide is disclosed.

Japanese Laid-Open Patent Publication 2006-165529 Japanese Unexamined Patent Publication No. 2009-170905 Japanese Unexamined Patent Publication No. 2010-073881

 K. Koike et al., Applied Physics Letters, 87 (2005) 112 106

However, in patent document 1, it is not the design which supplies a carrier to a carrier traveling layer by the electron affinity difference of an active layer. Moreover, there is a description that it is possible to reduce the leakage current, but there is a problem that sufficient carrier density is not obtained, and as a result, sufficient mobility is not obtained.

In Non-Patent Document 1, in order to obtain high mobility, a heterostructure field effect transistor (HEMT) is produced by epitaxial growth by molecular beam epitaxy (MBE method), and the lattice mismatch between the substrate and the semiconductor film layer is very high. It needs to be small. Therefore, it is necessary to heat substrate temperature above 700 degreeC, and there exists a problem that the selectivity of a base material falls remarkably.

In patent document 2, since amorphous silicon which is about 1 order of mobility is used for the carrier traveling layer which is a quantum well part compared with an oxide semiconductor, sufficient mobility is not obtained. Moreover, the IGZO film which is an oxide semiconductor and the hetero semiconductor material of a-Si which is a non-oxide are bonded, and there exists a problem that a favorable bonding interface is not obtained.

In Patent Literature 3, it is proposed to insert a resistive layer between the electrode layer and the active layer as a means of improving the on / off ratio without inhibiting the carrier concentration of the IGZO film serving as the active layer, but the design by electron affinity is not considered. Since there is no sufficient inflow of carriers from the resistive layer to the active layer, there is a problem that field effect mobility exceeding the mobility of the conventional IGZO monolayer is not obtained.

This invention is made | formed in view of the said situation, The thin film transistor which can manufacture at low temperature (for example, 300 degrees C or less) about oxide semiconductor, especially IGZO-type oxide semiconductor, and shows the high field effect mobility, and its It is an object to provide a manufacturing method. Moreover, an object of this invention is to provide the apparatus provided with the thin film transistor which has high electron mobility in a channel layer.

The thin film transistor of the present invention is a thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,

The first layer having a first electron affinity, wherein the active layer is disposed on the gate electrode side via the gate insulating film, and a second electron affinity smaller than the first electron affinity, disposed on a side far from the gate electrode. A second region having:

In the film thickness direction of the active layer, a well type potential having the first region as the well layer, the second region and the gate insulating film as a barrier layer is formed.

The active layer is an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) (where a, b, and c are each a? 0, b? 0, and c? 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0.), b / (a + b) of the second region is greater than b / (a + b) of the first region. It is characterized by large.

The parameter of a semiconductor electronic structure is shown in FIG. The electron affinity (χ) means the energy required to give one electron, and in the case of a semiconductor, it refers to the energy difference from the lower end of the conductor (Ec) to the vacuum level (EVac). As shown in FIG. 1, the electron affinity can be determined from the difference between the ionization potential I and the band gap energy Eg. The ionization potential (I) can be obtained from the photoelectron spectroscopy measurement, and the band gap energy (Eg) can be obtained from the transmission spectrum measurement and the reflection spectrum measurement.

That is, in the thin film transistor of the present invention, an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) has its gate electrode side as shown in FIG. 2A. In the film thickness direction from the gate insulating film side in FIG. 2A, the first region A ₁ and the second region A ₂ are included, and the electron affinity χ ₁ of the first region A ₁ is defined as the first region A ₁ . By constructing a well type potential larger than the electron affinity (χ ₂ ) of the two regions, and making b / (a + b) of the second region larger than b / (a + b) of the first region, the first It is characterized by providing an electron affinity difference between the region A ₁ and the second region A ₂ .

In addition, a "region" shows the three-dimensional area | region (part) in a film thickness direction here. In addition, the 1st, 2nd area | region of an oxide semiconductor layer shall be comprised with the same kind of material. The same kind means that the element species constituting the film are the same, the cation composition ratio and the oxygen concentration being different, or that different elements are doped in a part of the constituent elements. For example, IGZO films having Ga / (In + Ga) different from each other are the same type, and are the same as the IGZO films in which Mg is doped in part of the IGZO film and Zn.

Region modulates b / (a + b) in (A _1, A ₂₎ by it is possible to impart a potential difference (the electron affinity difference), the respective inter-region. Further, by increasing the oxygen concentration in the region A _{1 than} the oxygen concentration in the region A ₂ , an additional electron affinity difference can be provided. In this invention, you may modulate b / (a + b) and oxygen concentration simultaneously.

Here, it is preferable that the electron affinity difference by modulating the cation composition ratio in the said 1st, 2nd area | region and / or oxygen concentration modulation is 0.17 eV or more and 1.3 eV or less, Furthermore, 1st, 2nd area | region It is preferable that the electron affinity difference in is 0.32 eV or more and 1.3 eV or less.

If the electron affinity difference of a 1st, 2nd area | region is 0.17 eV or more, carrier will flow efficiently from a 2nd area | region to a 1st area | region, and high carrier concentration and mobility can be obtained.

Moreover, in the thin film transistor of this invention, when the electron affinity difference increases, the quantity of carrier supplied to a 1st area | region increases, and the phenomenon that mobility increases is observed. The electron affinity difference of approximately 1.3 eV is obtained when modulating b / (a + b) to increase the electron affinity difference while fixing the Zn composition ratio among In, Ga, and Zn in the oxide semiconductor layer. In order to obtain the above electron affinity difference, for example, there is a method of greatly modulating the amount of Zn in the active layer. However, if the amount of Zn is greatly modulated, the amorphous structure in the oxide semiconductor layer becomes unstable, resulting in instability and nonuniformity of the TFT characteristics. In this regard, the electron affinity difference is preferably 1.3 eV or less.

In the thin film transistor of the present invention, the oxide semiconductor layer is preferably an amorphous film.

Whether or not the oxide semiconductor layer is amorphous can be confirmed by X-ray diffraction measurement. That is, when the clear peak which shows a crystal structure is not detected by X-ray diffraction measurement, it can be judged that the oxide semiconductor layer is amorphous.

In the thin film transistor of the present invention, an oxide semiconductor composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) is used as an active layer, and b / (a +) of the first region A ₁ is used. b) is preferably less than 0.5.

More preferably not less than, the first region _{(A 1) b / (a} + b) is less than 0.4, and the second area _{(A 2) b / (a} + b) is 0.6 is preferred.

In the thin film transistor of this invention, it is preferable that the said board | substrate has flexibility.

Examples of flexible substrates include saturated polyester / polyethylene terephthalate (PET) resin substrates, polyethylene naphthalate (PEN) resin substrates, crosslinked fumaric acid diester resin substrates, polycarbonate (PC) resin substrates, and polyether sulfones. (PES) resin substrate, polysulfone (PSF, PSU) resin substrate, polyarylate (PAR) resin substrate, cyclic polyolefin (COP, COC) resin substrate, cellulose resin substrate, polyimide (PI) resin substrate, poly Amideimide (PAI) resin substrate, maleimide-olefin resin substrate, polyamide (PA) resin substrate, acrylic resin substrate, fluorine resin substrate, epoxy resin substrate, silicone resin film substrate, polybenzazole resin substrate, episulfate Composite plastics with a substrate by a feed compound, a liquid crystal polymer (LCP) substrate, a cyanate resin substrate, an aromatic ether resin substrate, and silicon oxide particles Substrates made of composite plastic materials with nanoparticles such as substrates made of materials, metal nanoparticles, inorganic oxide nanoparticles and inorganic nitride nanoparticles, substrates made of composite plastic materials with metal- and inorganic-free nanofibers and microfibers, and carbon fibers , A substrate made of a composite plastic material with carbon nanotubes, a substrate made of a composite plastic material with glass peroxide, glass fibers, glass beads, a substrate made of a composite plastic material with clay minerals or particles having a mica-derived crystal structure A substrate made of a laminated plastic material having at least one bonding interface between the thin glass and the single organic material, an inorganic layer (for example, SiO ₂ , Al ₂ O ₃ , SiO _x N _y ) and an organic layer are alternately laminated Thus, the composite having a barrier performance having at least one bonding interface A substrate made of a material, a stainless steel substrate, a metal multilayer substrate in which stainless steels and dissimilar metals are laminated, an aluminum substrate, and an aluminum substrate having an oxide film formed thereon by performing an oxidation treatment (for example, anodizing treatment) on the surface. Etc. can be mentioned.

The manufacturing method of the 1st thin film transistor of this invention is a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate, The said active layer has the said gate at the said gate electrode side. An active layer comprising a first region having a first electron affinity disposed through an insulating film and a second region having a second electron affinity smaller than the first electron affinity disposed on a side far from the gate electrode, the active layer In the film thickness direction of a (In ₂ O ₃ )? B (Ga), as the active layer, a well type potential having the first region as the well layer, the second region and the gate insulating film as a barrier layer is formed. _An oxide semiconductor layer composed of ₂ O ₃ )? C (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0.) is formed by a sputtering method. Together,

In the film formation step, the first region is formed in the film formation chamber under a first oxygen partial pressure / argon partial pressure, and the inside of the film formation chamber is subjected to b / (a + b) of the first region under a second oxygen partial pressure / argon partial pressure. And forming the second region having a composition ratio of b / (a + b) larger than).

Here, it is preferable to make said 2nd oxygen partial pressure / argon partial pressure smaller than the said 1st oxygen partial pressure / argon partial pressure.

The manufacturing method of the 2nd thin film transistor of this invention is a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate, The said active layer has the said gate at the said gate electrode side. An active layer comprising a first region having a first electron affinity disposed through an insulating film and a second region having a second electron affinity smaller than the first electron affinity disposed on a side far from the gate electrode, the active layer In the film thickness direction of a (In ₂ O ₃ )? B (Ga), as the active layer, a well type potential having the first region as the well layer, the second region and the gate insulating film as a barrier layer is formed. _An oxide semiconductor layer composed of ₂ O ₃ )? C (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0.) is formed by a sputtering method. Together,

The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, wherein the first region is formed. And depositing oxygen-containing radicals on the film formation surface of the first region after the film formation of the region and / or the first region.

The manufacturing method of the 3rd thin film transistor of this invention is a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate, The said active layer has the said gate at the said gate electrode side. An active layer comprising a first region having a first electron affinity disposed through an insulating film and a second region having a second electron affinity smaller than the first electron affinity disposed on a side far from the gate electrode, the active layer In the film thickness direction of a (In ₂ O ₃ )? B (Ga), as the active layer, a well type potential having the first region as the well layer, the second region and the gate insulating film as a barrier layer is formed. _An oxide semiconductor layer composed of ₂ O ₃ )? C (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, c + a ≠ 0.) is formed by a sputtering method. Together,

The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, wherein the first region is formed. And during the film formation of the region and / or after the film formation of the first region, irradiating ultraviolet rays to the film forming surface of the first region in an ozone atmosphere.

Moreover, in the manufacturing method of the 1st thru | or 3rd thin film transistor of this invention, it is preferable that all the film-forming board | substrates are not exposed to air | atmosphere during the said film-forming process.

The display device of the present invention includes the thin film transistor of the present invention.

The image sensor of the present invention includes the thin film transistor of the present invention.

The X-ray sensor of the present invention includes the thin film transistor of the present invention.

The X-ray digital photographing apparatus of the present invention is characterized by comprising the X-ray sensor of the present invention.

In the thin film transistor of the present invention, the first region of the oxide semiconductor layer made of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) is in contact with a second region having a smaller electron affinity, The lower end of the conduction band of the first region forms a well type potential structure in which the second region and the gate insulating film are potential barriers. As a result, an electron carrier flows into a 1st area | region, and since a carrier density can be made high without changing the composition ratio and oxygen deficiency amount of a 1st area | region, it can be set as having high mobility.

In general, in an oxide semiconductor, in order to increase the carrier density, the amount of oxygen deficiency is increased. Excess oxygen deficiency simultaneously becomes a scatterer for the carrier, which causes a decrease in mobility. In the present invention, since the oxygen vacancies need not be increased in the first region serving as the well layer, the mobility caused by oxygen vacancies in the first region serving as the channel layer is reduced in addition to the increase of the carrier by the well type potential structure. Is suppressed, and further mobility can be improved.

In the thin film transistor of the present invention, since the oxide semiconductor layer made of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) is formed of the same material in the first and second regions, Compared with the case where the first region serving as the channel layer is in contact with the dissimilar material, the defect density at the interface can be reduced, and a thin film transistor excellent in uniformity, stability and reliability can be provided. At the same time, since the first region serving as the channel layer is not exposed to the outside air, deterioration of device characteristics depending on time and the environment in which the device is placed is reduced.

In the present invention, if the oxide semiconductor layer is an amorphous film, the film can be formed at a low temperature of 300 ° C. or lower, and thus is easily formed on a flexible resin substrate such as a plastic substrate. Therefore, application to a flexible display using a plastic substrate with a thin film transistor becomes easier. In addition, the amorphous film is easy to form a uniform film over a large area, and since there are no grain boundaries such as polycrystals, it is easy to suppress variations in device characteristics.

Since the display device of the present invention includes the thin film transistor of the present invention having high mobility, display with low power consumption and high quality can be realized.

Since the X-ray sensor of this invention is equipped with the thin film transistor of this invention excellent in reliability, S / N is high and high sensitivity characteristic can be implement | achieved.

Since the X-ray digital photographing apparatus of the present invention includes a transistor having a high mobility in the X-ray sensor, an image having a light weight and flexibility and a wide dynamic range can be obtained. Is preferred.

1 is a diagram for explaining parameters of a semiconductor electronic structure.
2A is a diagram showing a potential structure due to an electron affinity difference, and FIG. 2B is a diagram showing a band gap energy structure.
FIG. 3A is a top gate-top contact type, FIG. 3B is a top gate-bottom contact type, FIG. 3C is a bottom gate-top contact type, and FIG. 3D is a cross-sectional view schematically showing the configuration of a thin film transistor of bottom gate-bottom contact type. to be.
4 is a cross-sectional STEM image showing immediately after (A) lamination of the IGZO laminated film, (B) after 250 ° C. annealing, and (C) after 500 ° C. annealing.
5 shows Sample 1? A diagram showing a Tauc plot for 5.
FIG. 6 is a diagram showing the composition ratio dependence of the band gap energy guided from FIG. 5.
7 shows Sample 1? It is a figure which shows the excitation light energy and normalized photoelectron yield with respect to 5. FIG.
FIG. 8 is a diagram showing the composition dependence of the ionization potential obtained from FIG. 7.
9 is a diagram showing composition dependence of electron affinity.
10A shows Tauc plots for Samples 6, 7, and 10B.
FIG. 11 is a diagram showing the oxygen partial pressure / argon partial pressure dependency of the band gap energy guided from FIG. 10.
12A is a diagram showing excitation light energy and normalized electron yield for samples 6, 7, and 12B.
FIG. 13 is a diagram showing the oxygen partial pressure / argon partial pressure dependency of the ionization potential guided from FIG. 12.
It is a figure which shows oxygen partial pressure / argon partial pressure dependency of electron affinity.
15A is a diagram showing specific resistance, FIG. 15B is carrier density, and FIG. 15C is Ga / (In + Ga) dependency of mobility.
It is a schematic sectional drawing which shows a part of liquid crystal display device of embodiment.
17 is a schematic configuration diagram of electrical wiring of the liquid crystal display of FIG. 16.
18 is a schematic cross-sectional view showing a part of the organic EL display device of the embodiment.
19 is a schematic configuration diagram of electrical wiring of the organic EL display device of FIG. 18.
20 is a schematic cross-sectional view showing a portion of the X-ray sensor array of the embodiment.
FIG. 21 is a schematic configuration diagram of electrical wiring of the X-ray sensor array of FIG. 20.
22 is a diagram illustrating Vg-Id characteristics of the examples and the comparative examples.
FIG. 23 is a diagram showing potential depth Δχ dependence of mobility μ in Examples 1, 2, 3, and Comparative Example 1. FIG.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described with reference to drawings.

<Thin Film Transistor>

3A to 3D show the first? It is sectional drawing which shows typically the structure of the thin film transistors 1-4 of 4th Embodiment. 3a? In each of the thin film transistors of FIG. 3D, the same reference numerals are given to common elements.

In the thin film transistors 1 to 4 according to the embodiment of the present invention, the active layer 12, the source electrode 13, the drain electrode 14, the gate insulating film 15, on the substrate 11, has a gate electrode 16, and has a first and a second area (a _1, a ₂₎ to the active layer 12 is a film constituting the well-type potential in the thickness direction (?, see Fig. 3d Fig. 3a).

The active layer 12 consists of an oxide semiconductor layer (IGZO layer) represented by a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO), and the first region A ₁ has a well type potential a is (see Fig. 2a) wells additional first area having the electron affinity (χ ₁₎ is in the second area (a ₂₎ is the liquid disposed on the far side in the first region (a ₁₎ than the gate electrode 16 , The second electron affinity χ ₂ smaller than the first electron affinity χ ₁ , and the cation composition ratio b / (a + b) is larger than the first area.

In the thin film transistors 1 to 4 of the present invention, the first and second regions are successively formed, and layers other than oxide semiconductor layers such as electrode layers are not inserted between the first and second regions.

Region modulates b / (a + b) in (A _1, A ₂₎ by it is possible to impart a potential difference (the electron affinity difference), the respective inter-region. In addition, by making the oxygen concentration in the region A ₁ larger than the oxygen concentration in the region A ₂ , an additional electron affinity difference can be provided, and the carrier can be efficiently concentrated in the potential well. At the same time, by increasing the oxygen concentration in the region A ₁ , a decrease in mobility due to impurity scattering can be suppressed, and further mobility can be improved. In this invention, you may modulate b / (a + b) and oxygen concentration simultaneously.

The thin film transistor 1 of the first embodiment shown in FIG. 3A is a top gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 3B is a top gate-bottom contact type transistor. The thin film transistor 3 of the third embodiment shown in FIG. 3C is a bottom gate-top contact type transistor, and the thin film transistor 4 of the fourth embodiment shown in FIG. 3D is a bottom gate-bottom contact type. Of transistors.

3a? In the embodiment shown in FIG. 3D, the arrangement of the gate, source, and drain electrodes with respect to the active layer (IGZO layer) is different. The functions of the elements denoted by the same reference numerals are the same, and the same material can be adapted.

Hereinafter, each component is explained in full detail.

(Board)

There is no restriction | limiting in particular about the shape, structure, size, etc. of the board | substrate 11 for forming the thin film transistor 1, According to the objective, it can select suitably. The structure of the substrate may be a single layer structure or a laminated structure. As the board | substrate 11, the board | substrate which consists of inorganic materials, such as YSZ (yttrium stabilized zirconium) and glass, resin, a resin composite material, etc. can be used, for example. Especially, the board | substrate which consists of resin or a resin composite material is preferable at the point which is lightweight and has flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyether sulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, Fluorine resins such as polyamideimide, polyetherimide, polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ah Substrates made of synthetic resins such as ionomer resins, cyanate resins, crosslinked fumaric acid diesters, cyclic polyolefins, aromatic ethers, maleimide-olefins, celluloses, episulfide compounds, composite plastics of the aforementioned synthetic resins and silicon oxide particles Substrate made of material, imager A substrate made of a composite plastic material such as a synthetic resin or the like and a metal nanoparticle, an inorganic oxide nanoparticle or an inorganic nitride nanoparticle, a substrate made of a composite plastic material of the above-described synthetic resin and carbon fiber or a carbon nanotube, the synthesis described above Substrates made of a composite plastic material with a resin or glass peroxide, glass fibers or glass beads, a substrate made of a composite plastic material of a synthetic resin and particles having a clay mineral or mica-derived crystal structure, thin glass and the above-mentioned materials A laminated plastic substrate having at least one bonding interface between any one of the synthetic resins, and an inorganic layer and an organic layer (synthetic resin already described) are alternately laminated to constitute a composite material having a barrier performance having at least one bonding interface. Board, Stainless The aluminum substrate of the oxide film formation which improved the insulation of the surface by performing an oxidation process (for example, anodizing process) to a metal multilayer board | substrate which laminated | stacked a gas substrate or stainless steel and a dissimilar metal, or the surface can be used.

Moreover, as a resin substrate, what is excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low hygroscopicity, etc. is preferable. The resin substrate may be provided with a gas barrier layer for preventing the permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate, and the adhesion with the lower electrode.

Moreover, it is preferable that the thickness of a board | substrate is 50 micrometers or more and 500 micrometers or less. If the thickness of the substrate is 50 µm or more, the flatness of the substrate itself is further improved. If the thickness of the substrate is 500 µm or less, the flexibility of the substrate itself is further improved, and the use as the substrate for a flexible device becomes easier. Moreover, since the thickness which has sufficient flatness and crosslinkability differs according to the material which comprises a board | substrate, it is necessary to set the thickness according to a board | substrate material, but the range is generally 50 micrometers? It becomes the range of 500 micrometers.

(Active layer)

The active layer 12 is composed of an IGZO film, more specifically, a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO), and the first and second electron affinity (χ ₁ , χ ₂ ) a b of the first and second areas (a _1, a ₂₎ a first electron affinity, and a (χ ₁₎ large, is greater than the second electron affinity (χ ₂₎ in addition, the area (a ₂₎ each having / a + b is larger than b / (a + b) in the region A ₁ .

In order to form the well type potential in the stacking direction, the electron affinity difference of each region is given by modulating b / (a + b) between the regions. The difference between the potentials of the first region A ₁ and the second region A ₂ is that the potential of the well type is reduced by lowering the oxygen concentration of the second region A ₂ to the oxygen concentration of the first region A ₁ . The electron affinity difference which forms a can be provided. When each area | region is comprised by the common element composition ratio, the higher the oxygen concentration, the greater the electron affinity.

Here, it is preferable that the electron affinity difference by modulating b / (a + b) in the said 1st, 2nd area | region and oxygen concentration modulation is 0.17 eV or more and 1.3 eV or less, Furthermore, 1st, 2nd It is preferable that the electron affinity difference in a region is 0.32 eV or more and 1.3 eV or less.

If the electron affinity difference of a 1st, 2nd area | region is 0.17 eV or more, carrier will flow efficiently from a 2nd area | region to a 1st area | region, and high carrier concentration and high mobility can be obtained.

Moreover, in the thin film transistor of this invention, when the electron affinity difference increases, the quantity of carrier supplied to a 1st area | region increases, and the phenomenon that mobility increases is observed. When the affinity difference is increased by modulating b / (a + b) while the Zn composition ratio of In, Ga, and Zn in the oxide semiconductor layer is fixed, an electron affinity difference of approximately 1.3 eV is obtained at the maximum. In order to obtain the above electron affinity difference, for example, there is a method of greatly modulating the amount of Zn in the active layer. If the amount of Zn is greatly modulated, the amorphous structure in the oxide semiconductor layer becomes unstable, and the instability and nonuniformity of the TFT characteristics As a result, the electron affinity difference is preferably 1.3 eV or less.

Specifically, the control of the oxygen concentration is performed by forming a film under relatively low oxygen partial pressure when forming the second region, and by forming a film under relatively high oxygen partial pressure when forming the first region, or After the first region film formation, a treatment of irradiating with oxygen radicals and ozone can be performed to promote oxidation of the film to reduce the amount of oxygen vacancies in the first region.

Moreover, it is preferable to make the oxygen deficiency amount of a 1st area extremely small. In the case of using an oxide semiconductor layer as a channel layer in the related art, it is necessary to increase the carrier density to some extent in order to increase the mobility, thereby intentionally forming oxygen vacancies, that is, lowering the oxygen concentration. However, when there are many oxygen deficiencies, there exists a problem that oxygen defect itself becomes a scatterer with respect to a carrier, and causes the fall of mobility. In the present invention, since the carrier as the channel layer is supplied from the second region, even if the amount of oxygen vacancies in the first region is extremely small, sufficient carrier density and mobility accompanying it are obtained.

The transistor of the present invention, it is preferred to be smaller than b / (a + b) of the b / (a + b) of the first region (A ₁₎ of the oxide semiconductor layer, a second area (A ₂₎ . It is also, b / (a + b) is less than or equal to 0.5 of the first region (A ₁₎ is preferred. More preferably not less than, the first region and the _{(A 1) a / a +} b is 0.6 or more Further, the 2 b / a + b is 0.6 in the area (A ₂₎ is preferred.

By enlarging the difference between b / (a + b) of the first region and the second region, the energy difference at the lower end of the conduction band becomes large, and it is possible to efficiently localize the electron carrier to the first region.

Moreover, it is preferable that Zn / In + Ga (equivalent to 2c / (a + b) in the above-mentioned general formula) of the 1st area which comprises the active layer in this invention is 0.5 or more, and 2c / (of the 2nd area | region a + b) is preferably 0.5 or less. As 2c / (a + b) increases, the optical absorption edge shifts to the long wavelength side, and as 2 / (a + b) increases, the band gap narrows. Therefore, an energy difference at the bottom of the conduction band can be obtained by arranging an IGZO layer having a larger 2c / (a + b) in the first region and an IGZO layer having a smaller 2c / (a + b) in the second region. It is possible to localize the electron carrier to the first region. The method of controlling 2c / (a + b) can form a deeper well-potential structure by applying the difference of b / (a + b) to a film with a large difference, and of course b / (a + b) It is possible to use even when is the same in each area.

In addition, a deeper well-type potential structure can be obtained by doping a part of Zn of the oxide semiconductor layer made of IGZO with an element ion having a wider band gap. Specifically, it is possible to enlarge the band gap of the film by doping Mg. For example, a deeper well type potential structure can be formed by doping Mg only in the second region. In addition, only Do, Ga, and Zn can be formed by doping Mg in each region in a state where a difference is provided between b / (a + b) and 2c / (a + b) between the first region and the second region. Compared with the system which controlled the composition ratio, the entire band gap can be widened while maintaining the height of the well barrier.

Since the blue light emitting layer used for the organic EL exhibits broad light emission having a peak of about λ = 450 nm, if the optical band gap of the IGZO film is relatively narrow and has optical absorption in the region, the threshold shift of the transistor is The problem arises. Therefore, as a thin film transistor especially used for organic electroluminescent drive, it is preferable that the band gap of the material used for a channel layer is larger.

In IGZO, when b / (a + b) is made large, the optical absorption end is shifted to the short wavelength side, and the band gap is widened. At the same time, the electrical conductivity is lowered by the composition having a large b / (a + b). In other words, when the IGZO film having a large b / (a + b) is used alone in the thin film transistor, the transistor characteristics (specifically, mobility exceeding several tens to 100 cm 2 / Vs) cannot be obtained (Fig. 15C). Reference.). In the present invention, the IGZO layer (second region) having a wide band gap and large b / (a + b) is bonded to the IGZO layer (first region) having a relatively small bend gap and small b / (a + b). By using the structure, a well type potential formed of the gate insulating film and the active layer is formed, and it becomes possible to localize the carrier in the first region.

The carrier density of a 1st area | region can be arbitrarily controlled by 2nd oxygen deficiency amount control or cation dope. In order to increase the carrier density, the amount of oxygen deficiency in the second region may be increased or a material (for example, Ti, Zr, Hf, Ta, etc.) tending to become a relatively large valence cation may be doped. However, when doping cation having a large valence, since the number of constituent elements of the oxide semiconductor film increases, the carrier density is changed by the oxygen concentration (oxygen deficiency amount) in view of simplification and low cost of the film forming process. It is desirable to control.

In addition, since it is possible to form into a film at the temperature of 300 degrees C or less, it is preferable that an oxide semiconductor layer is amorphous. For example, an amorphous IGZO film can be formed at a substrate temperature of 200 deg.

The film thickness (total film thickness) of the total of the active layer 12 is 10? It is preferable that it is about 200 nm.

(Source? Drain Electrode)

The source electrode 13 and the drain electrode 14 are not particularly limited as long as they have high conductivity, and for example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al-Nd, tin oxide, and oxidation Metal oxide conductive films, such as zinc, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO), etc. can be used as a single layer or two or more laminated structures.

Both the source electrode 13 and the drain electrode 14 are, for example, a wet method such as a printing method and a coating method, a physical method such as a vacuum deposition method, a sputtering method and an ion plating method, and a chemical method such as CVD and plasma CVD methods. What is necessary is just to form into a film in accordance with the method selected suitably in consideration of aptitude with the material used in etc.

In the case where the source electrode 13 and the drain electrode 14 are formed of the above metals, the thickness is 10 nm or more and 1000 nm, considering the film forming property, the patterning property by the etching or the lift-off method, the conductivity, and the like. It is preferable to set it as the following, and it is more preferable to set it as 50 nm or more and 100 nm or less.

(Gate insulating film)

As the gate insulating film 15, preferably has a high insulating property, and for example, an insulating film, or these compounds such as _{SiO 2, SiN x, SiON,} Al 2 O 3, Y 2 O 3, Ta 2 O 5, HfO 2 Or an insulating film containing at least two.

The gate insulating film 15 is considered to be compatible with materials used in a wet method such as a printing method, a coating method, a physical method such as a vacuum deposition method, a sputtering method, an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method selected appropriately.

In addition, the gate insulating film 15 needs to have a sufficient thickness in order to lower the leakage current and improve the voltage resistance, while an excessively large thickness causes an increase in the driving voltage. Although the thickness of the gate insulating film 15 may vary with materials, it is 10 nm? 10 micrometers is preferable, and 50 nm? 1000 nm is more preferable, and 100 nm? 400 nm is particularly preferred.

(Gate electrode)

The gate electrode 16 is not particularly limited as long as it has high conductivity, and for example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al-Nd, tin oxide, zinc oxide, indium oxide, and oxidation Metal oxide conductive films, such as indium tin (ITO) and indium zinc oxide (IZO), etc. can be used as a single layer or a laminated structure of two or more layers.

The gate electrode 16 is, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as CVD or plasma CVD method. In consideration of the aptitude, the film may be formed according to a method selected appropriately.

In the case where the gate electrode 16 is formed of the metal, the thickness is preferably 10 nm or more and 1000 nm or less, considering the film forming property, the patterning property by the etching or the lift-off method, the conductivity, and the like. It is more preferable to set it as 50 nm or more and 200 nm or less.

(Method for Manufacturing Thin Film Transistor)

The manufacturing method of the top gate-top contact type thin film transistor 1 shown in FIG. 3A is demonstrated easily. The substrate 11 is prepared, and the active layer (IGZO film) 12 is formed on the substrate 11 by a film forming method such as a sputtering method in the order of the second region A ₂ and the first region A ₁ . We form. Subsequently, the active layer 12 is patterned. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed by photolithography on the remaining portion, and the pattern is formed by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixture of phosphoric acid, nitric acid, and acetic acid.

Next, a metal film for forming the source and drain electrodes 13 and 14 is formed on the active layer 12. Subsequently, the metal film is patterned into a predetermined shape by an etching or lift-off method to form the source electrode 13 and the drain electrode 14. At this time, it is preferable to simultaneously pattern the source and drain electrodes 13 and 14 and the wirings connected to these electrodes (not shown).

After the source and drain electrodes 13 and 14 and the wiring are formed, the gate insulating film 15 is formed. The gate insulating film 15 is patterned to a predetermined shape by photolithography and etching.

After the gate insulating film 15 is formed, the gate electrode 16 is formed. After the film formation, the electrode film is patterned into a predetermined shape by etching or lift-off to form the gate electrode 16. At this time, it is preferable to simultaneously pattern the gate wiring of the gate electrode 16.

According to the above procedure, the thin film transistor 1 shown in FIG. 3A can be manufactured.

(Film Formation Step of Active Layer)

Next, the formation process of an active layer is demonstrated in detail. The film thickness (total film thickness) of the total of the active layer 12 is 10? About 200 nm is preferable, and it is preferable that each area | region is formed continuously, without exposing to air | atmosphere. The film is continuously formed without being exposed to the atmosphere, and as a result, better transistor characteristics can be obtained. Moreover, since the number of film-forming processes can be reduced, manufacturing cost can also be reduced.

Here, a description will be given of the production of a bottom gate type thin film transistor as shown in FIGS. 3C and 3D. As described above, the film is formed in the order of the first region A ₁ and the second region A ₂ when the bottom gate type thin film transistor is manufactured. In the manufacture of the top gate thin film transistor, the active layer is formed in the order of the second region A ₂ and the first region A ₁ .

First, the first region A _{1 is} formed. Here, for example, an IGZO film having Ga / (In + Ga) = 0.25 and Zn / (In + Ga) = 0.5 is formed as the first region A ₁ so as to have a film thickness of 10 nm.

As a method of forming a film so as to have a composition ratio of the metal element as described above, a sputter film may be In, Ga, Zn, or a co-sputter using a combination of these oxides or targets of these complex oxides, or the metal element in the previously formed IGZO film. The sputter | spatter of the complex oxide target whose composition ratio of which is mentioned above may be sufficient. Although the board | substrate temperature in film-forming may be arbitrarily selected according to a board | substrate, when using a flexible board | substrate, it is preferable that board | substrate temperature is closer to room temperature.

In the case of increasing the carrier density of the first region, the oxygen partial pressure in the film formation chamber during film formation is relatively low, and the oxygen concentration in the film is lowered. For example, the oxygen partial pressure / argon partial pressure at the time of film-forming is set to 0.005. On the contrary, when the electron carrier density is lowered, the oxygen partial pressure in the deposition chamber at the time of film formation is relatively high (for example, the oxygen partial pressure / argon partial pressure at the time of film formation is set to 0.05), or oxygen radical during or after film formation. Is irradiated with ultraviolet rays to the film formation substrate surface in an ozone atmosphere to increase the oxygen concentration in the film.

Next, film formation of the second region is performed. The film formation in the second region may be a method of stopping film formation once after changing the oxygen partial pressure in the film formation chamber and the power applied to the target after film formation in the first region, and then restarting the film formation. The method of changing the partial pressure of oxygen and the electric power applied to a target quickly or gently may be sufficient. In addition, the target may be a method of changing the input power by using the target used for the first region film formation as it is, and power input to the target used for the first region film formation when switching the film formation from the first region to the second region. The method of applying power to different targets may be stopped, or a method of applying power to a plurality of targets in addition to the target used for film formation in the first region may be used.

Here, as the second region, for example, an IGZO film having a composition ratio of a metal element of Ga / (In + Ga) = 0.75 and Zn / (In + Ga) = 0.5 is formed so as to have a thickness of 30 nm.

Although the board | substrate temperature in film-forming may be arbitrarily selected according to a board | substrate, when using a flexible board | substrate, it is preferable that board | substrate temperature is closer to room temperature.

In the case of increasing the carrier density in the second region, the oxygen partial pressure in the film formation chamber during film formation is relatively low, and the oxygen concentration in the film is lowered. For example, the oxygen partial pressure / argon partial pressure at the time of film-forming is set to 0.005. On the contrary, when the electron carrier density is lowered, the oxygen partial pressure in the deposition chamber at the time of film formation is relatively high (for example, the oxygen partial pressure / argon partial pressure at the time of film formation is 0.05), or oxygen radicals are formed during or after film formation. The surface of the film formation substrate is irradiated with ultraviolet rays in an ozone atmosphere to increase the oxygen concentration in the film. In embodiment of this invention, it is more preferable that the oxygen concentration of a 1st area | region is higher than the oxygen concentration of a 2nd area.

In addition, in order to raise the oxygen concentration in a film | membrane by irradiation of an oxygen radical or ultraviolet irradiation in an ozone atmosphere, you may carry out in the film formation of a 1st area | region and a 2nd area | region, and after film-forming, and may carry out only after 2nd area | region film formation. do. Moreover, although the board | substrate temperature at the time of oxygen radical irradiation may be arbitrarily selected according to a board | substrate, when using a flexible board | substrate, it is preferable that board | substrate temperature is closer to room temperature.

In addition, annealing may be performed after the oxide semiconductor layer is formed. Although the atmosphere at the time of annealing can be arbitrarily selected according to a film | membrane, and annealing temperature may be arbitrarily selected according to a board | substrate, When using a flexible substrate, it is preferable to anneal at lower temperature (for example, 200 degrees C or less). On the other hand, when using the board | substrate which has high heat resistance, you may perform annealing treatment at high temperature near 500 degreeC.

4 is a cross-sectional STEM image of a laminated film obtained by laminating five layers of an IGZO film with Ga / (In + Ga) = 0.75 and an IGZO film with Ga / In + Ga) = 0.25, and FIG. 4A is immediately after lamination (annealed). Before the treatment), FIG. 4B shows that the annealing temperature was treated at 250 ° C., and FIG. 4C shows that the annealing temperature was treated at 500 ° C. FIG. It can be seen from FIG. 4 that the laminated structure is maintained even when annealed at 500 ° C.

In addition, the present inventors use an IGZO layer having a small energy gap as a well layer by changing the electron affinity with respect to the composition ratio and / or oxygen concentration of a cation, and making a well-type potential structure with respect to an IGZO layer. It was confirmed by performing the following experiment that it is possible to do.

The electron affinity χ is determined by the difference between the ionization potential I and the band gap energy Eg as described above. Band gap energy Eg can measure the reflectance transmittance of light, and can calculate it using a Tauc plot. Here, band gap energy Eg shall directly point to the value of transition. In addition, ionization potential (I) can be calculated | required from photoelectron spectroscopy measurement.

(Depending on cation composition ratio of electron affinity (χ))

Sample 1 with different cation composition ratio? 5 was produced and each said measurement was carried out and the dependence on the cation composition ratio of the electron affinity (χ) was investigated.

First, an IGZO membrane sample 1? 5 was produced. Sample 1 5 forms an IGZO film | membrane in which Ga / (In + Ga) differs as a cation composition ratio, respectively, on a board | substrate. Any sample also used a synthetic quartz glass substrate (manufactured by Cobarent Material, product number T-4040) as the substrate.

Sample 1 is formed by forming an IGZO film having Ga / (In + Ga) = 0 and Zn / (In + Ga) = 0.5 on a substrate so as to have a thickness of 100 nm. And an oxygen partial pressure / argon partial pressure of 0.01 at the time of film formation was performed by In ₂ O ₃ target, Ga ₂ O ₃ target and a ball sputtering (sputter-co) with the ZnO target. In addition, the substrate temperature at the time of film-forming was made into room temperature, and the pressure in the film-forming chamber at the time of film-forming always maintained 4.4 * 10 <^-1> Pa by automatically controlling the opening degree of an exhaust valve.

Sample 2 5 was produced in the same manufacturing procedure as Sample 1, except that the values of Ga / (In + Ga) were different. Sample 2 has Ga / (In + Ga) = 0.25, sample 3 has Ga / (In + Ga) = 0.5, sample 4 has Ga / (In + Ga) = 0.75, and sample 5 has Ga / (In + Ga) = 1.

Also, for each sample 1? Control of Ga / (In + Ga) and Zn / (In + Ga) of the 5 was performed by adjusting the power value is input to each target of _{In 2 O 3, Ga 2 O} 3, ZnO.

Each sample 1? 5 shows a Tauc plot obtained from the results of reflectance transmittance measurement. It can be seen that as the Ga / (In + Ga) increases, the band gap energy also increases.

FIG. 6 shows the band gap energy of each sample derived from the Tauc plot shown in FIG. 5. From these results, if Ga / (In + Ga) is increased from 0 to 1, the band gap energy is 1.2? It became clear that it was about 1.3 eV.

7 shows each sample 1? Excited light energy and normalized photoelectron yield by the photoelectron spectroscopy measurement with respect to 5 are shown. In the graph of FIG. 7, the excitation light energy of the rise of a curve, ie, the energy value starting photoelectron emission, means an ionization potential.

FIG. 8 shows each sample 1? It is a graph which shows the ionization potential of 5. It is apparent from Fig. 8 that the ionization potential is at a maximum value near 0.5 of Ga / (In + Ga), and that the ionization potential is decreasing as it is moved away from it.

From the difference between the band gap energy (Eg) and the ionization potential (I) obtained above, each sample 1? The electron affinity (χ) of 5 was calculated. Table 2 shown below lists the composition ratio, oxygen partial pressure / argon partial pressure, energy gap (Eg), ionization potential (I), and electron affinity (χ) of each sample.

Fig. 9 shows Ga / (In + Ga) dependence of electron affinity obtained from the above result. It can be seen that the electron affinity (χ) decreases as Ga / (In + Ga) takes a maximum value near 0.25 and moves away from it, and when Ga / (In + Ga) is increased from 0.25 to 1, the electron affinity 1.2? It can be seen that it is as small as 1.3 eV.

As mentioned above, it became clear that electron affinity can be changed by changing Ga / In + Ga. Therefore, in the oxide semiconductor layer made of IGZO, for example, when the oxygen concentration modulation of the regions A ₁ and A ₂ is not performed, the Ga / (In + Ga) of the region A ₁ is set to 0.25. By setting Ga / In + Ga of the region A ₂ to 0.75, it can be seen that a well structure having a potential difference of 0.48 eV of the regions A ₁ and A ₂ can be obtained.

(Dependence of Oxygen Concentration of Electron Affinity (χ))

Samples with different oxygen concentrations 6? 9 was produced and the dependence on the oxygen concentration of the electron affinity χ which performed the same measurement was investigated.

Sample 6 9 made the IGZO film | membrane the measurement object similarly to the above, and formed into a film on the same manufacturing procedure and the same board | substrate. Sample 6 had Ga / (tn + Ga) = 0.75 and Zn / (In + Ga) = 0.5, and the oxygen partial pressure / argon partial pressure = 0 at the time of film-forming. Sample 7 set oxygen partial pressure / argon partial pressure = 0.01 at the time of film-forming in sample 6. Sample 8 had Ga / (In + Ga) = 0.25, Zn / (In + Ga) = 0.5, and the oxygen partial pressure / argon partial pressure = 0 at the time of film-forming. In Sample 8, sample 9 had an oxygen partial pressure / argon partial pressure of 0.01 at the time of film formation. Table 3 shows the composition ratios of the production samples 6 to 9, oxygen partial pressure / argon partial pressure, energy gaps to be described later, and the like.

Each sample 6? 9, Tauc plots of the results of reflectance and transmittance measurements are shown in Figs. 10A and 10B. FIG. 10A is a Tauc plot for samples 6 and 7 with Ga / (In + Ga) of 0.75, and FIG. 10B is for samples 8, 9 with Ga / (In + Ga) of 0.25. In any case, even if the oxygen partial pressure / argon partial pressure at the time of film-forming is changed, it turns out that band gap energy Eg does not change significantly.

FIG. 11 plots the band gap energy of each sample derived from the Tauc plots shown in FIGS. 10A and 10B on the horizontal axis of oxygen partial pressure / argon partial pressure. From this result, it became clear that even if the oxygen partial pressure / argon partial pressure was changed, there was almost no change in the band gap energy.

FIG. 12A shows samples 6 and 7, FIG. 12B shows excitation light energy and normalized photoelectron yield by photoelectron spectroscopy measurements on samples 8 and 9, and FIG. 13 shows angles obtained from the graphs of FIGS. 12A and 12B. It shows the ionization potential of a sample. The results shown in FIG. 13 show that even when the values of Ga / (In + Ga) are different, the ionization potential increases as the oxygen partial pressure / argon partial pressure at the time of film formation increases.

From the difference between the band gap energy (Eg) and the ionization potential (I) obtained above, each sample 6? The electron affinity χ of 9 was determined (see Table 3).

Fig. 14 shows the oxygen partial pressure / argon partial pressure dependence of electron affinity at the time of film formation obtained from the above result. It became clear that electron affinity (χ) became larger as oxygen partial pressure / argon partial pressure at the time of film-forming increased. It was found that when the oxygen partial pressure / argon partial pressure at the time of film formation was increased from 0 to 0.01, the electron affinity increased by about 0.2 eV even in the case where the value of Ga / (In + Ga) was 0.75, 0.25.

As mentioned above, it became clear that the electron affinity can be changed by changing the oxygen partial pressure / argon partial pressure at the time of film-forming, More specifically, it is clear that the electron affinity can be enlarged by increasing oxygen partial pressure / argon partial pressure.

Accordingly, in the oxide semiconductor layer made of IGZO, for example, area (A _1), in addition to the electron affinity difference giving modulating b / (a + b) of the area (A _2), area (A ₁ ) by the oxygen partial pressure / argon partial pressure during the film formation, the area (a ₂₎ greater than the oxygen partial pressure / argon partial pressure during the film formation, it is possible to obtain a larger electron affinity difference.

In general, when the oxygen partial pressure / argon partial pressure at the time of film formation is large, the oxygen concentration in the film is high. On the contrary, when the oxygen partial pressure / argon partial pressure at the time of film formation is small, the oxygen concentration decreases. As it increases, it means that the electron affinity increases.

In this experiment, as a method of increasing the oxygen concentration in the film, a method of increasing the oxygen partial pressure / argon partial pressure at the time of film formation was employed, but ultraviolet rays were applied to the film forming surface in an ozone atmosphere in which oxygen radicals were irradiated onto the film forming surface. Even if a method such as irradiation is employed, the oxygen concentration in the film can be increased in the same manner.

The above-described modulation of Ga / (In + Ga) and the modulation of oxygen concentration in the film can be applied simultaneously. For example, the first region A ₁ is applied to Ga / (In + Ga) = 0.25. The composition ratio and the oxygen concentration in the film (high oxygen partial pressure / argon partial pressure = 0.01 at the time of film formation) were used as the IGZO film (sample 9 in Table 3), and the second region A ₂ was Ga / (In + Ga ) = 0.75 and the composition ratio between the IGZO membrane (Sample 6 in Table 3) having a low compositional ratio and a low oxygen concentration in the film (oxygen partial pressure / argon partial pressure at the time of film formation = 0). If only the modulation is performed, a deeper well barrier structure (electron affinity difference (Δχ) = 0.65) can be obtained.

Here, an experiment performed on the carrier concentration and the mobility in the IGZO film will be described. Carrier concentration and mobility can be calculated | required by the measurement of a hall effect and a specific resistance.

15A? Fig. 15C shows Ga / (In + Ga) dependence of specific resistance, carrier density, and mobility in IGZO films prepared by varying the oxygen partial pressure / argon partial pressure. In Fig. 15,? Is the oxygen partial pressure / argon partial pressure is 0.01, ■ is the oxygen partial pressure / argon partial pressure is 0.005, and ▲ is the data for the sample whose oxygen partial pressure / argon partial pressure is zero.

The sample provided for the measurement is produced by the same method as the above. Hall measurement apparatus (Toyo Technica make, Hall effect resistivity measuring apparatus Resitest 8300) was used for the measurement of a Hall effect and a specific resistance.

It can be seen from FIG. 15B) that the carrier density can be independently controlled by changing Ga / (In + Ga) or oxygen partial pressure / argon partial pressure. For example, by making Ga / (In + Ga) constant and changing only the oxygen partial pressure / argon partial pressure, it is possible to arbitrarily adjust only the carrier concentration in the film without changing the band gap of the film. However, when oxygen partial pressure / argon partial pressure is 0, by changing Ga / (In + Ga), carrier concentration can be controlled arbitrarily, but it turns out that mobility remains low as shown to FIG. 15C. have. From this result, it was found that the mobility obtained by simply increasing the oxygen deficiency amount to increase the carrier concentration cannot be obtained.

Next, the result of having compared the carrier concentration and mobility of IGZO monolayer film and laminated structure is demonstrated.

As a laminated structure, a 10 nm IGZO film having a composition ratio (0.25)-oxygen partial pressure / argon partial pressure (0.01) of sample 7 was formed on a substrate, and then the composition ratio (0.75)-oxygen partial pressure / argon partial pressure (0) of sample 6 was successively formed. ) Was fabricated to form a Hall element having a thickness of 50 nm.

As a single film, the Hall element of each single film of Sample 7 (IGZO-0.25-0.01) and Sample 6 (IGZO-0.75-0) was prepared, respectively.

Compared with the carrier concentration of the monolayers in each region, or compared with the carrier concentration values expected from the simple average when the monolayers were laminated, the carrier structure had increased carrier density and increased mobility. This means that a well potential is formed, and electrons move in the well layer.

The use of the thin film transistor of the present invention described above is not particularly limited, but for example, a display device as an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) It is suitable as a drive element in the present invention.

In addition, the electronic device of the present invention is a device such as a flexible display that can be produced by a low temperature process using a resin substrate, image sensors such as CCD (Charge Coupled Device), CM0S (Complementary Metal Oxide Semiconductor), various sensors such as X-ray sensors, It is used suitably as a drive element (drive circuit) in various electronic devices, such as MEMS (Micro Electro Mechanical System).

Both the display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics with low power consumption. In addition, "characteristic" here is a display characteristic in the case of a display apparatus, and a sensitivity characteristic in the case of a sensor.

<Liquid Crystal Display Device>

In FIG. 16, the schematic sectional drawing of the one part is shown about the liquid crystal display device of one Embodiment of the electro-optical device of this invention, and the schematic block diagram of the electrical wiring is shown in FIG.

As shown in FIG. 16, the liquid crystal display device 5 of this embodiment is the gate electrode 16 protected by the top gate type thin film transistor 1 and the passivation layer 54 of the transistor 1 shown to FIG. 3A. A liquid crystal layer 57 disposed between the pixel lower electrode 55 and the opposing upper electrode 56, and an RGB color filter 58 for generating a different color in correspondence with each pixel. It is the structure provided with the polarizing plates 59a and 59b on the color filter 58 of the board | substrate 11 side of 10), respectively.

In addition, as shown in FIG. 17, the liquid crystal display device 5 of the present embodiment includes a plurality of gate wirings 51 parallel to each other and a data wiring 52 parallel to each other that intersects the gate wirings 51. ). Here, the gate wiring 51 and the data wiring 52 are electrically insulated. The thin film transistor 1 is provided near the intersection of the gate wiring 51 and the data wiring 52.

The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 52. The drain electrode 14 of the thin film transistor 1 is connected to the pixel lower electrode 55 (with a conductor embedded in the contact hole 19) via a contact hole 19 formed in the gate insulating film 15. have. The pixel lower electrode 55 forms a capacitor 53 together with the grounded counter electrode 56.

In the liquid crystal device of the present embodiment shown in FIG. 16, it is assumed that a thin film transistor of a top gate type is provided, but the thin film transistor used in the liquid crystal device which is the display device of the present invention is not limited to the top gate type. May be a thin film transistor.

Since the thin film transistor of the present invention has high mobility, high-definition display such as high precision, high speed response, high contrast, and the like in a liquid crystal display device can be achieved, which is suitable for large screen. In addition, when the IGZO of the active layer is amorphous, variations in device characteristics can be suppressed, and excellent display quality without unevenness on a large screen is realized. In addition, since the characteristic shift is small, the gate voltage can be reduced, and further, power consumption of the display device can be reduced. In addition, according to the present invention, since a thin film transistor can be produced using an amorphous IGZO film capable of film formation at low temperature (for example, 200 ° C. or less) as a semiconductor layer, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to this invention, the flexible liquid crystal display device excellent in display quality can be provided.

<Organic EL display device>

18, the schematic sectional drawing of a part is shown about the organic electroluminescent display apparatus of the active matrix system of one Embodiment of the electro-optical device of this invention, and the schematic block diagram of an electrical wiring is shown in FIG.

There are two types of driving methods of the organic EL display device, a simple matrix method and an active matrix method. The simple matrix method has an advantage of being able to be manufactured at low cost. However, the number of scan lines is inversely proportional to the light emission time near the scan lines in that the pixels are emitted by selecting the scan lines one by one. Therefore, high precision and large screen are difficult. Since the active matrix method forms transistors and capacitors for each pixel, the manufacturing cost is high. However, the active matrix method is suitable for high precision and large screen because there is no problem that the number of scanning lines cannot be increased like the simple matrix method.

In the active matrix organic EL display device 6 of the present embodiment, the top gate thin film transistor 1 shown in FIG. 3A is used for driving on a substrate 60 provided with a passivation layer 61a. 1a) and an organic light emitting element 65 comprising an organic light emitting layer 64 sandwiched between the lower electrode 62 and the upper electrode 63 on the transistors 1a and 1b. The upper surface is also configured to be protected by the passivation layer 61b.

As shown in FIG. 19, the organic EL display device 7 according to the present embodiment includes a plurality of gate wirings 66 parallel to each other and a data wiring 67 parallel to each other crossing the gate wiring 66. ) And drive wirings 68. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16a of the switching thin film transistor 1b is connected to the gate wiring 66, and the source electrode 13b of the switching thin film transistor 1b is connected to the data wiring 67. The drain electrode 14b of the switching thin film transistor 1b is connected to the gate electrode 16a of the driving thin film transistor 1a, and the driving thin film transistor 1a is turned on by using the capacitor 69. Keep it in a state. The source electrode 13a of the driving thin film transistor 1a is connected to the drive wiring 68, and the drain electrode 14a is connected to the organic EL light emitting element 65.

In the organic EL device of the present embodiment shown in FIG. 18, it is assumed that the top gate type thin film transistors 1a and 1b are provided. The thin film transistor used in the organic EL device which is the display device of the present invention is a top gate. The bottom gate type thin film transistor is not limited to the type.

Since the thin film transistor of the present invention has high mobility, display of low power consumption and high quality is possible. In addition, according to the present invention, since a thin film transistor can be manufactured using an amorphous IGZO film capable of film formation at low temperature (for example, 200 ° C. or less) as a semiconductor layer, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to this invention, it is excellent in display quality and can provide a flexible organic electroluminescence display.

In addition, in the organic EL display device shown in FIG. 18, the upper electrode 63 may be a top emission type, or the bottom electrode 62 and the TFTs may be a bottom emission type by using each electrode of the TFT as a transparent electrode. do.

<X-ray sensor>

20, the schematic sectional drawing of the part is shown about the X-ray sensor which is one Embodiment of the sensor of this invention, and the schematic block diagram of the electrical wiring is shown in FIG.

20 is a schematic cross-sectional view showing an enlarged portion of the X-ray sensor array more specifically. The X-ray sensor 7 of the present embodiment includes the thin film transistor 1 and the capacitor 70 formed on the substrate, the charge collecting electrode 71 formed on the capacitor 70, and the X-ray conversion layer 72. And the upper electrode 73 are configured. The passivation film 75 is formed on the thin film transistor 1.

The capacitor 70 has a structure in which an insulating film 78 is disposed between the lower electrode 76 for capacitors and the upper electrode 77 for capacitors. The capacitor upper electrode 77 is one of the source electrode 13 and the drain electrode 14 of the thin film transistor 1 via the contact hole 79 formed in the insulating film 78 (drain electrode in FIG. 20). (14)).

The charge collection electrode 71 is formed on the capacitor upper electrode 77 in the capacitor 70 and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is formed to cover the capacitor 70 of the thin film transistor 1. The upper electrode 73 is formed on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

As shown in FIG. 21, the X-ray sensor 7 of the present embodiment includes a plurality of gate wires 81 parallel to each other and a plurality of data wires 82 parallel to each other that intersect with the gate wire 81. Equipped with. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. The thin film transistor 1 is provided near the intersection of the gate wiring 81 and the data wiring 82.

The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. The drain electrode 14 of the thin film transistor 1 is connected to an electrode 71 for charge collection, and furthermore, the electrode 71 for charge collection together with the grounded counter electrode 76 has a capacitor 70. It consists of.

In the X-ray sensor 7 of this structure, X-rays are irradiated from the upper side (upper electrode 73 side) in FIG. 21 to generate an X-ray conversion layer 72 and an electron-hole pair. By applying a high electric field to the X-ray conversion layer 72 by the upper electrode 73, the generated charge is accumulated in the capacitor 70, and is read out by sequentially scanning the thin film transistor 1.

Since the X-ray sensor of the present invention has a thin film transistor 1 having high on-current and excellent reliability, the S / N is high and the sensitivity characteristic is excellent. An image of the range is obtained. In particular, the X-ray digital photographing apparatus of the present invention is not only capable of shooting still images, but is preferably used in an X-ray digital photographing apparatus capable of performing single-vision perspective and still image shooting. Moreover, when IGZ0 of an active layer in a thin film transistor is amorphous, the image excellent in uniformity is obtained.

In addition, in the X-ray sensor of this embodiment shown in FIG. 20, the top gate type thin film transistor was provided, but the thin film transistor used by the sensor of this invention is not limited to a top gate type, but is a bottom gate type A thin film transistor may be sufficient.

Example 1

Example 1, 2, 3, and Comparative Examples 1 and 2 were produced about the bottom gate type thin film transistor, and the mobility was compared. Table 4 is a table showing oxygen partial pressure / argon partial pressure and mobility at the time of Ga / (In + Ga) film formation of each transistor.

&Lt; Example 1 >

A bottom gate and top contact thin film transistor were fabricated as Example 1. As the substrate, a heavily doped p-type silicon substrate (manufactured by Mitsubishi Material Corporation) having a SiO ₂ oxide film of 100 nm formed on the surface thereof was used. The oxide semiconductor layer is made of IGZO. First, a 5 nm sputter film is formed on the InGaZnO film having Ga / (In + Ga) = 0.25 and Zn / (In + Ga) = 0.5 as the first region (A ₁ ). the second area as _{(a 2), Ga / (} in + Ga) = 0.75, Zn / (in + Ga) = 0.5 was deposited in the sputtering 30 ㎚ IGZO film. The oxide semiconductor layer was formed continuously without being exposed to the atmosphere between the regions. Sputtering of each area was carried out by the In ₂ O ₃ target, Ga ₂ O ₃ target, sputtering ball (co-sputter) using a ZnO target. The film thickness of each region was adjusted by adjusting the film formation time. The detailed sputtering conditions of each area are as follows.

(Sputter condition of the first area A ₁ )

Attained vacuum degree; 6 × 10 ^-6 Pa

Deposition pressure; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.02

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 43.0: 38.0: 19.0

(Sputter condition of the second area A ₂ )

Attained vacuum degree; 6 × 10 ^-6 Pa

Deposition pressure; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.005

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 14.7: 67.8: 17.5

After lamination of the oxide semiconductor layer by sputtering, an ohmic contact made of Ti (10 nm) / Au (40 nm) was formed on the laminated film by a vacuum deposition method via a metal mask.

As a result, Example 1 of the bottom gate type thin film transistor 1 having a channel length of 180 μm and a channel width of 1 mm was obtained.

<Example 2>

The device configuration is the same as that in Example 1, and only the composition of the oxide semiconductor layer is different. First, as the first region (A ₁₎ As, Ga / (In + Ga) = 0.375, Zn / (In + Ga) = 0.5 the IGZO film after the film formation 5 ㎚ sputtering, a second area (A _2), Ga An IGZO film of / (In + Ga) = 0.625 and Zn / (In + Ga) = 0.5 was formed with a 30 nm sputter film. The oxide semiconductor layer was formed continuously without being exposed to the atmosphere between the regions. Sputtering of each area was carried out by the In ₂ O ₃ target, Ga ₂ O ₃ target, sputtering ball (co-sputter) using a ZnO target. The film thickness of each region was adjusted by adjusting the film formation time. The detailed sputtering conditions of each area are as follows.

(Sputter condition of the first area A ₁ )

Attained vacuum degree; 6 × 10 ^-6 Pa

Deposition pressure; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.02

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 39.5: 50.0: 18.0

(Sputter condition of the second area A ₂ )

Attained vacuum degree; 6 × 10 ^-6 GPa

Film formation tension; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.005

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 20.5: 61.0: 17.0

<Example 3>

The device configuration is the same as that in Example 1, and the composition of the oxide semiconductor layer and the oxygen concentration are different. First, as the first region (A ₁₎ As, Ga / (In + Ga) = 0.0, Zn / (In + Ga) = 0.5 the IGZO film after the film formation 5 ㎚ sputtering, a second area (A _2), Ga A 30 nm sputter film was formed into an IGZO film with / (In + Ga) = 1.0 and Zn / (In + Ga) = 0.5. The oxide semiconductor layer was formed continuously without being exposed to the atmosphere between the regions. Sputtering of each area was carried out by the In ₂ O ₃ target, Ga ₂ O ₃ target, sputtering ball (co-sputter) using a ZnO target. The film thickness of each region was adjusted by adjusting the film formation time. The detailed sputtering conditions of each area are as follows.

(Sputter condition of the first area A ₁ )

Attained vacuum degree; 6 × 10 ^-6 Pa

Deposition pressure; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.067

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 55.0: 0.0: 13.0

(Sputter condition of the second area A ₁ )

Attained vacuum degree; 6 × 10 ^-6 Pa

Deposition pressure; 4.4 × 10 ^-1 Pa

Film formation temperature; Room temperature

Oxygen partial pressure / argon partial pressure; 0.005

Input power ratio of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO targets; 0.0: 60.0: 15.0

Comparative Example 1

In the film formation of the oxide semiconductor of Example 1, only IGZO film is 45 nm formed under the conditions of the input power ratio of 31.5: 61.0: 20.0 and the oxygen partial pressure / argon partial pressure of 0.002 without performing composition in the layer thickness direction and oxygen modulation. In addition, the thin film transistor was produced in the same manner as in Example 1 as Comparative Example 1. This is a transistor having a conventional IGZO monolayer having a composition of In: Ga: Zn = 1: 1: 1 (Ga / (In + Ga) = 0.5) in an active layer, and a well type potential structure is not formed in the layer thickness direction. It is

Comparative Example 2

In the film formation of the oxide semiconductor layer of Example 1, a thin film transistor was produced in the same manner as in Example 1 except that the first region was formed and the second region was not formed. The comparative example 2 is a case where the 2nd area | region used as a carrier supply layer is not contained in a structure except that the well type potential structure is not formed in the layer thickness direction.

For Examples 1, 2, and 3 and Comparative Examples 1 and 2 described above, measurement of transistor characteristics (Vg-Id characteristics) and mobility (μ) were carried out using a semiconductor parameter analyzer 4156C (manufactured by Azirent Technologies). Was carried out. The measurement result was shown in FIG. In the measurement of the Vg-Id characteristic, the drain voltage Vd is fixed at 10 V, and the gate voltage Vg is set at -15 V? It changed by the range of + 15V, and implemented by measuring the drain current Id in each gate voltage Vg.

As shown in Table 4, in Examples 1, 2, and 3 having a well type potential structure, mobility of 20 cm 2 / Vs or more was obtained, and in Example 3, a high value of 57.4 cm 2 / Vs was obtained. lost. On the other hand, about the comparative example 1 which does not have composition and oxygen concentration modulation in the layer thickness direction, the mobility about 11 cm <2> / Vs which is an average value as a transistor of the conventional IGZO single film was obtained. In Comparative Example 2 in which the second region was not formed, the transistor was driven, but the mobility was significantly reduced compared to the laminated TFT element at 0.029 cm 2 / Vs. This means that in the comparative example 2 which does not have a carrier supply layer, since a 2nd area | region is a carrier supply layer, sufficient carrier concentration was not obtained.

23 shows the potential depth Δχ dependence of mobility μ in Examples 1, 2, 3, and Comparative Example 1. FIG. Δχ is calculated as an electron affinity difference due to oxygen concentration modulation is approximately 0.1 eV in addition to the modulation of b / (a + b). If the potential depth (Δχ) is increased, the mobility increases. From this figure, by setting Δχ = 0.17 eV or more, the mobility of 20 cm 2 / Vs or more, which is almost twice the mobility of the IGZO monolayer, is obtained, so that a low power consumption, high quality display device, a high sensitivity X-ray sensor, or the like can be provided. Become. Therefore, in the transistor of the present invention, the electron affinity difference between the first and second regions is preferably 0.17 eV or more.

1, 2, 3, 4 thin film transistor
11 boards
12 oxide semiconductor layer
13 source electrode
14 drain electrode
15 gate insulating film
16 gate electrode
First region of the A ₁ oxide semiconductor layer
Second region of the A ₂ oxide semiconductor layer

Claims (17)

A thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a substrate,
The first layer having a first electron affinity, wherein the active layer is disposed on the gate electrode side via the gate insulating film, and a second electron affinity smaller than the first electron affinity, disposed on a side far from the gate electrode. A second region having:
In the film thickness direction of the active layer, a well type potential having the first region as the well layer, the second region and the gate insulating film as a barrier layer is formed.
The active layer is an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO) (where a, b, and c are each a? 0, b? 0, and c? 0, also a + b ≠ 0, b + c ≠ 0, c + a ≠ 0.,
And b / (a + b) of the second region is larger than b / (a + b) of the first region. The method of claim 1,
The difference between the electron affinity of the first region and the electron affinity of the second region is 0.17 eV or more and 1.3 eV or less. The method of claim 2,
The difference between the electron affinity of the first region and the electron affinity of the second region is 0.32 eV or more and 1.3 eV or less. The method of claim 1,
And the oxide semiconductor layer is amorphous. The method of claim 1,
The oxide semiconductor layer of claim 1, wherein b / (a + b) of the first region is smaller than 0.5. The method of claim 5, wherein
In the oxide semiconductor layer, the thin film transistor wherein b / (a + b) of the first region is smaller than 0.4 and b / (a + b) of the second region is 0.6 or more. The method of claim 1,
The oxide semiconductor layer, wherein the oxygen concentration in the first region is greater than the oxygen concentration in the second region. The method of claim 1,
And the substrate has flexibility. As a manufacturing method of a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate,
The first layer having a first electron affinity, wherein the active layer is disposed on the gate electrode side via the gate insulating film, and a second electron affinity smaller than the first electron affinity, disposed on a side far from the gate electrode. And a second region having a film having a well type potential in which the first region is a well layer, the second region and the gate insulating film are barrier layers in the film thickness direction of the active layer. an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0.).
In the film formation step, the first region is formed in the film formation chamber under a first oxygen partial pressure / argon partial pressure, and the inside of the film formation chamber is subjected to b / (a + b) of the first region under a second oxygen partial pressure / argon partial pressure. And forming the second region having a composition ratio of b / (a + b) larger than). The method of claim 9,
The second oxygen partial pressure / argon partial pressure is made smaller than the first oxygen partial pressure / argon partial pressure. As a manufacturing method of a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate,
The first layer having a first electron affinity, wherein the active layer is disposed on the gate electrode side via the gate insulating film, and a second electron affinity smaller than the first electron affinity, disposed on a side far from the gate electrode. And a second region having a film having a well type potential in which the first region is a well layer, the second region and the gate insulating film are barrier layers in the film thickness direction of the active layer. an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0.).
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, wherein the first region is formed. And depositing an oxygen-containing radical on the film formation surface of the first region after the film formation of the region and / or the first region is formed. As a manufacturing method of a thin film transistor which has an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on a board | substrate,
The first layer having a first electron affinity, wherein the active layer is disposed on the gate electrode side via the gate insulating film, and a second electron affinity smaller than the first electron affinity, disposed on a side far from the gate electrode. And a second region having a film having a well type potential in which the first region is a well layer, the second region and the gate insulating film are barrier layers in the film thickness direction of the active layer. an oxide semiconductor layer composed of a (In ₂ O ₃ ) to b (Ga ₂ O ₃ ) to c (ZnO), where a, b, and c are each a ≥ 0, b ≥ 0, c ≥ 0, and a + b ≠ 0, b + c ≠ 0, and c + a ≠ 0.).
The film forming step includes the step of forming the first region and the second region having a composition ratio of b / (a + b) larger than b / (a + b) of the first region, wherein the first region is formed. And irradiating the film formation surface of the first region in an ozone atmosphere during the film formation of the region and / or after the deposition of the first region. The method according to any one of claims 9 to 12,
And a film forming substrate is not exposed to the atmosphere during the film forming process. The thin film transistor as described in any one of Claims 1-8 was provided. The display apparatus characterized by the above-mentioned. An image sensor comprising the thin film transistor according to any one of claims 1 to 8. An X-ray sensor comprising the thin film transistor according to any one of claims 1 to 8. An X-ray digital photographing apparatus comprising the X-ray sensor according to claim 16.

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