JP6016455B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor film. The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  A technique for forming a transistor (also referred to as a thin film transistor or a TFT) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image display device. Silicon-based semiconductors are widely known as semiconductors applicable to transistors.

  As another semiconductor, an oxide semiconductor has attracted attention. For example, a technique for manufacturing a transistor using a Zn—O-based oxide semiconductor or an In—Ga—Zn—O-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2). .

  Further, Non-Patent Document 1 discloses an oxide semiconductor transistor in which the resistivity of an oxide semiconductor in that portion is reduced to form a source region and a drain region by a self-alignment process in which an exposed oxide semiconductor is subjected to argon plasma treatment. Has been.

JP 2007-123861 A JP 2007-96055 A

S. Jeon et al. “180 nm Gate Length Amorphous InGaZnO Thin Film Transistor for High Density Image Sensor Application”, IEDM Tech. Dig. , P. 504, 2010.

  As the image display device becomes higher in definition and the scale of the integrated circuit is increased, high-speed driving of the circuit is required. The transistor has a higher on-characteristic (for example, on-current and field-effect mobility) and is suitable for high-speed operation of the circuit.

  However, if the parasitic resistance between the source electrode and the drain electrode is high, there is a problem that sufficiently high on-characteristics cannot be obtained.

  In the method disclosed in Non-Patent Document 1, the surface of the oxide semiconductor is exposed, and argon plasma treatment is performed, so that the oxide semiconductor in the portions to be the source region and the drain region is also etched at the same time. The region is thinned (see FIG. 8 of Non-Patent Document 1). As a result, the resistance of the source region and the drain region increases, and the probability of occurrence of defective products due to over-etching associated with the thinning increases.

  The present invention has been made under such a technical background. Therefore, one embodiment of the present invention is a semiconductor device in which parasitic resistance between a source electrode and a drain electrode is reduced and on-characteristics are improved. It is one of the issues to provide. Another object is to provide a highly reliable semiconductor device.

  In order to solve the above problems, the present invention has focused on a method for forming an oxide semiconductor film in which a channel is formed. For a conductive oxide film including an oxide semiconductor to which an impurity element is added, a semiconductor region is formed by replacing the impurity element in part of the oxide film with oxygen. Then, a low resistance region in which the impurity element in the oxide film is not replaced with oxygen may be used as a source region and a drain region, and a semiconductor region in which the impurity element is replaced with oxygen may be used as a channel formation region.

  That is, in the method for forming a semiconductor film of one embodiment of the present invention, an oxide layer including an oxide semiconductor to which an impurity element is added is formed over a formation surface, and a part of the top surface of the oxide layer is exposed. Forming a semiconductor region in part of the oxide layer by forming a protective layer over the oxide layer and subjecting the exposed region of the oxide layer to substitution treatment for replacing the impurity element with oxygen. Have

  By such a method, a semiconductor film in which a semiconductor region is formed in part of a low-resistance oxide layer can be formed. Further, since the low-resistance region is not thinned by using the method of one embodiment of the present invention, the resistance of the region can be sufficiently reduced.

  Such a semiconductor film can be applied as a resistance element using, for example, a high-resistance semiconductor region as a resistor in addition to a transistor. By changing the conditions for the replacement process for the semiconductor region, the resistivity value in the semiconductor region can be freely set. Further, since the parasitic resistance is extremely reduced by the low resistance region including the oxide semiconductor to which the impurity element is added, the deviation of the resistivity value from the design value can be suppressed.

  The impurity element in the method for forming a semiconductor film is preferably nitrogen.

  A thin film including an oxide semiconductor containing nitrogen can be used as a conductive film having extremely high conductivity. Further, a nitrogen atom is preferable because it has an atomic radius close to that of an oxygen atom and can be replaced with an oxygen atom relatively easily by a substitution treatment.

  In the method for forming a semiconductor film, it is preferable to perform at least one of oxygen radical treatment, oxygen ion implantation treatment, oxygen plasma treatment, and thermal oxidation treatment as the substitution treatment.

  The substitution of the impurity element can be performed by bringing high-energy oxygen into contact with the oxide layer. The above-described processing method is preferable because the above-described method can be applied without any special capital investment because of its high affinity with the conventional semiconductor process.

  Two or more of the above processing methods may be used. For example, by performing oxygen radical treatment and oxygen ion implantation treatment on an oxide layer to which an impurity element is added, uniform replacement can be performed from the surface layer to the lower layer of the oxide layer.

  In addition, in the method for manufacturing a semiconductor device of one embodiment of the present invention, an oxide layer including an oxide semiconductor to which an impurity element is added is formed over a formation surface and a part of the top surface of the oxide layer is exposed. Then, a protective layer is formed over the oxide layer, and the exposed region of the oxide layer is subjected to substitution treatment for replacing the impurity element with oxygen, so that the first low-resistance region and the first low-resistance region are formed in the oxide layer. A step of forming a semiconductor region sandwiched between the two low-resistance regions, a step of forming a gate insulating layer, and a step of forming a gate electrode layer. Further, the gate insulating layer and the semiconductor region are formed in contact with each other, the gate electrode layer and the gate insulating layer are formed in contact with each other, and the gate electrode layer and the semiconductor region are formed to overlap each other.

  With such a method, the contact resistance with the source electrode or the drain electrode can be sufficiently reduced by using the low resistance region sandwiching the semiconductor region as the source region or the drain region. Therefore, a semiconductor device in which the parasitic resistance between the source electrode and the drain electrode is reduced and the on-characteristic is improved can be manufactured.

  In another embodiment of the present invention, a method for manufacturing a semiconductor device includes forming an oxide layer including an oxide semiconductor to which an impurity element is added over a formation surface and exposing part of the top surface of the oxide layer. And forming a protective layer over the oxide layer, etching a part of the upper portion of the oxide layer in the exposed region, and substituting oxygen for the impurity element in the exposed region of the oxide layer. A process is performed to form a semiconductor region in part of the oxide layer, a step of forming a gate insulating layer, and a step of forming a gate electrode layer. Further, the gate insulating layer and the semiconductor region are formed in contact with each other, the gate electrode layer and the gate insulating layer are formed in contact with each other, and the gate electrode layer and the semiconductor region are formed to overlap each other.

  By such a method, since the thickness of the low resistance region can be formed thicker than that of the semiconductor region, the resistance of the region can be further reduced. In addition, since the semiconductor region can be thinned at the same time, the short channel effect can be effectively suppressed even when the semiconductor device is miniaturized.

  In addition, the impurity element in any of the above methods for manufacturing a semiconductor device is preferably nitrogen.

  Moreover, it is preferable to perform any one or more of oxygen radical treatment, oxygen ion implantation treatment, oxygen plasma treatment, and thermal oxidation treatment as the substitution treatment in any of the above semiconductor device manufacturing methods.

  The semiconductor device of one embodiment of the present invention includes a semiconductor region sandwiched between a first low-resistance region, a second low-resistance region, a first low-resistance region, and a second low-resistance region on the same surface. A gate electrode layer overlapping with the semiconductor region, and a gate insulating layer sandwiched between the semiconductor region and the gate electrode layer. In addition, the thickness of the semiconductor region is smaller than that of the first low resistance region and the second low resistance region, and the first low resistance region, the second low resistance region, and the semiconductor region are oxides containing an impurity element. The semiconductor region includes a semiconductor, and the semiconductor region has a higher oxygen content and a lower impurity element content than the first low resistance region and the second low resistance region.

  With such a configuration, the thickness of the low resistance region is thicker than that of the semiconductor region, so that the resistance of the region can be further reduced. At the same time, since the semiconductor region is thinned, the short channel effect can be effectively suppressed even when the semiconductor device is miniaturized. In addition, when the semiconductor region contains a sufficiently reduced amount of nitrogen, the on-current can be increased and a semiconductor device with improved on-characteristic can be obtained.

  In the semiconductor device, it is preferable that the semiconductor region is provided so as to continuously increase in thickness toward an end portion in contact with the first low resistance region or the second low resistance region.

  With such a structure, current density can be reduced at the end portion of the semiconductor region, so that heat generation at the boundary between the channel and the source or drain is suppressed, and a highly reliable semiconductor device can be obtained.

  In particular, in the case of a top-gate transistor, the coverage of the gate insulating layer is enhanced at the boundary between the semiconductor region and the low-resistance region having different thicknesses. Therefore, gate leakage and dielectric breakdown due to local thinning of the gate insulating layer. Such a problem is suppressed, and a highly reliable semiconductor device can be obtained.

  Further, the impurity element in any of the above semiconductor devices is preferably nitrogen.

  In particular, by using nitrogen as the impurity element, a low resistance region having high conductivity can be obtained.

  In addition, the oxide semiconductor in any of the above semiconductor devices is preferably an oxide containing indium, gallium, and zinc.

  In the case where such an oxide semiconductor is used for a semiconductor device such as a transistor, even if the oxide semiconductor is in an amorphous state formed at a relatively low temperature, it has better electrical characteristics than other oxide semiconductors ( High field effect mobility, small S value, etc.) and high reliability are preferable. Here, for example, zinc oxide, which is one of oxide semiconductors, tends to be in a polycrystalline state at a low temperature, and it is difficult to obtain desired electric characteristics such as field effect mobility and S value due to the crystal grain boundary.

  According to the present invention, it is possible to provide a semiconductor device in which the parasitic resistance between the source electrode and the drain electrode is reduced and the on-characteristic is improved. In addition, a highly reliable semiconductor device can be provided.

6A and 6B illustrate a structure example of a semiconductor device according to one embodiment of the present invention. 4A to 4D illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate a structure example of a semiconductor device according to one embodiment of the present invention. 4A to 4D illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate a structure example of a semiconductor device according to one embodiment of the present invention. 4A to 4D illustrate an example of a manufacturing process of a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate a structure example of a semiconductor device according to one embodiment of the present invention. 6A and 6B illustrate a structure example of a semiconductor device according to one embodiment of the present invention. 3A and 3B each illustrate a structure example of a resistance element of one embodiment of the present invention. 3A and 3B each illustrate a structure example of a resistance element of one embodiment of the present invention. FIG. 10 illustrates a configuration example of a CPU of one embodiment of the present invention. 6A and 6B illustrate a structure example of an electronic device according to one embodiment of the present invention. 6A and 6B illustrate a structure example of an electronic device according to one embodiment of the present invention. The measurement result of sheet resistance concerning an example. The cross-sectional observation image concerning an Example. The cross-sectional observation image concerning an Example. The measurement result of the EDX analysis concerning an Example. The measurement result of the XPS analysis concerning an Example.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

  Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

  A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

  In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed, or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “things having some electric action” include electrodes, wirings, switching elements such as transistors, resistance elements, coils, capacitive elements, and other elements having various functions.

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. In this embodiment, a structural example and a manufacturing method of a transistor will be described as an example of a semiconductor device.

<Configuration example>
1A is a schematic top view of a transistor 100 exemplified in this structural example, and FIG. 1B is a schematic cross-sectional view taken along a cutting line AB in FIG. 1A. Note that some components (such as the protective layer 109 and the gate insulating layer 111) are not illustrated in FIG. 1A for clarity.

  The transistor 100 formed over the substrate 101 includes an oxide layer 103 including a low resistance region 105a, a low resistance region 105b, and a semiconductor region 107, a protective layer 109 that covers the low resistance region 105a and the low resistance region 105b, and at least A gate insulating layer 111 in contact with the upper surface of the semiconductor region 107; a gate electrode layer 113 in contact with the upper surface of the gate insulating layer 111 and overlapping the semiconductor region 107; an insulating layer 117 covering the oxide layer 103 and the gate electrode layer 113; A source electrode layer 115a and a drain electrode layer 115b which are electrically connected to the low resistance region 105a or the low resistance region 105b through openings provided in the insulating layer 117, respectively.

  The oxide layer 103 includes an oxide semiconductor to which an impurity element is added.

  The low resistance region 105 a and the low resistance region 105 b are regions that have been sufficiently reduced in resistance by the impurity element, and form the source region or the drain region of the transistor 100. Therefore, the parasitic resistance between the source electrode layer 115a and the drain electrode layer 115b is sufficiently reduced.

  The semiconductor region 107 includes a region where a channel of the transistor 100 is formed, and has a higher oxygen content and a lower content of the impurity element than the low resistance region 105a and the low resistance region 105b.

  It is preferable that the semiconductor region 107 contain the impurity element in a sufficiently reduced amount because the on characteristics (such as field-effect mobility and on-state current) of the transistor 100 are improved.

  Further, since the semiconductor region 107 contains the same trace amount of impurity elements as the low resistance region 105a and the low resistance region 105b, a Schottky barrier at the boundary between the semiconductor region 107 and the low resistance region 105a or the low resistance region 105b. Therefore, parasitic resistance between the source electrode layer 115a and the drain electrode layer 115b can be reduced.

  The gate electrode layer 113 may be provided so as to overlap with at least part of the semiconductor region 107, but by providing the gate electrode layer 113 so as to overlap with the entire semiconductor region 107 as illustrated in FIG. Since a region where the gate electrode is not formed (also referred to as a Loff region) can be eliminated, the on-state current of the transistor 100 can be increased.

  A protective layer 109 is formed in a region where the gate electrode layer 113 and the low resistance region 105a or the low resistance region 105b overlap. Since the protective layer 109 can reduce parasitic capacitance between the gate electrode layer 113 and the low resistance region 105a or the low resistance region 105b, the transistor 100 that can be driven with low power consumption can be realized. Further, by providing the protective layer 109, the gate insulating layer 111 can be thinned while reducing the parasitic capacitance. By reducing the thickness of the gate insulating layer 111, the on characteristics can be further improved.

  Note that although one gate electrode layer 113 is provided above the semiconductor region 107 in the above description, it functions as a second gate insulating layer closer to the substrate 101 than the semiconductor region 107 as shown in FIG. The second gate electrode layer 116 may be provided with the insulating layer 118 provided therebetween. By applying an appropriate potential to one of the gates, the threshold voltage of the transistor can be freely set. For example, a normally-off transistor can be reliably realized by applying a potential for turning off the transistor to one gate.

  At this time, the surface of the insulating layer 118 covering the second gate electrode layer 116 is flattened so that a step formed by reflecting the thickness of the second gate electrode layer 116 is eliminated. It is preferable that For example, the surface of the insulating layer 118 may be subjected to a planarization process such as a polishing process such as a CMP method, a dry etching process, or a plasma process.

  The transistor 100 illustrated in this structural example is a transistor in which the parasitic resistance between the source electrode layer 115a and the drain electrode layer 115b is reduced and the on-state characteristics are improved.

<Example of production method>
Hereinafter, an example of a method for manufacturing the transistor 100 will be described. FIG. 2 is a schematic cross-sectional view according to the method for manufacturing the transistor exemplified in this embodiment.

  First, the insulating layer 119 is formed over the substrate 101.

  There is no particular limitation on a substrate that can be used as the substrate 101 having an insulating surface as long as it has at least heat resistance to withstand heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, It may be used as the substrate 101.

  Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 101. In order to manufacture a flexible semiconductor device, the transistor 100 may be directly formed over a flexible substrate, or the transistor 100 is manufactured over another manufacturing substrate and then transferred to the flexible substrate. Also good. Note that a separation layer may be provided between the formation substrate and the transistor 100 in order to separate the transistor 100 from the formation substrate and transfer it to the flexible substrate.

  The insulating layer 119 functions as a protective film for preventing impurities contained in the substrate 101 from diffusing into the transistor 100. The insulating layer 119 can be formed by a plasma CVD method, a sputtering method, or the like. Silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide , Gallium oxide, or a film containing a mixed material thereof can be a single layer or a stacked structure. Note that the insulating layer 119 is preferably formed as a single layer or a stacked structure including an oxide insulating layer so that the oxide insulating layer is in contact with the oxide layer 103 to be formed later. Note that the insulating layer 119 is not necessarily provided.

  It is preferable that the insulating layer 119 have an oxygen-excess region because excess oxygen contained in the insulating layer 119 can fill oxygen vacancies in a channel formation region of the semiconductor region 107 to be formed later. In the case where the insulating layer 119 has a stacked structure, it is preferable that at least a layer in contact with the oxide layer 103 (preferably an oxide insulating layer) include an oxygen-excess region. In order to provide the oxygen-excess region in the insulating layer 119, for example, the insulating layer 119 may be formed in an oxygen atmosphere. Alternatively, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be introduced into the insulating layer 119 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method (also referred to as an ion doping method or an ion implantation method), plasma treatment, or the like can be used.

  The insulating layer 119 preferably includes a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film in contact with the lower side of the layer having an oxygen-excess region. When the insulating layer 119 includes a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film, diffusion of impurities into the transistor 100 can be prevented.

  Planarization treatment may be performed on a region where the oxide layer 103 is formed in contact with the insulating layer 119. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

  As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the insulating layer 119 can be removed.

  As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case of performing the combination, the order of the steps is not particularly limited, and may be set as appropriate in accordance with the uneven state of the surface of the insulating layer 119.

  Further, hydrogen (including water and hydroxyl groups) is removed (dehydrated or dehydrated) from the insulating layer 119 so that impurities such as hydrogen (including water and hydroxyl groups) are reduced and oxygen is excessive. Heat treatment (dehydration or dehydrogenation treatment) and / or oxygen doping treatment may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be repeated.

  Next, a conductive oxide film including an oxide semiconductor to which an impurity element is added is formed over the insulating layer 119, and the oxide film is processed into an island shape to form the oxide layer 103 (FIG. 2 (A)).

  As a method for forming the oxide film, a sputtering method, an MBE (Molecular Beam Epitaxy) method, a plasma CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method, or the like can be used as appropriate. A sputtering method is preferably used.

  The oxide film is formed in an atmosphere containing an impurity element to be added, preferably in an atmosphere containing an impurity element and oxygen. By forming a film in an atmosphere containing an impurity element, the impurity element can be uniformly added to the formed film.

  In addition, in the case where a film is formed by a sputtering method, an oxide film including an oxide semiconductor to which an impurity element is added is formed by using a target including an impurity element in addition to the above. Also good. Alternatively, an oxide film may be formed by using two targets, a target including an oxide semiconductor and a target including an impurity element, and forming the targets simultaneously or alternately from the two targets.

  An oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. Further, as a stabilizer for reducing variation in electrical characteristics of the transistor 100, in addition to them, at least one of gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr), and aluminum (Al) is used. It is preferable to have.

  Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

  For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide Oxides, Sn—Mg oxides, In—Mg oxides, In—Ga oxides, In—Ga—Zn oxides (also referred to as IGZO) which are oxides of ternary metals, In -Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide Oxide, In-Zr-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In- Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn Oxide, In—Lu—Zn oxide, In—Sn—Ga—Zn oxide, In—Hf—Ga—Zn oxide, In—Al—Ga— which is an oxide of a quaternary metal It is formed by a sputtering method or the like using a target such as a Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, or In-Hf-Al-Zn-based oxide. Can do. Note that the above oxide semiconductor can be formed by a vacuum evaporation method, a pulse laser deposition method, a CVD method, or the like without being limited to the sputtering method.

  Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. M represents one or more metal elements of Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

  For example, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 2: 2: 1, or In: Ga: Zn = 3: 1: 2 atomic ratio In—Ga—Zn-based oxidation Or an oxide in the vicinity of the composition can be used. Alternatively, In: Sn: Zn = 1: 1: 1, In: Sn: Zn = 2: 1: 3, or In: Sn: Zn = 2: 1: 5 atomic ratio In—Sn—Zn-based oxide Or an oxide in the vicinity of the composition may be used.

  The oxide semiconductor containing indium is not limited to these compositions, and an oxide semiconductor having an appropriate composition may be used depending on required electrical characteristics (field-effect mobility, threshold value, variation, and the like). In order to obtain necessary electrical characteristics, it is preferable that the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, and the like are appropriate.

  For example, in a transistor including an In—Sn—Zn-based oxide semiconductor, high field effect mobility can be obtained relatively easily. However, even in a transistor including an In—Ga—Zn-based oxide semiconductor, field-effect mobility can be increased by reducing the defect density in the bulk.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C, (A + B + C = 1) is the vicinity of r of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ It refers to meet the r ^2. For example, r may be 0.05. The same applies to other oxides.

  In this embodiment, the oxide film has a single-layer structure. Note that the oxide film may have a structure in which a plurality of oxide films including an oxide semiconductor to which an impurity is added are stacked. For example, the oxide film may be a stack of a first oxide film and a second oxide film, and metal oxides having different compositions may be used for the first oxide film and the second oxide film. . For example, a ternary metal oxide may be used for the first oxide film, and a binary metal oxide may be used for the second oxide film. For example, both the first oxide film and the second oxide film may be ternary metal oxides.

  In addition, the constituent elements of the first oxide film and the second oxide film may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide film may be In: Ga: Zn = 1: 1: 1 and the atomic ratio of the second oxide film may be In: Ga: Zn = 3: 1: 2. Good. Alternatively, the atomic ratio of the first oxide film may be In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide film may be In: Ga: Zn = 2: 1: 3. Good.

  At this time, it is preferable that the In and Ga contents of the oxide film on the side close to the gate electrode (channel side) of the first oxide film and the second oxide film satisfy In> Ga. The content ratio of In and Ga in the oxide film far from the gate electrode (back channel side) is preferably In ≦ Ga.

  In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

  By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

  Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide film and the second oxide film. That is, a structure in which a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, or an amorphous oxide semiconductor is appropriately combined may be used. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide film and the second oxide film, internal stress of the oxide film or external stress is relieved and transistor characteristics vary. And the reliability of the transistor can be further improved.

  As an impurity element added to the oxide semiconductor, for example, phosphorus (P), arsenic (As), antimony (Sb), boron (B), aluminum (Al), tungsten (W), molybdenum (Mo), nitrogen ( One or more selected from N), fluorine (F), chlorine (Cl), titanium (Ti), carbon (C), and zinc (Zn) can be used.

  Further, nitrogen is preferably used as the impurity element. Nitrogen has an atomic radius close to that of oxygen and can be easily replaced with the site of an oxygen atom in the oxide semiconductor, so that the crystal structure is maintained without breaking the bond in the oxide semiconductor (if it has crystallinity) An oxide film with low resistance can be obtained. Further, since nitrogen can be easily replaced with oxygen by a subsequent replacement treatment, the impurity element concentration in the semiconductor region 107 can be sufficiently reduced, and the transistor 100 can obtain favorable electrical characteristics.

  When forming the oxide film, the film is formed in a gas atmosphere containing the above-described elements. Alternatively, a film is formed by a sputtering method using a target containing the above-described element.

  Oxygen vacancies are generated in the oxide semiconductor to which the impurity element is added. In the oxide semiconductor, oxygen vacancies serve as donors and generate electrons which are carriers in the oxide semiconductor. Thus, an oxide film into which an impurity element for generating oxygen vacancies in the oxide semiconductor is introduced has lower resistance than an oxide semiconductor to which the impurity element is not added, and the source region of the transistor 100 or It functions as a drain region.

  The concentration of the impurity element in the oxide film may be set as appropriate depending on the type of impurity element used and the resistivity of the target oxide film. For example, in the case where nitrogen is used as the impurity element, the concentration of nitrogen contained in the oxide film is 0.1 atomic% or more and 30 atomic% or less, more preferably 1 atomic% or more and 20 atomic% or less. When the concentration of nitrogen contained in the oxide film is lower than 0.1 atomic%, the carrier density is insufficient. When the concentration of nitrogen contained in the oxide film is higher than 30 atomic%, the substitution process of nitrogen and oxygen is performed later. The replacement may be insufficient, and the function of the semiconductor region 107 as a semiconductor may be impaired.

  As another method for forming an oxide film, after forming a semiconductor film containing an oxide semiconductor, the above-described impurity element can be introduced to form an oxide film.

  As one method for introducing an impurity element into the semiconductor film, an ion implantation method can be used. In addition, the impurity element is introduced into the semiconductor film by a process of exposing the surface of the semiconductor film to plasma in an atmosphere containing the impurity element (plasma process) or a process of exposing the surface of the semiconductor film to a radical of the impurity element (radical process). May be.

  Further, after introducing the impurity element into the semiconductor film, heat treatment for diffusing the impurity element into the semiconductor film may be performed. By the heat treatment, impurity elements are uniformly distributed in the film, and variation in resistance of the formed oxide film can be reduced.

  In this embodiment, the oxide film is formed by a sputtering method in a reduced-pressure atmosphere using an In—Ga—Zn-based oxide as a target and nitrogen gas as a deposition gas.

In addition, the hydrogen concentration of the formed oxide film can be reduced by introducing a sputtering gas from which hydrogen and moisture are removed while removing residual moisture in the deposition chamber. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, a turbo molecular pump provided with a cold trap may be used. A film formation chamber evacuated using a cryopump has a high exhaust capability of, for example, a compound containing hydrogen atoms such as hydrogen molecules and water (H ₂ O), and thus is included in the oxide film formed in the film formation chamber. The concentration of unintended impurities can be reduced.

  In the case where the oxide film is formed by a sputtering method, the relative density (filling rate) of the metal oxide target used for film formation is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target having a high relative density, the formed oxide film can be a dense film.

  In addition, by forming a film with the surface to be formed heated, unintentional impurities such as water and hydrogen can be prevented from entering the film. The temperature for heating the surface to be formed may be 150 ° C. or higher and 450 ° C. or lower, and preferably the substrate temperature may be 200 ° C. or higher and 350 ° C. or lower. Further, by heating the substrate at a high temperature at the time of film formation, an oxide film having crystallinity can be formed.

  The oxide film 103 can be formed by processing the oxide film formed by the above-described method into an island shape by a photolithography process. A resist mask for forming the island-shaped oxide layer 103 may be formed by an inkjet method. When the resist mask is formed by an inkjet method, a photomask is not used, so that manufacturing cost can be reduced.

  Next, an insulating film is formed over the oxide layer 103, and the insulating film is processed to form the protective layer 109 having an opening that exposes part of the top surface of the oxide layer 103 (FIG. 2B )).

  The protective layer 109 is provided so that a region of the oxide layer 103 that overlaps with the protective layer 109 is not exposed to a subsequent replacement process. Therefore, the material and thickness of the protective layer 109 are appropriately selected according to the method and conditions used for the subsequent substitution process.

  For example, as the protective layer 109, a film containing silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or a mixed material thereof It can be a single layer or a laminated structure. Here, the protective layer 109 preferably has a structure in which the oxide insulating layer is in contact with the oxide layer 103 as a single layer or a stacked structure including the oxide insulating layer.

  As the insulating layer 119, an oxide insulating film having an oxygen-excess region is preferably used for at least the layer in contact with the oxide layer 103 in the protective layer 109.

  The insulating film serving as the protective layer 109 can be formed by a plasma CVD method, a sputtering method, or the like.

  The opening portion of the protective layer 109 is formed so as not to cover a pair of opposed end portions of the oxide layer 103. Further, the opening is formed so as to traverse the oxide layer 103 so as to include a part of each of the other opposing ends of the oxide layer 103. By providing such an opening, a region where the upper surface is exposed and a region overlapping with the two protective layers 109 sandwiching the region are formed in the oxide layer 103. Note that the opening may be formed by a photolithography method or the like.

  Subsequently, a semiconductor region 107 is formed in part of the oxide layer 103 by performing substitution treatment on the exposed region of the oxide layer 103 (FIG. 2C). At this time, a pair of regions of the oxide layer 103 overlapping with the protective layer 109 becomes a low resistance region 105a and a low resistance region 105b, respectively.

  The replacement treatment is treatment for replacing the impurity element in the oxide layer 103 with oxygen by introducing high-energy oxygen 121 into the oxide layer 103. As the substitution treatment, oxygen radical treatment, treatment for introducing oxygen by an ion implantation method (oxygen ion implantation treatment), oxygen plasma treatment, thermal oxidation treatment, or the like can be used.

  The oxygen 121 contains at least one of oxygen radicals, ozone, oxygen atoms, and oxygen ions (including molecular ions and cluster ions).

  Part of the impurity element in the oxide semiconductor included in the oxide layer 103 is replaced with oxygen by the replacement treatment. Therefore, with the reduction of oxygen vacancies in the oxide semiconductor, the carrier concentration in the oxide semiconductor is reduced. Therefore, the semiconductor region 107 subjected to the replacement treatment functions as a semiconductor in which a channel of the transistor 100 is formed. On the other hand, the low-resistance region 105a and the low-resistance region 105b that are not subjected to the substitution treatment are low-resistance regions because the state where the carrier concentration is high is maintained, and function as a source region or a drain region of the transistor 100.

  When oxygen radical treatment is performed, high-density plasma excited by high frequency in an oxygen atmosphere is generated, and oxygen radicals excited by the high-density plasma are brought into contact with the surface to be treated. With the oxygen radical, the impurity element in the oxide layer 103 can be replaced with oxygen.

More specifically, a gas containing oxygen is introduced into a reduced-pressure processing chamber, and a high-density plasma is generated by introducing microwaves while the substrate 101 is heated to room temperature or a temperature of 100 ° C. to 550 ° C. Can be generated. When plasma excitation is performed by introduction of microwaves, plasma with a low electron temperature (3 eV or less, preferably 1.5 eV or less) and a high electron density (1 × 10 ¹¹ cm ⁻³ or more) can be generated. Substitution treatment can be performed on the oxide layer 103 by oxygen radicals (which may include OH radicals) generated by the high-density plasma. When a rare gas such as argon is mixed with the plasma processing gas, oxygen radicals can be efficiently generated by the excited species of the rare gas. This method can cause a solid phase reaction at a low temperature of 500 ° C. or lower by effectively using active radicals excited by plasma.

  As an ion implantation method used for the oxygen ion implantation treatment, a plasma immersion ion implantation method, an implantation method using a gas cluster ion beam, or the like may be used.

  In the case of using oxygen ion implantation, oxygen 121 may be introduced by treating the entire surface of the substrate 101 at one time, for example, using a linear ion beam. When a linear ion beam is used, the substrate 101 and the ion beam are scanned relatively.

As the oxygen supply gas, a gas containing oxygen can be used. For example, O ₂ gas, N ₂ O gas, CO ₂ gas, CO gas, NO ₂ gas, or the like can be used. When the apparatus used for the oxygen ion implantation process includes a mass analyzer, only the oxygen 121 can be introduced even if the gas containing nitrogen or carbon is used as a plate. Note that a rare gas (eg, Ar) may be included in the oxygen supply gas.

  The oxygen implantation depth may be set as appropriate in accordance with the thickness of the oxide layer 103, but is set so that an oxygen concentration peak is formed near the center of the oxide layer 103 in the thickness direction. It is preferable. In addition, when the oxygen implantation depth is variable during the treatment, it is more preferable to set so that the oxygen layer 103 is uniformly implanted in the thickness direction.

  Alternatively, heat treatment may be performed after oxygen 121 is introduced into the oxide layer 103 by an oxygen ion implantation treatment. By performing heat treatment, a substitution reaction between the impurity element remaining in the semiconductor region 107 and oxygen 121 that is not substituted with the impurity element can be promoted.

  In the case of performing oxygen plasma treatment, plasma is generated in an atmosphere containing oxygen, and oxygen ions or oxygen radicals are generated by the plasma. Oxygen 121 or oxygen radicals can be introduced into the oxide layer 103 by colliding with the surface of the substrate 101 placed over the electrode to which a bias potential is applied. Note that a rare gas (eg, Ar) is preferably contained in the oxygen supply gas because the concentration of oxygen supplied can be controlled while plasma is stabilized.

  Note that part of the upper layer of the exposed region of the oxide layer 103 is etched by the oxygen plasma treatment, so that the thickness of the semiconductor region 107 may be smaller than the thickness of the low resistance region 105a and the low resistance region 105b. .

  In the case of performing thermal oxidation treatment, oxygen 121 can be introduced into the oxide layer 103 by heating in an atmosphere containing oxygen.

  Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.

  The thermal oxidation treatment is preferably performed in an oxygen atmosphere or a mixed atmosphere of oxygen and a rare gas. At this time, it is preferable that water, hydrogen, etc. are not contained in oxygen gas and noble gas. For example, the purity of oxygen gas and rare gas introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). It is preferable to do.

  In addition, after heating the oxide layer 103 by heat treatment, high-purity oxygen gas or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) is maintained in the same furnace while maintaining the heating temperature or gradually cooling from the heating temperature. The amount of water when measured using a dew point meter of the system may be 20 ppm (air at dew point conversion of −55 ° C.) or less, preferably 1 ppm or less, more preferably 10 ppb or less. It is preferable that the oxygen gas does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas introduced into the heat treatment apparatus is preferably 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas is 1 ppm or less, preferably 0.1 ppm or less).

  As another method of thermal oxidation treatment, oxygen 121 may be introduced into the oxide layer 103 by irradiating the substrate 101 with laser light in an oxygen atmosphere and heating the oxide layer 103.

  Subsequently, a gate insulating layer 111 is formed over the protective layer 109 and the semiconductor region 107.

  The gate insulating layer 111 can be formed using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate.

As a material of the gate insulating layer 111, a direction insulating material such as silicon oxide, gallium oxide, aluminum oxide, silicon nitride, silicon oxynitride, aluminum oxynitride, or silicon nitride oxide can be used. The gate insulating layer 111 preferably contains oxygen in a portion in contact with the semiconductor region 107. In particular, the gate insulating layer 111 preferably includes oxygen in the film (in the bulk) at least in an amount exceeding the stoichiometric composition ratio. For example, when a silicon oxide film is used as the gate insulating layer 111, , SiO _{2 + α} (where α> 0).

As materials for the gate insulating layer 111, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added, and hafnium aluminate (HfAl _x O _y (HfAl _x O _y ( x> 0, y> 0)), and materials such as lanthanum oxide may be used. Further, the gate insulating layer 111 may have a single-layer structure or a stacked structure.

  Hydrogen (including water and hydroxyl groups) is removed (dehydrated or dehydrated) in the gate insulating layer 111 so that impurities such as hydrogen (including water and hydroxyl groups) are reduced and oxygen is excessive in the gate insulating layer 111. Heat treatment (dehydration or dehydrogenation treatment) or oxygen doping treatment may be performed. The dehydration or dehydrogenation treatment and the oxygen doping treatment may be performed a plurality of times, or both may be repeated.

  Next, a conductive film is formed over the gate insulating layer 111, and part of the conductive film is etched to form the gate electrode layer 113 (FIG. 2D).

  As a material for the gate electrode layer 113, a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component can be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode layer 113. The gate electrode layer 113 may have a single-layer structure or a stacked structure.

  As a material for the gate electrode layer 113, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Conductive metal oxide materials such as zinc oxide and indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the metal oxide material and the metal material can be employed.

  Further, as one layer of the gate electrode layer 113 in contact with the gate insulating layer 111, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, An In—Ga—O film containing nitrogen, an In—Zn—O film containing nitrogen, a Sn—O film containing nitrogen, an In—O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. . These films have a work function of 5 eV (electron volt), preferably 5.5 eV (electron volt) or higher, and when used as the gate electrode layer 113, the threshold voltage of the transistor can be set to a positive voltage. In other words, a so-called normally-off switching element can be realized.

  Subsequently, an insulating layer 117 is formed over the gate insulating layer 111 and the gate electrode layer 113. After that, an opening reaching the low resistance region 105a or the low resistance region 105b is formed in the insulating layer 117, the gate insulating layer 111, and the protective layer 109. Next, the source electrode layer 115a and the drain electrode layer 115b which are electrically connected to the low resistance region 105a or the low resistance region 105b through the opening are formed (FIG. 2E).

  The insulating layer 117 can be formed by a plasma CVD method, a sputtering method, an evaporation method, a coating method, or the like. As a material used for the insulating layer 117, a single layer of an inorganic insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, gallium oxide, hafnium oxide, magnesium oxide, zirconium oxide, lanthanum oxide, or barium oxide is used. It can be used in a laminated structure. Alternatively, as the insulating layer 117, an insulating film that can be easily planarized (planarized insulating film) may be formed in order to reduce surface unevenness due to the transistor, or an inorganic insulating film and a planarized insulating film may be stacked. Good. As the planarization insulating film, an organic material such as polyimide resin, acrylic resin, or benzocyclobutene resin can be used. Alternatively, a low dielectric constant material (low-k material) or the like can be used in addition to the organic material.

  As a material used for the source electrode layer 115a and the drain electrode layer 115b, for example, a metal such as aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten, or a nitride of the above metal (titanium nitride, molybdenum nitride, or tungsten nitride). ) Etc. can be used. In addition, a refractory metal film such as titanium, molybdenum, or tungsten or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) on one or both of the lower side or upper side of a metal film such as aluminum or copper ) May be laminated. Alternatively, the conductive film used for the source electrode layer 115a and the drain electrode layer 115b may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, or a material in which silicon oxide is included in these metal oxide materials can be used.

  For example, as the source electrode layer 115a and the drain electrode layer 115b, a single layer of a molybdenum film, a stacked film of a tantalum nitride film and a copper film, a stacked film of a tantalum nitride film and a tungsten film, or the like can be used.

  Since the source electrode layer 115a and the drain electrode layer 115b are provided in contact with the low resistance region 105a or the low resistance region 105b of the oxide layer 103, respectively, contact resistance thereof can be reduced.

  Through the above process, the transistor 100 can be formed over the substrate 101.

  According to the method exemplified in this manufacturing process example, an impurity element is added and a sufficiently low resistance low resistance region is used as the source region or the drain region, so that the parasitic resistance between the source electrode and the drain electrode is sufficiently high. A transistor with reduced on-state characteristics can be manufactured.

  Further, a part of the impurity layer in the oxide layer including the oxide semiconductor to which the impurity element is added is replaced with oxygen, so that a semiconductor region in which a channel is formed is formed. Therefore, the source region and the drain region are not thinned by a process for forming the low resistance region (for example, argon plasma treatment), and the source region and the drain region can be made a low resistance region.

<Modification 1>
Hereinafter, a structural example and a manufacturing process example of a transistor having a different structure from the transistor exemplified in the above structural example will be described.

  FIG. 3A is a schematic cross-sectional view of the transistor 110 exemplified in this modification. The transistor 110 is different from the transistor 100 illustrated in the above structure example in that the semiconductor region 107 includes a region having a smaller thickness than the low resistance region 105a and the low resistance region 105b.

  A part of the semiconductor region 107 is formed thinner than the low resistance region 105a or the low resistance region 105b.

  Thus, part of the semiconductor region 107 is provided thinner than the low resistance region 105a and the low resistance region 105b, so that the threshold voltage of the transistor 110 can be easily set to a positive voltage. A normally-off switching element can be realized. Further, since the thickness of the semiconductor region 107 can be reduced, the short channel effect can be suppressed. Furthermore, since the low resistance region 105a and the low resistance region 105b can be formed thick, parasitic resistance between the source electrode and the drain electrode can be reduced.

  The semiconductor region 107 has a so-called taper shape in which the thickness increases as the end portion is in contact with the low resistance region 105a or the low resistance region 105b. Furthermore, the thickness of the end portion of the semiconductor region 107 that is in contact with the low resistance region 105a or the low resistance region 105b is preferably equal to the thickness of the low resistance region 105a and the low resistance region 105b.

  FIG. 3B is an enlarged view of the vicinity of the boundary between the semiconductor region 107 indicated by a broken line in FIG. 3A and the low-resistance region 105b functioning as a drain. Here, FIG. 3B schematically illustrates a state in which the carrier 123 flows toward the low resistance region 105b when the transistor 110 is on.

  As shown in FIG. 3B, since the end portion of the semiconductor region 107 is tapered, the carrier 123 spreads in the thickness direction at the end portion of the semiconductor region 107 and flows to the low resistance region 105b. In addition, the current density at the boundary between the semiconductor region 107 and the low resistance region 105b can be reduced. Therefore, heat generation at the end portion is suppressed, and the transistor 110 can have high reliability.

  At this time, if the oxide layer 103 is provided so as to continuously increase in thickness so as not to cause a step at the boundary between the semiconductor region 107 and the low resistance region 105a or the low resistance region 105b, the current density at these boundaries is increased. It is preferable because relaxation of the is promoted.

  In particular, in a top-gate transistor, the coverage of the gate insulating layer 111 is increased at the boundary between the semiconductor region 107 and the low-resistance region 105a or the low-resistance region 105b having different thicknesses, so that the gate insulating layer 111 is locally formed. Problems such as gate leakage and dielectric breakdown due to thinning are suppressed, and the transistor 110 with high reliability can be obtained.

  The case where the transistor 110 including the oxide layer 103 including the semiconductor region 107 having such a shape is manufactured will be described below with reference to FIGS.

  First, as in the above manufacturing process example, the insulating layer 119, the oxide layer 103, and the insulating film 108 to be the protective layer 109 are formed over the substrate 101 (FIG. 4A). Subsequently, part of the insulating film 108 is etched to form the protective layer 109 (FIG. 4B).

  At this time, by performing over-etching so that the upper layer of the oxide layer 103 is etched when the insulating film 108 is etched, as shown in FIG. A part of the region to be formed can be thinned.

  Alternatively, after the insulating film 108 is etched, the oxide layer 103 may be processed by further etching the upper layer of the oxide layer 103 using the same resist mask. Alternatively, after the insulating film 108 is etched to form the protective layer 109 and the resist mask is removed, the upper layer of the oxide layer 103 is etched using the protective layer 109 as an etching mask (also referred to as a hard mask). Good.

  Subsequently, the exposed region of the oxide layer 103 is subjected to reduction treatment, and oxygen 121 is introduced into the region to replace the impurity element with oxygen, whereby the semiconductor region 107 is formed in part of the oxide layer 103. It forms (FIG.4 (C)).

  After that, in accordance with the above manufacturing process example, the gate insulating layer 111, the gate electrode layer 113, the insulating layer 117, the source electrode layer 115a, and the drain electrode layer 115b are formed (FIG. 4D).

  Note that in the above description, the method for reducing the thickness of the region to be the semiconductor region 107 of the oxide layer 103 and then performing the reduction treatment on the region has been described. However, the reduction treatment and the etching process on the upper layer of the oxide layer 103 are performed. You may do it at the same time. For example, after the insulating film 108 is etched to form the protective layer 109, a part of the oxide layer 103 is etched on the oxide layer 103, such as an oxygen plasma treatment, as a reduction treatment for the exposed region of the oxide layer 103. By performing this process, oxygen 121 is introduced into a region to be the semiconductor region 107 of the oxide layer 103, and the region is thinned.

  Through the above steps, the transistor 110 can be manufactured.

  This embodiment can be implemented in combination with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 2)
In this embodiment, as another example of the semiconductor device of one embodiment of the present invention, a structure example of a transistor having a structure different from that in the above embodiment and an example of a manufacturing method thereof will be described. In addition, below, description is abbreviate | omitted about the part which overlaps with the said embodiment, and a different point is demonstrated in detail.

<Configuration example>
5A is a schematic top view of the transistor 150 exemplified in this embodiment, and FIG. 5B is a schematic cross-sectional view taken along a cutting line CD in FIG. 5A. Note that some components (such as the gate insulating layer 111) are not illustrated in FIG. 5A for clarity.

  The transistor 150 is different from the transistor 110 described in Embodiment 1 in that the protective layer 109 is not provided, and the source electrode layer 115a or the drain electrode layer 115b is in contact with the top surface and the side surface of the oxide layer 103. Is different.

  The source electrode layer 115a and the drain electrode layer 115b cover the low resistance region 105a or the low resistance region 105b, respectively, and are provided in contact with the upper surface and side surfaces thereof. Accordingly, the contact area of the source electrode layer 115a and the drain electrode layer 115b with the low-resistance region 105a or the low-resistance region 105b can be significantly increased as compared with the transistor 110, so that the region between the source electrode layer 115a and the drain electrode layer 115b is The parasitic resistance can be made extremely small.

<Example of manufacturing process>
Hereinafter, an example of a manufacturing process of the transistor 150 will be described with reference to FIGS. FIG. 6 is a schematic cross-sectional view according to a method for manufacturing the transistor exemplified in this embodiment.

  First, the insulating layer 119 and the oxide layer 103 are formed over the substrate 101 by the method exemplified in Embodiment 1.

  Next, a conductive film 114 to be the later source electrode layer 115a and drain electrode layer 115b is formed over the insulating layer 119 and the oxide layer 103 (FIG. 6A).

  Next, part of the conductive film 114 is etched to form the source electrode layer 115a and the drain electrode layer 115b (FIG. 6B).

  At this time, as shown in FIG. 6B, an upper layer of the exposed region of the oxide layer 103 may be etched, and a region to be a semiconductor region 107 later may be thinned. For the method for etching the upper layer of the oxide layer 103, Modification 1 of Embodiment 1 may be referred to.

  Subsequently, the exposed region of the oxide layer 103 is subjected to reduction treatment, and oxygen 121 is introduced into the region to replace the impurity element with oxygen, whereby the semiconductor region 107 is formed in part of the oxide layer 103. It is formed (FIG. 6C).

  At this time, depending on the replacement treatment method, part of the upper surfaces of the source electrode layer 115a and the drain electrode layer 115b may be oxidized and insulated. Therefore, the conductive film 114 included in the source electrode layer 115a and the drain electrode layer 115b is preferably formed thick beforehand in accordance with the replacement treatment method used.

  In addition, an oxide film is formed on the top surfaces of the source electrode layer 115a and the drain electrode layer 115b by the replacement treatment, so that the oxide film is used as a barrier film for suppressing corrosion and migration of the source electrode layer 115a and the drain electrode layer 115b. be able to.

  Thereafter, in accordance with Embodiment Mode 1, a gate insulating layer 111, a gate electrode layer 113, and an insulating layer 117 are formed (FIG. 6D).

  Through the above process, the transistor 150 can be manufactured.

  According to such a method, since the source electrode layer 115a and the drain electrode layer 115b also function as the protective layer 109 in Embodiment 1, the manufacturing process can be simplified and the manufacturing can be performed with high yield.

  This embodiment can be implemented in combination with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 3)
In this embodiment, as another example of the semiconductor device of one embodiment of the present invention, a structural example of a transistor having a structure different from that of the above embodiment will be described. In addition, below, description is abbreviate | omitted about the part which overlaps with the said embodiment, and a different point is demonstrated in detail.

<Configuration example 1>
7A is a schematic top view of the transistor 170 exemplified in this structural example, and FIG. 7B is a schematic cross-sectional view taken along the cutting line EF in FIG. 7A. Note that some components (such as the protective layer 109 and the gate insulating layer 111) are not illustrated in FIG. 7A for clarity.

  The transistor 170 is different from the transistor 110 illustrated in Embodiment 1 in that the source electrode layer 115 a and the drain electrode layer 115 b are arranged on the substrate 101 side with respect to the oxide layer 103.

  The source electrode layer 115a and the drain electrode layer 115b are provided to be separated from each other over the insulating layer 119, and the oxide layer 103 is provided in contact with the source electrode layer 115a and the drain electrode layer 115b. Each of the source electrode layer 115a and the drain electrode layer 115b is electrically connected to the low resistance region 105a or the low resistance region 105b. The semiconductor region 107 of the oxide layer 103 is provided so as to overlap with a region between the source electrode layer 115a and the drain electrode layer 115b.

  Here, the source electrode layer 115 a or the drain electrode layer 115 b may be provided so as to overlap with the gate electrode layer 113. In this configuration example, since the protective layer 109 is provided between the gate electrode layer 113 and the source electrode layer 115a or the drain electrode layer 115b, the parasitic capacitance between the electrodes can be sufficiently reduced even if they are provided in an overlapping manner. can do.

  Further, opposing end portions of the source electrode layer 115 a and the drain electrode layer 115 b may extend to a region overlapping with the semiconductor region 107. At this time, part of the source electrode layer 115 a and the drain electrode layer 115 b may be in contact with the lower surface of the semiconductor region 107. Thus, by providing the source electrode layer 115a and the drain electrode layer 115b so as to increase the contact area with the low resistance region 105a or the low resistance region 105b, the parasitic resistance between the source electrode layer 115a and the drain electrode layer 115b. Can be further reduced.

  In the structure of the transistor 110, the source electrode layer 115a or the drain electrode layer 115b and the gate electrode layer 113 may be in contact with each other, so that the distance between the source electrode layer 115a and the drain electrode layer 115b is sufficiently large. Although it cannot be made small, the transistor 170 exemplified in this structural example does not have such a need, so that a fine transistor can be realized.

<Configuration example 2>
8A is a schematic top view of the transistor 180 exemplified in this structural example, and FIG. 8B is a schematic cross-sectional view taken along a cutting line GH in FIG. 8A. Note that some components (such as the gate insulating layer 111 and the insulating layer 117) are not illustrated in FIG. 8A for clarity.

  The transistor 180 is different from the transistor 150 illustrated in Embodiment 2 in that the gate electrode layer 113 and the gate insulating layer 111 are provided closer to the substrate 101 than the oxide layer 103.

  Specifically, the gate electrode layer 113 is provided over the insulating layer 119, and the gate insulating layer 111 is provided to cover the gate electrode layer 113. An oxide layer 103 is provided in contact with the gate insulating layer 111 so as to overlap with the gate electrode layer 113. Further, a source electrode layer 115a or a drain electrode layer 115b is provided in contact with the upper surfaces of the low resistance region 105a and the low resistance region 105b of the oxide layer 103, respectively. In addition, a semiconductor region 107 is provided in a region of the oxide layer 103 that does not overlap with the source electrode layer 115a and the drain electrode layer 115b.

  Here, as illustrated in FIG. 8, the gate electrode layer 113 is provided so as to overlap with part of the source electrode layer 115a and the drain electrode layer 115b, so that the semiconductor region is turned on when the transistor 180 is turned on. Since a channel is formed in the entire region including the end portion 107, the on-state current of the transistor 180 can be increased.

  8C, a second gate insulating layer 181 that is in contact with the upper surface of the semiconductor region 107 and a second gate electrode layer that is in contact with the second gate insulating layer 181 and overlaps with the semiconductor region 107 are formed. It is good also as a structure which provides 183. By applying an appropriate potential to one of the gates, the threshold voltage of the transistor can be freely set. 8C, the semiconductor region 107 is sandwiched between two gate insulating layers, so that diffusion of impurities into the semiconductor region 107 is suppressed and a highly reliable transistor can be realized.

  This embodiment can be implemented in combination with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 4)
In this embodiment, examples of resistance elements that can be manufactured by the above-described method for manufacturing a semiconductor device will be described with reference to drawings. In addition, below, description is abbreviate | omitted about the part which overlaps with the said embodiment, and a different point is demonstrated in detail.

  In addition, the resistance element exemplified in this embodiment can be manufactured in the same manufacturing process as the transistor exemplified in the above embodiment. Therefore, the transistor and the resistor can be manufactured over the same substrate without increasing the number of steps. In addition, in the case where a layer included in the resistor element exemplified in this embodiment has a function common to any one of the layers included in the transistor described in the above embodiment, the name and the code are common. May be used.

<Configuration example 1>
9A is a schematic top view of the resistance element 200 exemplified in this configuration example, and FIG. 9B is a schematic cross-sectional view taken along the cutting line IJ in FIG. 9A. Note that for clarity, some of the components (such as the insulating layer 117) are not explicitly illustrated in FIG.

  The resistance element 200 is different from the transistor 100 illustrated in Embodiment 1 in that it does not include the gate electrode layer 113.

  The resistance element 200 includes an oxide layer 103 including a semiconductor region 107 sandwiched between a low resistance region 105a and a low resistance region 105b. A protective layer 109 is provided in contact with the upper surfaces of the low resistance region 105a and the low resistance region 105b. In addition, the first electrode layer 125a and the second electrode layer 125b provided over the insulating layer 117 have low resistance through openings provided in the insulating layer 117, the gate insulating layer 111, and the protective layer 109. The region 105a or the low resistance region 105b is electrically connected.

  The resistance element 200 is a resistance element using the resistance component of the semiconductor region 107. Here, the low resistance region 105a and the low resistance region 105b are sufficiently reduced in resistance, and the contact resistance between the region and the first electrode layer 215a or the second electrode layer 215b is also sufficiently reduced. Since the parasitic resistance between the first electrode layer 215 a or the second electrode layer 215 b is extremely small, the resistance value of the resistance element 200 is substantially determined by the resistance component of the semiconductor region 107.

  Here, the conductivity of the semiconductor region 107 can be changed by changing the conditions of the replacement process in forming the semiconductor region 107. Therefore, even if the resistance element 200 is formed in the same shape, resistance elements having various resistance values can be manufactured by changing the replacement process condition according to the required resistance value.

  Note that the gate insulating layer 111 and the insulating layer 117 may not be provided. Further, when at least one of the gate insulating layer 111 and the insulating layer 117 is provided in contact with the upper surface of the semiconductor region 107, diffusion of impurities into the semiconductor region 107 is suppressed, so that the resistance element 200 can have high reliability. This is preferable.

<Configuration example 2>
10A is a schematic top view of the resistance element 210 exemplified in this configuration example, and FIG. 10B is a schematic cross-sectional view taken along the cutting line KL in FIG. 10A. Note that for clarity, some of the components (such as the insulating layer 117) are not explicitly illustrated in FIG.

  The resistance element 210 is different from the transistor 150 illustrated in Embodiment 2 in that it does not include the gate electrode layer 113.

  The first electrode layer 215a and the second electrode layer 215b cover the low resistance region 105a or the low resistance region 105b, respectively, and are provided in contact with the upper surface and side surfaces thereof. Accordingly, since the contact area between the first electrode layer 215a and the second electrode layer 215b with the low resistance region 105a or the low resistance region 105b can be extremely large as compared with the resistance element 200, the first electrode layer 215a and the second electrode layer 215b The contact resistance between the two electrode layers 215b can be made extremely small.

  Further, similarly to the above configuration example 1, the gate insulating layer 111 and the insulating layer 117 may be omitted. However, it is preferable to provide at least one of them because the resistance element 210 can be highly reliable.

  This embodiment can be implemented in combination with any of the other embodiments and examples described in this specification as appropriate.

(Embodiment 5)
When an oxide semiconductor film having crystallinity is used as the oxide semiconductor that can be used for the oxide layer 103 described in the above embodiment, the electrical characteristics of the transistor can be improved. It is preferable that a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film be used as the oxide semiconductor film. A semiconductor device to which the CAAC-OS film is applied is described below.

  The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts and amorphous parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

  The crystal part included in the CAAC-OS film is triangular when viewed from the direction perpendicular to the ab plane and the c-axis is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface. It has a shape or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

  Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. In addition, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

  Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape or the cross-sectional shape of the surface). Note that the c-axis direction of the crystal part is in a direction parallel to the normal direction of the formation surface or the normal direction of the surface when the CAAC-OS film is formed. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

  A transistor including a CAAC-OS film can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

  Note that part of oxygen included in the oxide semiconductor film may be replaced with nitrogen.

  Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

  Note that Ra is an arithmetic mean roughness defined in JIS B 0601: 2001 (ISO4287: 1997) expanded to three dimensions so that it can be applied to a curved surface. Can be expressed as “average value of absolute values of” and defined by the following equation (1).

In the above, the designated surface is a surface to be subjected to roughness measurement, and coordinates ((x ₁ , y ₁ , f (x ₁ , y ₁ )) (x ₁ , y ₂ , f (x ₁₎ , Y ₂ )) (x ₂ , y ₁ , f (x ₂ , y ₁ )) (x ₂ , y ₂ , f (x ₂ , y ₂ )) The area of the rectangle projected on the xy plane is S0, and the height of the reference surface (average height of the specified surface) is Z _0. Ra can be evaluated with an atomic force microscope (AFM). It is.

  As a method for obtaining the CAAC-OS film as described above, for example, the oxide semiconductor film is formed by heating the substrate (for example, the substrate temperature is set to 170 ° C.), and the c-axis alignment is performed substantially perpendicular to the surface. There is a way.

  Note that the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. A crystalline oxide that is different from a CAAC-OS is used for the first oxide semiconductor film and the second oxide semiconductor film. A semiconductor may be applied. In other words, the CAAC-OS and a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, or an amorphous oxide semiconductor may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress and external stress of the stacked oxide semiconductor film are relieved. In addition, variations in transistor characteristics can be reduced, and the reliability of the transistor can be further improved. On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor, such as hydrogen, and easily generates oxygen vacancies, so that it is easily n-type. Therefore, it is preferable to use an oxide semiconductor having crystallinity such as CAAC-OS for the oxide semiconductor film on the channel side.

  Alternatively, the oxide semiconductor film may have a stacked structure of three or more layers and a structure in which an amorphous oxide semiconductor film is sandwiched between a plurality of crystalline oxide semiconductor films. Alternatively, a structure in which crystalline oxide semiconductor films and amorphous oxide semiconductor films are alternately stacked may be employed. The above structures in the case where the oxide semiconductor film has a stacked structure of a plurality of films can be combined as appropriate.

  As described above, with the use of the CAAC-OS film as the oxide semiconductor film, hydrogen can be easily released from the top surface of the CAAC-OS film in heat treatment (dehydrogenation treatment). Further, in the heat treatment, it is possible to selectively release a large amount of hydrogen by reducing the separation of oxygen.

  This embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 6)
In this embodiment, a CPU (Central Processing Unit) using at least part of the semiconductor device disclosed in the above embodiment will be described as an example of the semiconductor device.

  FIG. 11A is a block diagram illustrating a specific configuration of a CPU. The CPU shown in FIG. 11A has an ALU 1191 (ALU: arithmetic circuit unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, an ALU 1191 (arithmetic logic unit). A bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) are included. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 11A is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

  Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

  The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

  In the CPU illustrated in FIG. 11A, a memory cell is provided in the register 1196. The memory cell of the register 1196 includes both a logic element that inverts logic (hereinafter referred to as an inverting element) and a nonvolatile memory element.

  In the CPU illustrated in FIG. 11A, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by an inverting element or to hold data by a nonvolatile memory element in a memory cell included in the register 1196 is selected. When the data retention by the inverting element is selected, the power supply voltage is supplied to the memory cell in the register 1196. When retention of data in the nonvolatile memory element is selected, data is rewritten to the nonvolatile memory element, and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

  The power supply is stopped by providing a switching element between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied, as shown in FIG. 11B or 11C. Can do. The circuits in FIGS. 11B and 11C will be described below.

  11B and 11C, the register 1196 includes a switching element that controls supply of a power supply potential to the memory cell.

  A register 1196 illustrated in FIG. 11B includes a switching element 1141 and a memory cell group 1143 including a plurality of memory cells 1142. Specifically, each memory cell 1142 includes both an inverting element and a nonvolatile memory element. A high-level power supply potential VDD is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. Further, each memory cell 1142 included in the memory cell group 1143 is supplied with the potential of the signal IN and the low-level power supply potential VSS.

  In FIG. 11B, a transistor is used as the switching element 1141, and switching of the transistor is controlled by a signal SigA applied to the gate electrode thereof.

  Note that FIG. 11B illustrates a structure in which the switching element 1141 includes only one transistor; however, there is no particular limitation, and a plurality of transistors may be included. In the case where the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be combined in series and parallel. May be connected.

  FIG. 11C illustrates an example of a register 1196 in which a low-level power supply potential VSS is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143.

  A switching element is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied to temporarily stop the operation of the CPU and retain data even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, even when a personal computer user stops inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption. it can.

  In addition, since electronic devices to which such a CPU is applied have reduced power consumption, they can operate sufficiently even with relatively small power obtained by, for example, solar cells or non-contact power feeding (also referred to as wireless power feeding). it can. For example, the electronic device includes a solar battery module or a non-contact power supply module and a secondary battery (such as a lithium ion battery) that stores electric power obtained by such a module.

  By applying the semiconductor device illustrated in the above embodiment to a switching element or a resistance element that constitutes such a CPU, a CPU in which high-speed operation is realized with high on-state characteristics can be obtained.

  Here, the CPU has been described as an example, but the present invention can also be applied to LSIs such as a DSP (Digital Signal Processor), a custom LSI, and an FPGA (Field Programmable Gate Array).

(Embodiment 7)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). As electronic equipment, display devices such as televisions, monitors, lighting devices, desktop or notebook personal computers, word processors, image reproduction for reproducing still images or moving images stored in recording media such as a DVD (Digital Versatile Disc) Device, Portable CD player, Radio, Tape recorder, Headphone stereo, Stereo, Cordless phone cordless handset, Transceiver, Portable radio, Mobile phone, Car phone, Portable game machine, Calculator, Personal digital assistant, Electronic notebook, Electronic book, Electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners, etc., dishwashers, dish drying , Clothes dryer, futon dryer Electric refrigerators, electric freezers, electric refrigerator, DNA storage freezers, smoke detectors, radiation counters, medical devices such as dialyzers and the like. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, and power storage systems. In addition, an engine using petroleum, a moving body driven by an electric motor using electric power from a non-aqueous secondary battery, and the like are also included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, and electric assist. Examples include motorbikes including bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes, planetary probes, and space ships. Specific examples of these electronic devices are shown in FIGS.

  FIG. 12A shows a portable music player. A main body 3021 is provided with a display portion 3023, a fixing portion 3022 to be attached to the ear, a speaker, operation buttons 3024, an external memory slot 3025, and the like. By applying the semiconductor device illustrated in the above embodiment to a CPU or the like incorporated in the main body 3021, a portable music player (PDA) with further reduced power consumption can be obtained.

  Furthermore, if the portable music player shown in FIG. 12A is provided with an antenna, a microphone function, and a wireless function and is linked to a mobile phone, a wireless hands-free conversation is possible while driving a passenger car or the like.

  FIG. 12B illustrates a computer, which includes a main body 9201 including a CPU, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like. If a semiconductor device such as a CPU described in the above embodiment is used, a power-saving computer can be obtained.

  In FIG. 13A, a television set 8000 includes a display portion 8002 incorporated in a housing 8001 and can display an image on the display portion 8002 and output sound from a speaker portion 8003. The semiconductor device described in the above embodiment can be used for a driver circuit for operating the display portion 8002 incorporated in the housing 8001.

  A display portion 8002 includes a semiconductor display device such as a liquid crystal display device, a light emitting device including a light emitting element such as an organic EL element, an electrophoretic display device, a DMD (Digital Micromirror Device), and a PDP (Plasma Display Panel). Can be used.

  The television device 8000 may include a receiver, a modem, and the like. The television device 8000 can receive a general television broadcast by a receiver, and is connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (between the sender and the receiver or between the receivers).

  In addition, the television device 8000 may include a CPU for performing information communication and a memory. As the television device 8000, a semiconductor device such as a CPU exemplified in the above embodiment can be used.

  In FIG. 13A, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 is an example of an electronic device using a semiconductor device such as a CPU exemplified in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. Although FIG. 13A illustrates the case where the CPU 8203 is provided in the indoor unit 8200, the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the CPU exemplified in the above embodiment, an air conditioner excellent in power saving can be realized.

  In FIG. 13A, an electric refrigerator-freezer 8300 is an example of an electronic device including a semiconductor device such as a CPU exemplified in the above embodiment. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, and the like. In FIG. 13A, the CPU 8304 is provided inside the housing 8301. By using the semiconductor device such as the CPU exemplified in the above embodiment for the CPU 8304 of the electric refrigerator-freezer 8300, power saving can be achieved.

  FIG. 13B and FIG. 13C illustrate an example of an electric vehicle which is an example of an electronic device. An electric vehicle 9700 is equipped with a secondary battery 9701. The output of the power of the secondary battery 9701 is adjusted by the control circuit 9702 and supplied to the driving device 9703. The control circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By using a semiconductor device such as a CPU exemplified in the above embodiment for the processing device 9704 of the electric vehicle 9700, power saving can be achieved.

  The drive device 9703 is configured by a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine. The processing device 9704 is based on input information such as operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of traveling (information such as uphill and downhill, load information on the drive wheels) The control signal is output to the control circuit 9702. The control circuit 9702 controls the output of the driving device 9703 by adjusting the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter that converts direct current to alternating current is also built in, although not shown.

  This embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

  In this example, a substitution treatment was performed on an oxide film including an oxide semiconductor to which an impurity element was added, and the sheet resistance was measured before and after the substitution treatment, and the cross-sectional observation was performed after the substitution treatment. Show about.

<Preparation of sample>
First, a silicon oxide film was formed on a 126 mm × 126 mm glass substrate by a sputtering method so as to have a thickness of 100 nm.

  Subsequently, an In—Ga—Zn—O film (hereinafter also referred to as an IGZO—N film) to which nitrogen was added was formed over the silicon oxide film by a sputtering method so as to have a thickness of 30 nm.

The film formation condition of the IGZO-N film is an oxide target having a composition ratio of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 2 [mol ratio], and the distance between the substrate and the target is set as follows. The substrate temperature was 200 ° C. in an atmosphere of 60 mm, pressure 0.4 Pa, direct current (DC) power supply 0.5 kW, and nitrogen (N ₂ flow rate 40 sccm).

  For the IGZO-N film, a sample (sample 1) subjected to oxygen radical treatment as a replacement treatment and a sample (sample 2) subjected to oxygen ion implantation treatment were manufactured.

The conditions for the oxygen radical treatment were argon and oxygen (Ar flow rate 900 sccm, O2 flow rate 5 sccm) atmosphere, power 3.8 kW (frequency 2.45 GHz), substrate temperature 200 ° C., processing chamber pressure 10 ⁶ Pa, electrode spacing 60 mm, The treatment was performed for 10 minutes.

An ion implantation method was used as the oxygen ion implantation process. The oxygen ion implantation conditions were an oxygen ion dose of 5.0 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 5 kV.

  Through the above steps, Sample 1 in which oxygen radical treatment was performed as a substitution treatment on the IGZO-N film and Sample 2 in which oxygen ion implantation treatment was conducted as a substitution treatment were produced. Moreover, the thing which has not performed the substitution process was used as a comparative example.

  Here, with respect to Sample 1 and Sample 2, sheet resistance measurement was performed before and after the substitution process. The measurement was performed on 25 points in a 100 mm × 100 mm region.

<Sheet resistance measurement>
Then, the result of the sheet resistance measurement measured before and after the substitution process in Sample 1 and Sample 2 is shown.

[Sample 1]
The measurement result of the sheet resistance of Sample 1 is shown in FIG. While the sheet resistance value was in the range of 0.43 MΩ / □ to 1.63 MΩ / □ before the replacement process, the sheet resistance value was higher than the detection upper limit of the apparatus after the replacement process ( 1 GΩ / □ or more).

[Sample 2]
The measurement result of the sheet resistance of Sample 2 is shown in FIG. The sheet resistance value was in the range of 0.40 MΩ / □ to 1.39 MΩ / □ before the replacement process, but after the replacement process, it exceeded the upper detection limit of the device except for abnormal values. (1 GΩ / □ or more). Here, after the replacement process was performed, the points where the sheet resistance value was extremely low were distributed unevenly toward the edge of the substrate, and thus were excluded from the target as abnormal values.

<Observation result of cross-sectional image>
Subsequently, cross sections of the three prepared samples were observed with a scanning transmission electron microscope (STEM (Scanning Transmission Electron Microscopy)). As a pretreatment for observation, carbon and Pt were coated on each sample.

[Comparative example]
A cross-sectional observation image of the comparative example is shown in FIG. It was confirmed that the IGZO-N film was formed with a thickness of about 32.6 nm on the silicon oxide film.

[Sample 1]
A cross-sectional observation image of Sample 1 is shown in FIG. It was confirmed that the IGZO-N film was formed with a thickness of about 35.3 nm on the silicon oxide film. In addition, it was confirmed that a different layer was formed in a region of about 12.1 nm of the upper layer of the IGZO-N film (a region indicated by an arrow in the drawing).

[Sample 2]
A cross-sectional observation image of Sample 2 is shown in FIG. It was confirmed that the IGZO-N film was formed with a thickness of about 33.7 nm on the silicon oxide film. In addition, it was confirmed that a different layer was formed in a region of approximately 6.2 nm (region indicated by an arrow in the drawing) of the upper layer of the IGZO-N film.

<EDX analysis>
Subsequently, the results of analysis by energy dispersive X-ray spectroscopy (EDX) of the different layers in the IGZO-N films observed in Sample 1 and Sample 2 are shown. The same analysis was performed for the comparative example.

  FIG. 17 shows the EDX analysis results in the IGZO-N film of the comparative example and the different layers in the IGZO-N films of Sample 1 and Sample 2. FIG. 17 shows the relative concentrations of Ga, Zn, N, and O with respect to In.

  In both Sample 1 and Sample 2, it was confirmed that the nitrogen concentration decreased and the oxygen concentration increased.

  From the above series of results, it was confirmed that nitrogen, which is an impurity element in the IGZO-N film, was replaced with oxygen by the replacement treatment. Furthermore, it was confirmed that the resistivity was significantly increased by substituting a part of the upper layer of the IGZO-N film with oxygen by the substitution treatment.

  Here, in this example, the effect of the replacement treatment was observed only in a part of the upper layer of the IGZO-N film. However, from the result of this example, the IGZO-N film was made thinner or the conditions for the replacement treatment were further increased. It was suggested that the replacement process could be performed over the entire layer of the IGZO-N film by optimization.

<Composition analysis result by XPS analysis>
In this example, the results of a more detailed composition analysis using the X-ray photoelectron spectroscopy (XPS) for the three samples prepared in Example 1 are shown.

  FIG. 18 shows the composition analysis results by XPS analysis on the outermost surface of the IGZO-N film for the comparative example, sample 1 and sample 2. FIG. 18 shows the concentrations of In, Ga, Zn, N, and O.

  The nitrogen concentration was about 10.5 atom% in the comparative example where no substitution treatment was performed, whereas it was about 1.4 atom% in the sample 1 and about 5.1 atom% in the sample 2.

  On the other hand, the oxygen concentration was about 47.8 atom% in the comparative example, whereas it was 59.5 atom% for sample 1 and about 55.5 atom% for sample 2.

  As described above, it was confirmed that the nitrogen in the film was replaced with oxygen because a substantial decrease in the concentration of nitrogen and a significant increase in the concentration of oxygen were observed after the substitution treatment.

100 transistor 101 substrate 103 oxide layer 105a low resistance region 105b low resistance region 107 semiconductor region 108 insulating film 109 protective layer 110 transistor 111 gate insulating layer 113 gate electrode layer 114 conductive film 115a source electrode layer 115b drain electrode layer 116 gate electrode layer 117 Insulating layer 118 Insulating layer 119 Insulating layer 121 Oxygen 123 Carrier 125a Electrode layer 125b Electrode layer 150 Transistor 170 Transistor 180 Transistor 181 Gate insulating layer 183 Gate electrode layer 200 Resistance element 210 Resistance element 215a Electrode layer 215b Electrode layer 1141 Switching element 1142 Memory Cell 1143 Memory cell group 1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
3021 Main body 3022 Fixed portion 3023 Display portion 3024 Operation button 3025 External memory slot 8000 Television apparatus 8001 Case 8002 Display portion 8003 Speaker portion 8200 Indoor unit 8201 Case 8202 Air outlet 8203 CPU
8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigeration room door 8303 Freezing room door 8304 CPU
9201 Main body 9202 Case 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9700 Electric vehicle 9701 Secondary battery 9702 Control circuit 9703 Driving device 9704 Processing device

Claims (2)

An oxide layer;
A gate insulating film;
A gate electrode overlapping the oxide layer through the gate insulating film;
A source electrode electrically connected to the oxide layer;
A drain electrode electrically connected to the oxide layer ,
The oxide layer has a first layer and a second layer,
The first layer and the second layer have In, Ga, and Zn, respectively.
The first layer disposed on the side far from the gate electrode has an In and Ga content ratio of In ≦ Ga,
The second layer disposed on the side close to the gate electrode has a content ratio of In and Ga of In> Ga ,
The oxide layer includes a first region, a second region, and a channel formation region between the first region and the second region,
The channel formation region overlaps the gate electrode;
Each of the first region and the second region is in contact with an insulating film,
The insulating film has a first taper at an end,
The semiconductor device , wherein the oxide layer has a second taper in a region continuous with the first taper . An oxide layer;
A gate insulating film;
A gate electrode overlapping the oxide layer through the gate insulating film;
A source electrode electrically connected to the oxide layer;
A drain electrode electrically connected to the oxide layer,
The oxide layer includes a first region, a second region, and a channel formation region between the first region and the second region,
The channel formation region overlaps the gate electrode;
Each of the first region and the second region is in contact with an insulating film,
The insulating film has a first taper at an end,
The semiconductor device, wherein the oxide layer has a second taper in a region continuous with the first taper.