JP5795551B2 - Method for manufacturing field effect transistor - Google Patents

Description

  The present invention relates to a method for manufacturing a field effect transistor.

  2. Description of the Related Art In recent years, field-effect transistors using an In—Ga—Zn—O-based (hereinafter referred to as IGZO) oxide semiconductor thin film as an oxide semiconductor layer (channel layer), particularly thin film transistors (TFTs), have been researched. Development is thriving. An oxide semiconductor thin film can be formed at a low temperature, exhibits higher mobility than amorphous silicon, and is transparent to visible light. Therefore, a flexible TFT should be formed on a substrate such as a plastic plate or film. Is possible (for example, Non-Patent Document 1).

  As a modification of the TFT using such an IGZO as an oxide semiconductor layer, Patent Document 1 discloses that a first region containing IZO or ITO is disposed on the side closer to the gate electrode, and IGZO is disposed on the side far from the gate electrode. There is disclosed a TFT using an oxide semiconductor layer having a two-layer structure in which a second region including the semiconductor layer is disposed.

  In addition, Patent Document 2 includes IGZO having a composition ratio different from that of IGZO in the first region on the surface of the first region including IGZO as the step of forming the oxide semiconductor layer having the two-layer structure. A method of manufacturing a bottom gate type TFT in which the second region is formed by sputtering at a film forming pressure of 0.4 Pa is disclosed.

C.S.Chuang et al., SID 08 DIGEST, P-13

JP 2010-21555 A JP 2010-73881 A

  By the way, a blue light emitting layer used for an organic EL (Electro Luminescence) including TFT and a liquid crystal shows broad light emission having a peak of about 450 nm, but the tail of the emission spectrum of blue light of the organic EL element continues to a wavelength of 420 nm. In consideration of the fact that the blue color filter allows light having a wavelength of 400 nm to pass through about 70%, it is required that the characteristic deterioration with respect to light irradiation in a wavelength region smaller than the wavelength 450 nm is low. If the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, a threshold shift of the transistor occurs.

  Here, for example, as a measure of stability against light irradiation, if a criterion that the absolute value | ΔVth | of the threshold shift amount for 420 nm light irradiation is 2 V or less is provided, | ΔVth | ≦ 2 V is set for 420 nm light irradiation. It is difficult to realize a TFT that satisfies the requirements.

  Specifically, Non-Patent Document 1 evaluates deterioration in characteristics of a TFT using conventional IGZO as an oxide semiconductor layer with respect to light irradiation, but the absolute value of the threshold shift amount with respect to light irradiation with a wavelength of 420 nm | ΔVth | exceeds 2V.

On the other hand, with an increase in display size and definition, there has been a demand for higher mobility of display driving TFTs (for example, more than 20 cm ² / Vs). High-functional displays that cannot be covered with (mobility of about 10 cmA ² / Vs) are also being proposed.

  In Patent Document 1, the first region as the current path layer (carrier traveling layer) contains IZO and ITO, and a high mobility TFT can be realized, but the light irradiation characteristic is not mentioned.

Moreover, in patent document 2, although the 1st area | region as a current path layer contains IGZO, the mobility is lower than ²⁰ cmA < ² > / Vs, and the light irradiation characteristic is not mentioned.

The present invention has been made in view of the above circumstances, and has a high mobility exceeding 20 cm ² / Vs and a high light stability in which the absolute value | ΔVth | of the threshold shift amount is 2 V or less with respect to light irradiation with a wavelength of 420 nm. An object of the present invention is to provide a method for manufacturing a field-effect transistor that achieves both compatibility.

The above-described problems of the present invention have been solved by the following means.
<1> A method for manufacturing a bottom-gate field effect transistor for forming a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, wherein the oxide semiconductor layer includes: As a formation process, a first film formation process for forming a first region including at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge; and In, Ga A second region containing at least one selected from the group consisting of Zn, Mg, Al, Sn, Sb, Cd, and Ge and having a lower electrical conductivity than the first region is a surface of the first region. And a second film forming step of sequentially adjusting a film forming pressure in the second region at least at the start of film formation to 2.0 Pa or more and 13.0 Pa or less. Transistor Manufacturing method.
<2> The method for producing a field effect transistor according to <1>, wherein in the second film formation step, a film formation pressure at the start of the film formation is adjusted to 5.0 Pa or more and less than 12.0 Pa.
<3> The method for manufacturing a field effect transistor according to <1> or <2>, wherein in the second film formation step, a film formation pressure at the start of the film formation is adjusted to 10.0 Pa or less.
<4> The method for producing a field effect transistor according to <3>, wherein in the second film formation step, a film formation pressure at the start of the film formation is adjusted to 8.0 Pa or less.
<5> In the second film-forming step, the film-forming pressure is switched to a pressure lower than the film-forming pressure at the start of film-forming during the film-forming, and any one of <1> to <4> The manufacturing method of the field effect transistor of description.
<6> Forming the second region up to the first film thickness of 5 nm at the film formation pressure at the start of film formation, and depositing the rest of the second region at a film formation pressure of less than 1.0 Pa. The method for producing a field effect transistor according to <5>.
<7> Any one of <1> to <6>, wherein the film thickness of the first region is 10 nm or less, and the film thickness of the second region is greater than or equal to the film thickness of the first region. A method for producing the field effect transistor according to claim 1.
<8> The field effect type according to any one of <1> to <7>, wherein the first film forming step forms the film so that In and Zn are included in the first region. A method for manufacturing a transistor.
<9> In the first film formation step and the second film formation step, the first region and the second region are formed so as to contain In, and the In atoms in the first region The method for producing a field effect transistor according to any one of <1> to <8>, wherein the composition ratio is higher than the In atom composition ratio of the second region.
<10> In the first film formation step and the second film formation step, the first region and the second region are formed such that Ga is contained, and Ga atoms in the first region are formed. The method for producing a field effect transistor according to any one of <1> to <9>, wherein the composition ratio is lower than the Ga atom composition ratio of the second region.
<11> In the first film formation step and the second film formation step, the first region and the second region are formed using a sputtering method while flowing a gas containing oxygen gas into the film formation chamber. And in said 1st film-forming process, oxygen gas of the quantity smaller than the flow volume of the oxygen gas sent at the time of said 2nd film-forming process is flowed, It is any one of said <1>-<10> A method of manufacturing a field effect transistor.
<12> Manufacturing of the field effect transistor according to <8>, including a heat treatment step of performing heat treatment at 300 ° C. to 600 ° C. during the oxide semiconductor layer formation step or after the second film formation step. Method.
<13> Any one of <1> to <11>, including a heat treatment step of performing heat treatment at 300 ° C. or higher and lower than 450 ° C. during the oxide semiconductor layer forming step or after the second film forming step. The manufacturing method of the field effect transistor of description.

According to the present invention, a field effect that achieves both high mobility exceeding 20 cm ² / Vs and high light stability in which the absolute value | ΔVth | of the threshold shift amount is 2 V or less with respect to light irradiation with a wavelength of 420 nm. A method for manufacturing a type transistor can be provided.

FIG. 1A is a schematic diagram showing an example of a top contact type TFT having a bottom gate structure, which is a TFT according to an embodiment of the present invention. FIG. 1B is a schematic diagram showing an example of a bottom contact type TFT with a bottom gate structure, which is a TFT according to an embodiment of the present invention. FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the invention. FIG. 3 is a schematic configuration diagram of electrical wiring of the liquid crystal display device shown in FIG. FIG. 4 is a schematic sectional view of a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the invention. FIG. 5 is a schematic configuration diagram of the electrical wiring of the electro-optical device shown in FIG. FIG. 6 is a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention. FIG. 7 is a schematic configuration diagram of electrical wiring of the sensor shown in FIG. FIG. 8A is a plan view of the TFT of the example and the comparative example, and FIG. 8B is a cross-sectional view of the TFT shown in FIG. FIG. 9 is a diagram illustrating the Vg-Id characteristics of the TFT according to the comparative example 1 when irradiated with monochrome light. FIG. 10 is a diagram illustrating the Vg-Id characteristics when the TFT according to Example 3 is irradiated with monochrome light. FIG. 11 is a graph showing the relationship between the light irradiation wavelength and ΔVth in the TFT according to the representative comparative example 1 and the TFT according to the example 3. FIG. 12 is a graph plotting the relationship between the deposition pressure and the threshold shift amount ΔVth (at a wavelength of 420 nm) based on Table 1.

  Hereinafter, a method for manufacturing a field effect transistor according to an embodiment of the present invention will be specifically described with reference to the accompanying drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals and description thereof is omitted as appropriate. In addition, the terms “upper” and “lower” used for the positional relationship in the following description are used for convenience and should not be constrained in the direction.

1. Configuration of Field Effect Transistor Before describing a method for manufacturing a field effect transistor according to an embodiment of the present invention, an outline of a configuration of a field effect transistor manufactured by the manufacturing method will be described. An example of a field effect transistor according to an embodiment of the present invention is a TFT.
A TFT according to an embodiment of the present invention includes a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode, and a drain electrode, and applies a voltage to the gate electrode to flow through the oxide semiconductor layer. It is an active element having a function of controlling current and switching current between a source electrode and a drain electrode. In the TFT according to the embodiment of the present invention, the oxide semiconductor layer further includes a first region in the film thickness direction and a second region disposed on the side farther from the gate electrode than the first region. I have. In the TFT of this embodiment, no layer other than the oxide semiconductor layer such as an electrode layer is inserted between the first region and the second region.

The TFT element structure includes a so-called reverse stagger structure (also referred to as a bottom gate type) and a stagger structure (also referred to as a top gate type) based on the position of the gate electrode. In this embodiment, the bottom gate type is used. TFT is used.
However, a bottom-gate TFT also has two modes, a so-called top contact type and a bottom contact type, based on contact portions between the oxide semiconductor layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate). However, any embodiment may be used.
Note that the top gate structure is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an oxide semiconductor layer is formed on the lower side of the gate insulating film. The gate electrode is disposed on the side, and the oxide semiconductor layer is formed on the upper side of the gate insulating film. The bottom contact type is a form in which the source / drain electrodes are formed before the oxide semiconductor layer and the lower surface of the oxide semiconductor layer is in contact with the source / drain electrodes. The top contact type is an oxide In this embodiment, the semiconductor layer is formed before the source / drain electrodes, and the upper surface of the oxide semiconductor layer is in contact with the source / drain electrodes.

  FIG. 1A is a schematic diagram showing an example of a bottom gate type top contact type TFT according to an embodiment of the present invention. In the TFT 10 illustrated in FIG. 1A, the gate electrode 14, the gate insulating film 16, the first region 18 </ b> A of the oxide semiconductor layer 18, and the second region of the oxide semiconductor layer 18 are formed on one surface in the thickness direction of the substrate 12. The regions 18B are sequentially stacked. The source electrode 20 and the drain electrode 22 are spaced apart from each other on (on the surface of) the second region 18B.

  FIG. 1B is a schematic diagram illustrating an example of a bottom-gate and bottom-contact TFT according to an embodiment of the present invention. In the TFT 30 illustrated in FIG. 1B, the gate electrode 14 and the gate insulating film 16 are sequentially stacked on one surface of the substrate 12 in the thickness direction. Further, the source electrode 20 and the drain electrode 22 are disposed on the surface of the gate insulating film 16 so as to be separated from each other, and further on the (surface) thereof, the first region 18A of the oxide semiconductor layer 18 and the oxide semiconductor The second region 18B of the layer 18 is sequentially stacked.

Note that the TFT according to this embodiment can have various configurations other than the above, and may have a configuration including a protective layer over an oxide semiconductor layer, an insulating layer over a substrate, and the like as appropriate. Good.
Further, the first region 18A and the second region 18B are distinguished from each other by a difference in contrast by a cross-sectional TEM (Transmission Electron Microscope) analysis of the oxide semiconductor layer 18, an ICP (Inductively Coupled Plasma) emission analyzer, It can be distinguished by the difference in composition and composition ratio by the fluorescent X-ray analyzer.

2. Manufacturing Method of Field Effect Transistor The manufacturing method of the bottom gate type field effect transistor (TFT 10 or TFT 30) described above includes the steps of forming the oxide semiconductor layer 18 as In, Ga, Zn, Mg, Al, Sn, A first film forming step of forming a first region 18A including at least one selected from the group consisting of Sb, Cd, and Ge; and In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge A second region 18B that includes at least one selected from the group consisting of and having a lower electrical conductivity than the first region 18A is formed on the surface of the first region 18A by sputtering, and the second region In this manufacturing method, at least a second film forming step of adjusting a film forming pressure at the start of film formation of 18B to 2.0 Pa or more and 13.0 Pa or less is performed.
According to such a manufacturing method, by using a stacked structure of the first region 18A and the second region 18B having electric conductivity smaller than that of the first region, the first region 18A is so-called “carrier traveling”. The second region 18B becomes a so-called “resistance layer”.
The first region 18A serving as the “carrier traveling layer” has TFT characteristics, in particular, light defects caused by damage (for example, plasma damage) received during film formation, as compared with the second region 18B serving as the “resistance layer”. The effect on the irradiation characteristics is considered to be large.
In the present embodiment, at least at the start of film formation in the second film formation process, the film formation pressure adjusted to 2.0 Pa or more and 13.0 Pa or less on the surface of the first region 18A formed by the first film formation process. Thus, since the second region 18B is formed, it is possible to reduce film formation damage (for example, plasma damage) on the surface of the first region 18A. As a result, it is possible to achieve both high mobility exceeding 20 cm ² / Vs and high light stability in which the absolute value | ΔVth | of the threshold shift amount is 2 V or less with respect to light irradiation with a wavelength of 420 nm.
The high mobility and high light stability means that the TFTs 10 and 30 of this embodiment can be suitably used for driving TFTs for large-area, high-definition transparent displays. . Further, it is not necessary to provide a light blocking layer in the organic EL or LCD driving TFT, and the manufacturing cost can be greatly reduced.

“Electrical conductivity” is a physical property value that represents the ease of electrical conduction of a substance. When a drug model is assumed where the carrier concentration n of the substance is e, the elementary charge is e, and the carrier mobility is μ, The electrical conductivity σ of the substance is expressed by the following formula.
σ = neμ
When the first region 18A or the second region 18B is an n-type semiconductor, the carriers are electrons, the carrier concentration indicates the electron carrier concentration, and the carrier mobility indicates the electron mobility. Similarly, in the case where the first region 18A or the second region 18B is a p-type semiconductor, the carriers are holes, the carrier concentration indicates the hole carrier concentration, and the carrier mobility indicates the hole mobility. The carrier concentration and carrier mobility of the substance can be obtained by Hall measurement.
The electrical conductivity can be determined by measuring the sheet resistance of the film whose thickness is known. Although the electrical conductivity of a semiconductor varies with temperature, the electrical conductivity described in the text indicates the electrical conductivity at room temperature (20 ° C.).
The “film formation pressure” refers to the pressure during film formation in the film formation chamber of the sputtering apparatus.
“Plasma damage” is physical damage caused by argon gas and oxygen gas (ionization by applying an electric field) ions introduced during film formation, and the influence of argon ions is greater because they have a larger mass than oxygen ions. .

  As a representative example of the manufacturing method of the field effect transistor as described above, a manufacturing method of the bottom gate type top contact type TFT 10 shown in FIG. 1A will be specifically described. The same method can be applied to the manufacturing method of the TFT 30.

-Step of forming gate electrode 14-
First, as shown in FIG. 1A, after preparing a substrate 12 for forming the TFT 10, the gate electrode 14 is formed on one main surface in the thickness direction of the substrate 12. Perform the process.
There is no restriction | limiting in particular about the shape of the board | substrate 12 to prepare, a structure, a magnitude | size, etc., It can select suitably according to the objective. The structure of the substrate 12 may be a single layer structure or a laminated structure. As the substrate 12, for example, glass, YSZ (yttrium stabilized zirconium), inorganic materials such as Si, resin such as polyethylene terephthalate, polyethylene naphthalate, polyimide, or composite plastic with clay mineral or particles having a mica-derived crystal structure A substrate made of a resin composite material such as a material can be used. Among these, a substrate made of a resin or a resin composite material is preferable in terms of light weight and flexibility. Note that the resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion to the lower electrode, and the like.

In forming the gate electrode 14, first, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD method or a plasma CVD method, or the like. A conductive film is formed according to a method appropriately selected in consideration of suitability with the material to be used. After film formation, the gate electrode 14 is formed from the conductive film by patterning the conductive film into a predetermined shape by photolithography, an etching method, a lift-off method, or the like. At this time, it is preferable to pattern the gate electrode 14 and the gate wiring simultaneously.
The conductive film constituting the gate electrode 14 is preferably a conductive film having high conductivity, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, Au, Al—Nd, Ag alloy, tin oxide, A metal oxide conductive film such as zinc oxide, indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO) can be used as a single layer or a stacked structure of two or more layers.

—Process for Forming Gate Insulating Film 16—
After the gate electrode 14 is formed, a step of forming the gate insulating film 16 is performed in which the gate insulating film 16 is formed on the gate electrode 14 and the exposed surface of the substrate 12.
In forming the gate insulating film 16, the same formation method as the formation method of the gate electrode 14 can be used.
The insulating film constituting the gate insulating film 16 is preferably highly insulating, for example, an insulating film such as SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ , Alternatively, an insulating film including at least two of these compounds may be used.

—Oxide Semiconductor Layer 18 Formation Step—
After the gate insulating film 16 is formed, an oxide semiconductor layer 18 forming step is performed in which the oxide semiconductor layer 18 is formed on the surface of the gate insulating film 16.

  In this formation step, the oxide semiconductor layer 18 may be formed of either an amorphous film or a crystalline film. However, in the case of an amorphous film, since it can be formed at a low temperature, it is preferably formed on the flexible substrate 12. In the case of an amorphous film, a crystal grain boundary does not exist and a highly uniform film can be obtained. Note that whether or not the oxide semiconductor layer 18 is an amorphous film can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, the oxide semiconductor layer 18 can be determined to be an amorphous film.

  The film thickness (total film thickness) including the first region 18A and the second region 18B in the oxide semiconductor layer 18 is not particularly limited, but it is possible to realize film uniformity and the total in the oxide semiconductor layer 18. From the viewpoint of easy adjustment of the carrier concentration, it is preferable that the carrier concentration is 10 nm or more and 200 nm or less.

  In the formation process of the oxide semiconductor layer 18, the first film formation process and the second film formation process are sequentially performed. In addition, you may perform intermediate processing processes, such as a patterning process and heat processing, between a 1st film-forming process and a 2nd film-forming process.

-First film formation process-
The first film formation step includes at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge (for example, In—Ga—Zn—O, In—Zn—O). In-Ga-O, In-Sn-O, In-Sn-Zn-O, In-Ga-Sn-O, In-O, etc.) a first region 18A is formed.

As a film formation method for the first region 18A, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. Is mentioned. Among these, it is preferable to use a vapor deposition method such as a vacuum deposition method, a sputtering method, an ion plating method, a CVD method or a plasma CVD method from the viewpoint of easy control of the film thickness. Among vapor phase film forming methods, sputtering method and pulsed laser deposition method (PLD method) are more preferable. Furthermore, the sputtering method is more preferable from the viewpoint of mass productivity.
In the case of the sputtering method, the input power is not particularly limited to DC / RF. In the sputtering method, film formation with a single target whose composition is adjusted and film formation by co-sputtering using a plurality of targets are possible, but a single target is preferable. In the case of co-sputtering, both DC / RF are used. For example, in the case of the IGZO system, In ₂ O ₃ and ZnO are DC sputtering, and Ga ₂ O ₃ is RF sputtering. Further, in order to control the conductivity of the obtained film, the oxygen partial pressure in the film formation chamber at the time of film formation is arbitrarily controlled. As a method for controlling the oxygen partial pressure in the film formation chamber, a method of changing the amount of O ₂ gas introduced into the film formation chamber may be used, or a method of changing the introduction amount of oxygen radicals or ozone gas may be used. . If resistance is high even when the introduction of oxygen gas is stopped, a reducing gas such as H ₂ or N ₂ may be introduced. In the case where oxygen radicals are used, it is more effective to inject directly onto the film formation substrate in relation to the film formation pressure and the mean free process.

  In the first film formation step, it is preferable to form a film so that at least one of In, Ga, Sn, Zn, and Cd is included, and at least one of In, Sn, Zn, and Ga is included. It is preferable to form a film so that at least one of In, Ga, and Zn is included (for example, an In—O system). Further, it is preferable to form a film so that at least In is contained.

In particular, in the first film formation step and the second film formation step described later, the first region 18A and the second region 18B are formed so as to contain In, and the In atom composition in the first region 18A. The ratio is preferably higher than the In atom composition ratio of the second region 18B. This is because by increasing the In composition ratio of the first region 18A, a tendency that the electron affinity is relatively increased is obtained, and the conduction carriers are easily concentrated in the first region 18A. In addition, it is easier to obtain a high carrier mobility because increasing the In content makes it easier to increase the conductive carrier concentration.
From the same point of view, in the first film formation step and the second film formation step described later, the first region 18A and the second region 18B are formed so as to contain Ga, and the first region 18A is formed. It is preferable that the Ga atom composition ratio is lower than the Ga atom composition ratio of the second region 18B.
From the same point of view, in the first film formation step and the second film formation step described later, the first region 18A and the second region 18B are formed while flowing a gas containing oxygen into the film formation chamber using a sputtering method. In the first film formation step, it is preferable to flow an oxygen gas in an amount smaller than the flow rate of the oxygen gas that flows during the second film formation step.
In addition, about the said composition, a composition ratio, and a film thickness, it can confirm with a fluorescent X ray analyzer.

  In the first film formation step, the first region 18A is formed so as to include at least two selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge. It is preferable (for example, In—Zn—O system, In—Ga—O system, Ga—Zn—O system), and in particular, from the viewpoint that the threshold shift amount can be remarkably suppressed with respect to light irradiation with a wavelength of 420 nm. It is preferable to form a film so that In and Zn are contained in the region 18A.

Furthermore, in the first film formation step, it is preferable to form a film so that the first region 18A contains all of In, Ga (or Sn), and Zn. That is, the composition of the first region 18A preferably includes In _(a) Ga _(b) Zn _(c) O _(d) (a, b, c, d> 0).
In particular, the first region 18A preferably includes In, Ga (or Sn), Zn, and O as main constituent elements. The “main constituent element” means that the composition ratio of In, Ga (or Sn), Zn, and O with respect to all the constituent elements in the first region 18A is 98% or more of the whole. . Accordingly, the first region 18A may also contain other elements such as Mg as described later.

  In the first film formation step, it is preferable to form the film so that the film thickness of the first region 18A is 10 nm or less. As described above, the first region 18A is preferably made of IZO or an extremely in-rich IGZO film that can easily achieve high mobility as described above. However, since such a high mobility film has a high carrier concentration, it is pinched off. Is relatively difficult, and the threshold value may be greatly shifted to the negative side. Therefore, by setting the film thickness of the first region 18A to 10 nm or less, it is possible to avoid that the total carrier concentration in the oxide semiconductor layer 18 becomes excessive and pinch-off is difficult.

The electrical conductivity of the first region 18A is preferably 10 ⁻⁶ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ . More preferably, it is 10 ⁻⁴ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ , and further preferably 10 ⁻¹ Scm ⁻¹ or more and less than 10 ² Scm ⁻¹ .

-Second film formation process-
In the second film formation step, the second film having at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge and having lower electrical conductivity than the first region 18A. The region 18B is formed on the surface of the first region 18A by a sputtering method, and the film formation pressure at least at the start of film formation in the second region 18B is adjusted to 2.0 Pa or more and 13.0 Pa or less.

  Unlike the first film forming process, the film forming method of the second region 18B in the second film forming process is premised on using a sputtering method. The preferable conditions for the sputtering method are the same as those described in detail in the first film formation step. It is preferable to perform sputtering film formation in succession from the viewpoint of improving productivity, suppression of impurity contamination, and film formation in the first film formation process and the second film formation process.

The film formation pressure at the start of film formation in the second film formation step is preferably 5.0 Pa or more and less than 12.0 Pa. This is because the absolute value | ΔVth | of the threshold shift amount is 1 V or less with respect to light irradiation with a wavelength of 420 nm. In addition, when the film formation pressure at the start of film formation is adjusted to 5.0 Pa or more, the dependency of the threshold shift amount on the light irradiation with a wavelength of 420 nm can be relaxed. That is, if the film forming pressure is 5.0 Pa or more, even if the film forming pressure fluctuates, fluctuations in the threshold shift amount can be suppressed.
Moreover, it is preferable to adjust the film formation pressure at the start of film formation in the second film formation step to 10.0 Pa or less. This is because even if the deposition pressure fluctuates within the range of 10.0 Pa or less, fluctuations in the threshold shift amount can be suppressed.

  Furthermore, it is preferable to adjust the film formation pressure at the start of film formation in the second film formation step to 8.0 Pa or less. It is because it can suppress that the film-forming speed falls extremely. The relationship between the deposition pressure and the deposition rate is such that the deposition rate decreases as the deposition pressure increases from approximately 1 Pa or higher.

In the second film formation step, it is preferable to switch the film formation pressure to a pressure lower than the film formation pressure at the start of film formation during the film formation from the viewpoint of shortening the film formation time. Specifically, the second region 18B is deposited up to the first 5 nm at the deposition pressure at the start of deposition, and the remaining second region 18B is deposited at a deposition pressure of less than 1.0 Pa.
Thus, at the start of film formation, the film formation pressure is adjusted to 2.0 Pa or more and 13.0 Pa or less to slowly form the second region 18B while suppressing plasma damage to the first region 18A. From the middle of the film, since the plasma damage is unlikely to contribute to the first region 18A due to the presence of a part of the second region 18B on the surface of the first region 18A, the film forming pressure is reduced to less than 1.0 Pa. The remaining second region 18B can be formed quickly and the film formation time can be shortened.

  The film thickness of the second region 18B is preferably greater than or equal to the film thickness of the first region 18A (eg, 10 nm or less). In particular, if it exceeds 10 nm, reduction of off-current and suppression of deterioration of S value can be expected. The film thickness of the second region 18B is preferably 120 nm or less, particularly less than 70 nm. This is because the resistance of the source / drain electrodes 20 and 22 and the first region 18A can be prevented from increasing, resulting in a decrease in mobility.

  The preferable conditions for the composition of the second region 18B are the same as those described in detail in the first film formation step. For example, in the second film formation step, it is preferable to form the film so that the second region 18B contains all of In, Ga (or Sn), and Zn.

The ultimate vacuum when the first region 18A and the second region 18B are formed by sputtering is not particularly limited, but is preferably 2.0 × 10 ⁻⁵ Pa or less, and about 1.0 × 10 ⁻⁶ Pa. More preferred. Since the H ₂ O component corresponding to the degree of vacuum is taken into the thin film and the carrier density changes depending on the degree of vacuum, the degree of vacuum is preferable in order to further enhance the effect of this embodiment.
In addition, the distance between the substrate 12 and the target when the first region 18A and the second region 18B are formed by sputtering is such that the lines of magnetic force cross the substrate and the sample folder, and the plasma becomes unstable (causes the density to decrease). From the viewpoint of suppressing the thickness, it is preferably 50 mm or more. In addition, the distance is preferably 150 mm or less from the viewpoint of suppressing a decrease in the film formation rate to a film formation rate suitable for manufacturing.

The electric conductivity of the second region 18B can assume the same range as that of the first region 18A on the assumption that the electric conductivity of the second region 18B is lower than that of the first region 18A, but is preferably 10 ⁻⁷ Scm ⁻¹ or more and 10 ¹ Scm. Less than ^-1 . More preferably, it is 10 ⁻⁷ Scm ⁻¹ or more and less than 10 ⁻¹ Scm ⁻¹ .

In addition, the carrier concentration (in other words, electric conductivity) of each region of the oxide semiconductor layer 18 can be controlled not only by composition modulation but also by oxygen partial pressure control during film formation.
Specifically, the oxygen concentration can be controlled by controlling the oxygen partial pressure during film formation in the first region 18A and the second region 18B, respectively. If the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be reduced, and a reduction in off-current can be expected accordingly. On the other hand, if the oxygen partial pressure during film formation is lowered, the carrier concentration can be increased, and an increase in field effect mobility can be expected accordingly. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after forming the second region 18B, it is possible to promote the oxidation of the film and reduce the amount of oxygen vacancies in the second region 18B. .
Further, for example, by doping a part of Zn contained in the oxide semiconductor layer 18 with element ions having a wider band gap, light irradiation stability accompanying an increase in the optical band gap can be imparted. Specifically, the band gap of the film can be increased by doping Mg. For example, by doping Mg in each region of the oxide semiconductor layer 18, the band gap can be increased while maintaining the band profile of the laminated film, compared to a system in which the composition ratio of In, Ga, Zn, etc. is controlled. It is.

And since the blue light emitting layer used for organic EL shows broad light emission having a peak at a wavelength of about 450 nm, the optical band gap of the oxide semiconductor layer 18 is relatively narrow, and the region has optical absorption. This causes a problem that a threshold shift of the transistor occurs. Accordingly, it is preferable that the material used for the oxide semiconductor layer 18 has a larger band gap, particularly for a TFT used for driving an organic EL.
Further, the carrier concentration in the first region 18A and the like can be arbitrarily controlled by cation doping. In order to increase the carrier concentration, a material (eg, Ti, Zr, Hf, Ta, etc.) that tends to be a cation having a relatively large valence may be doped. However, when doping a cation having a large valence, the number of constituent elements of the oxide semiconductor film increases, which is disadvantageous in terms of simplifying the film formation process and reducing the cost. ) To control the carrier concentration.

-Patterning process-
Next, a patterning process for patterning the oxide semiconductor layer 18 is performed. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed on the remaining portion by photolithography, and the pattern is formed by wet etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid and acetic acid. Further, patterning may be performed using dry etching, and there is no particular limitation. Note that the patterning of the oxide semiconductor layer 18 may be performed at any time with respect to the first region 18A after the first film formation step and with respect to the second region 18B after the second film formation step. From the viewpoint of suppressing etching damage and the like in the region, it is preferable to pattern the first region 18A and the second region 18B after the second film formation step.
In addition, without using photolithography and etching patterning methods, patterning using a metal mask that can be patterned simultaneously with sputter film formation in the first film formation process and the second film formation process in accordance with the application (resolution). A method can also be used.

-Heat treatment process-
It is preferable to perform a heat treatment step of heat-treating the substrate 12 during the formation step of the oxide semiconductor layer 18 or after the second film formation step. Note that “heat treatment during the formation process of the oxide semiconductor layer 18” refers to heating of the substrate during film formation. Further, the “heat treatment after the second film formation step” may be performed immediately after the formation of the oxide semiconductor layer 18 or after the formation of the source / drain electrodes 20 and 22 to be described later is completed.
The heat treatment temperature is preferably 300 ° C. or higher and 600 ° C. or lower in order to suppress variation in electrical characteristics. The atmosphere during post-annealing is preferably an oxygen-containing atmosphere, and an oxidizing atmosphere or an inert atmosphere can be used in an oxidizing atmosphere. When post-annealing is performed in an oxidizing atmosphere, oxygen in the oxide semiconductor layer is difficult to escape, generation of excess carriers is suppressed, and variations in electrical characteristics are less likely to occur. The heat treatment may be performed for each substrate, or a plurality of heat treatments may be performed using a clean oven or the like. Further, when the temperature is 600 ° C. or lower, cation mutual diffusion occurs between the first region 18A and the second region 18B, and the two regions can be prevented from crossing each other.
Whether or not cation mutual diffusion occurs in the first region 18A and the second region 18B can be confirmed, for example, by performing analysis by a cross-sectional TEM. In addition, the heat treatment step can be omitted.

  In particular, the heat treatment temperature is preferably 300 ° C. or higher and lower than 450 ° C. This is because the TFT operates more reliably regardless of the composition of the first region.

  Further, when the humidity of the heat treatment atmosphere is extremely high, moisture is easily taken into the film, and variations in electrical characteristics are likely to occur. Therefore, the relative humidity at room temperature is preferably 50% or less. Furthermore, although there is no particular limitation on the heat treatment time, it is preferable to hold at least 10 minutes in consideration of the time required for the film temperature to become uniform.

-Electrode formation process-
After the formation process of the oxide semiconductor layer 18 or after the heat treatment process, an electrode formation process is performed in which the source electrode 20 and the drain electrode 22 are formed over the second region 18B. However, from the viewpoint of ohmic contact formation, it is preferable to perform a heat treatment step after the electrode formation step. In the electrode formation step, the same formation method as that for the gate electrode can be used.
The conductive film constituting the source / drain electrodes 20 and 22 is made of a highly conductive material, for example, Al, Mo, Cr, Ta, Ti, Au, Au or other metals, Al—Nd, Ag alloy, tin oxide. , Zinc oxide, indium oxide, indium tin oxide (ITO), metal oxide conductive film such as zinc indium oxide (IZO), or the like can be used. As the source / drain electrodes 20 and 22, these conductive films can be used as a single layer structure or a laminated structure of two or more layers.

In the etching in the electrode forming step, a protective film for etching protection may be provided on the oxide semiconductor layer 18. The protective film may be formed continuously with the oxide semiconductor layer 18 or may be formed after the patterning of the oxide semiconductor layer 18.
Note that by using the TFT 10 of this embodiment, high mobility and high light irradiation stability can be obtained without using a protective film or the like on the oxide semiconductor layer 18 for reducing deterioration in characteristics due to light irradiation. Needless to say, the oxide semiconductor layer 18 may be provided with a protective film as described above. For example, it is possible to further improve the stability against light irradiation by providing a protective film that absorbs and reflects light in the ultraviolet region (wavelength 400 nm or less).

  Through the above procedure, a bottom gate type top contact type TFT 10 as shown in FIG. 1A can be manufactured. Further, according to the TFT manufacturing method of the present embodiment, the first region 18A and the second region 18B can be formed at a low temperature (for example, 400 ° C. or less) by using the constituent materials, and therefore the substrate 12 is also a resin substrate. Etc., the TFT 10 as a whole can be manufactured at a low temperature.

  Although the present invention has been described in detail with respect to specific embodiments, the present invention is not limited to such embodiments, and various other embodiments are possible within the scope of the present invention. It will be apparent to those skilled in the art, and for example, the plurality of embodiments described above can be implemented in combination as appropriate.

3. Applications There are no particular limitations on the use of the field effect transistor manufactured in the present embodiment described above. For example, electro-optical devices (for example, liquid crystal display devices, organic EL (Electro Luminescence) display devices, inorganic EL display devices) It is suitable for use in a driving element, particularly a large area device.
Furthermore, the field effect transistor of the embodiment is particularly suitable for a device that can be manufactured by a low-temperature process using a resin substrate (for example, a flexible display), various sensors such as an X-ray sensor, MEMS (Micro Electro Mechanical System), and the like. The present invention is suitably used as a drive element (drive circuit) in various electronic devices.

4). Electro-optical device and sensor The electro-optical device or sensor according to the present embodiment includes the above-described field-effect transistor (TFT 10).
Examples of electro-optical devices include display devices (eg, liquid crystal display devices, organic EL display devices, inorganic EL display devices, etc.).
As an example of the sensor, an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), an X-ray sensor, or the like is suitable.
Both the electro-optical device and the sensor using the TFT of this embodiment have high in-plane uniformity of characteristics. The “characteristic” referred to here is a display characteristic in the case of an electro-optical device (display device), and a sensitivity characteristic in the case of a sensor.
Hereinafter, a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of the electro-optical device or sensor including the field effect transistor manufactured according to the present embodiment.

5. 2. Liquid Crystal Display Device FIG. 2 is a schematic sectional view of a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and FIG. 3 is a schematic configuration diagram of the electric wiring.

  As shown in FIG. 2, the liquid crystal display device 100 of this embodiment includes the bottom gate type top contact type TFT 10 and the oxide semiconductor layer 18 protected by the passivation layer 102 of the TFT 10 shown in FIG. A liquid crystal layer 108 sandwiched between the pixel lower electrode 104 and the opposed upper electrode 106 and an RGB color filter 110 for developing different colors corresponding to each pixel are provided, and the substrate 10 side of the TFT 10 and the RGB color are provided. The filter 110 includes polarizing plates 112a and 112b, respectively.

  As shown in FIG. 3, the liquid crystal display device 100 according to the present embodiment includes a plurality of gate lines 112 that are parallel to each other and data lines 114 that are parallel to each other and intersect the gate lines 112. Here, the gate wiring 112 and the data wiring 114 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 112 and the data wiring 114.

  The gate electrode 14 of the TFT 10 is connected to the gate wiring 112, and the source electrode 20 of the TFT 10 is connected to the data wiring 114. Further, the drain electrode 22 of the TFT 10 is connected to the pixel lower electrode 104 via a contact hole 116 provided in the gate insulating film 16 (a conductor is embedded in the contact hole 116). The pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.

  Since the TFT of this embodiment has a very high stability during light irradiation, the reliability of the liquid crystal display device is increased.

6). Organic EL Display Device FIG. 4 is a schematic sectional view of a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 5 is a schematic configuration diagram of electric wiring.

  There are two types of driving methods for organic EL display devices: a simple matrix method and an active matrix method. The simple matrix method has an advantage that it can be manufactured at low cost. However, since the pixels are emitted by selecting one scanning line at a time, the number of scanning lines and the light emission time per scanning line are inversely proportional. Therefore, it is difficult to increase the definition and increase the screen size. The active matrix method has a high manufacturing cost because a transistor and a capacitor are formed for each pixel. However, since there is no problem that the number of scanning lines cannot be increased unlike the simple matrix method, it is suitable for high definition and large screen.

  In the active matrix organic EL display device 200 of this embodiment, a bottom gate type top contact type TFT 10 shown in FIG. 1A is provided on a substrate 12. The substrate 12 is, for example, a flexible support, and is a plastic film such as PEN, and has a substrate insulating layer 202 on the surface in order to be insulating. A patterned color filter layer 204 is disposed thereon. The driving TFT portion has a gate electrode 14, and a gate insulating film 110 is provided on the gate electrode 14. A connection hole is opened in part of the gate insulating film 16 for electrical connection. An oxide semiconductor layer 18 is provided in the driving TFT portion, and a source electrode 20 and a drain electrode 22 are provided thereon. The drain electrode 22 and the pixel electrode (anode) 206 of the organic EL element are continuous and integrated, and are formed by the same material and the same process. The drain electrode 22 of the switching TFT and the driving TFT are electrically connected through a connection hole by a connection electrode 208. Further, the whole is covered with the insulating film 210 except for the portion where the organic EL element of the pixel electrode portion is formed. On the pixel electrode portion, an organic layer 212 including a light emitting layer and a cathode 214 are provided to form an organic EL element portion.

  Further, as shown in FIG. 5, the organic EL display device 200 according to the present embodiment includes a plurality of gate wirings 220 that are parallel to each other, and a data wiring 222 and a driving wiring 224 that are parallel to each other and intersect the gate wiring 220. I have. Here, the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated. The gate electrode 14 of the switching TFT 10 b is connected to the gate wiring 220, and the source electrode 20 of the switching TFT 10 b is connected to the data wiring 222. Further, the drain electrode 22 of the switching TFT 10b is connected to the gate electrode 14 of the driving TFT 10, and the driving TFT 10a is kept on by using the capacitor 226. The source electrode 20 of the driving TFT 10 a is connected to the driving wiring 224, and the drain electrode 22 is connected to the organic layer 212.

  Since the TFT manufactured according to the present invention has very high stability during light irradiation, it is suitable for manufacturing a highly reliable organic EL display device.

  In the organic EL display device shown in FIG. 4, the top electrode of the organic layer 212 may be a top emission type with a transparent electrode, or the bottom electrode of the organic layer 212 and each electrode of the TFT may be transparent electrodes. It may be an emission type.

7). X-ray sensor FIG. 6 shows a schematic sectional view of a part of an X-ray sensor which is an embodiment of the sensor of the present invention, and FIG. 7 shows a schematic configuration diagram of its electric wiring.

  More specifically, FIG. 6 is a schematic cross-sectional view in which a part of the X-ray sensor array is enlarged. The X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed. A passivation film 308 is provided on the TFT 10.

  The capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314. The capacitor upper electrode 314 is connected to one of the source electrode 20 and the drain electrode 22 (the drain electrode 22 in FIG. 6) of the TFT 10 through a contact hole 318 provided in the insulating film 316.

The charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
The X-ray conversion layer 304 is a layer made of amorphous selenium, and is provided so as to cover the TFT 10 and the capacitor 310.
The upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.

  As shown in FIG. 7, the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that are parallel to each other and intersect the gate wiring 320. Here, the gate wiring 320 and the data wiring 322 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.

  The gate electrode 14 of the TFT 10 is connected to the gate wiring 320, and the source electrode 20 of the TFT 10 is connected to the data wiring 322. The drain electrode 22 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.

  In the X-ray sensor 300 of this embodiment, X-rays are irradiated from the upper part (upper electrode 306 side) in FIG. 6, and electron-hole pairs are generated in the X-ray conversion layer 304. By applying a high electric field to the X-ray conversion layer 304 by the upper electrode 306, the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.

  Since the X-ray sensor 300 of the present embodiment includes the TFT 10 having high stability during light irradiation, an image having excellent uniformity can be obtained.

  Examples will be described below, but the present invention is not limited to these examples.

<Depending on TFT characteristics of film formation pressure in second region>
-Production of TFTs according to Examples 1 to 10 and Comparative Examples 1 to 4-
First, the film formation pressure dependence of the second region with respect to the TFT characteristics was verified by fabricating bottom gate type top contact type TFTs according to Examples 1 to 5 and Comparative Examples 1 to 3 described below.

  FIG. 8A is a plan view of the TFT of the example and the comparative example, and FIG. 8B is a cross-sectional view of the TFT shown in FIG.

First, in Examples 1 to 5 and Comparative Examples 1 to 3, as shown in FIGS. 8A and 8B, a p-type Si substrate 502 with a thermal oxide film 504 (1 inch angle × 1 mm, thickness) as a substrate. : 525 μmt, thermal oxide film (SiO ₂ ): 100 nm), and a simple TFT 500 using the thermal oxide film 504 as a gate insulating film was manufactured.
Specifically, the first region 506 and the second region 508 of the oxide semiconductor layer are formed on a p-type Si substrate 502 with a thermal oxide film by using three types of targets of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO. A film was formed by co-sputtering while covering a portion other than the film formation portion of each region with a metal mask (first film formation process and second film formation process). The film forming conditions in each region are as follows.

-Film formation conditions in the first film formation step (first region 506)-
In; Ga: Zn composition ratio = 1.0: 1.0: 1.0,
Film thickness: 10nm
Plane size: 3mm x 4mm
Deposition pressure: 0.4 Pa
Ultimate vacuum: 8.0 × 10 ⁻⁶ Pa,
Deposition temperature: room temperature (25 ° C.)
Ar flow rate; 5.07 × 10 ⁻² Pa · m ³ / s,
O ₂ flow rate; 3.38 × 10 ⁻⁴ Pa · m ³ / s
Distance between substrate and target; 120mm

-Film-forming conditions of the second film-forming step (second region 508)-
In: Ga: Zn composition ratio = 0.5: 1.5: 1.0,
Film thickness: 50nm
Plane size: 3mm x 4mm
Deposition pressure: variable (Comparative Example 1; 0.4 Pa, Comparative Example 2; 1.0 Pa, Example 1; 2.0 Pa, Example 2; 5.0 Pa, Example 3; 10.0 Pa, Example 4; 12.0 Pa, Example 5; 13.0 Pa, Comparative Example 3; variable to 8 values of 15.0 Pa)
Ultimate vacuum: 8.0 × 10 ⁻⁶ Pa,
Deposition temperature: room temperature (25 ° C.)
Ar flow rate; 5.07 × 10 ⁻² Pa · m ³ / s,
O ₂ flow rate; 3.38 × 10 ⁻⁴ Pa · m ³ / s
Distance between substrate and target; 120mm

The film formation pressure was controlled by a diaphragm valve by reading the degree of vacuum in the film formation chamber. Since the signal to the diaphragm valve is controlled so as to become a set pressure by the pressure controller, two kinds of accuracy are required for the degree of vacuum, that is, the accuracy of the vacuum gauge of the film forming chamber and the diaphragm valve pressure controller.
Here, the vacuum gauge uses a digital capacitance gauge M-340DG-QA / C70 manufactured by Canon Anelva with a measurement error of 1%, and the pressure controller for the diaphragm valve uses a valve controller PM-5 manufactured by VAT Corporation with a measurement error of 0.028 Pa. Was used.
Therefore, when the target film forming pressure is x [Pa], the error in the film forming pressure is x × 0.01 + 0.028 [Pa].

The composition ratio was adjusted by controlling the power input to each target. Moreover, the value of the composition ratio used was obtained by a fluorescent X-ray analyzer.
In addition, the spread resistance measurement was performed on the film formation samples prepared by performing film formation under the same conditions as those of the first region 506 and the second region 508 according to Examples 1 to 5 and Comparative Examples 1 to 3. It was confirmed that the electrical resistivity of the first region 506 was lower than the electrical resistivity of the second region 508. That is, it was confirmed that the electrical conductivity of the second region 508 is smaller than the electrical conductivity of the first region 506. Further, it was confirmed by X-ray diffraction measurement that all the first regions 506 and the second regions 508 were amorphous films.

  Thereafter, source / drain electrodes 510 and 512 each having a size of 1 mm × 1 mm and a distance between electrodes of 0.2 mm were formed on the surface of the second region 508 by sputtering. The source / drain electrodes 510 and 512 were formed by pattern film formation using a metal mask. After depositing 10 nm of Ti, 50 nm of Au was deposited.

After the electrode layer was formed, a heat treatment step was performed in an electric furnace capable of controlling the atmosphere while maintaining 350 ° C. for 1 hour under an atmospheric pressure (Ar: O ₂ = 4: 1) atmosphere.

Thus, the bottom gate type top contact type TFT 500 according to Examples 1 to 5 and Comparative Examples 1 to 3 was obtained.

-Evaluation-
About each produced TFT500, the semiconductor characteristic analyzer 4156C (made by Agilent Technologies) was used, and the transistor characteristic (Vg-Id characteristic) and the mobility (micro | micron | mu) were measured. Vg-Id characteristics are measured by fixing the drain voltage (Vd) to 10 V, sweeping the gate voltage (Vg) within the range of -30 V to +30 V, and measuring the drain current (Id) at each gate voltage (Vg). I went to do it. The mobility is linear mobility from the Vg-Id characteristic in the linear region obtained by sweeping the gate voltage (Vg) in the range of -30V to + 30V with the drain voltage (Vd) fixed at 1V. Is calculated and written.

  Moreover, the stability of the TFT characteristic with respect to light irradiation was evaluated by irradiating each TFT 500 produced with monochromatic light with variable wavelength.

In this stability evaluation, each TFT 500 was placed on a probe stage stage and dried air was allowed to flow for 2 hours or more, and then TFT characteristics were measured in the dried air atmosphere. The irradiation intensity of the monochrome light source is 10 μW / cm ² , the wavelength λ is in the range of 360 to 700 nm, and the light irradiation is performed by comparing the Vg-Id characteristics when the monochrome light is not irradiated and the Vg-Id characteristics when the monochrome light is irradiated. Stability (ΔVth) was evaluated. The measurement conditions for TFT characteristics under monochrome light irradiation were fixed at Vds = 10 V and measured by sweeping the gate voltage in the range of Vg = -15 to 15V. Unless otherwise specified below, all measurements are performed after irradiating with monochromatic light for 10 minutes. The threshold shift amount ΔVth for light irradiation of 420 nm was used as an index of light stability of the TFT 500.

  Typical Vg-Id characteristics among the measurement results of the Vg-Id characteristics during monochrome light irradiation are shown in FIGS. The Vg-Id characteristics of FIG. 9 are those of the TFT according to Comparative Example 1, and the Vg-Id characteristics of FIG. 10 are those of the TFT according to Example 3. FIG. 11 is a graph showing the relationship between the light irradiation wavelength and ΔVth in the TFT according to the representative comparative example 1 and the TFT according to the example 3.

  As shown in FIGS. 9 and 10, it can be seen that the Vg-Id characteristic shifts to the minus side as the irradiation wavelength becomes shorter. As shown in FIG. 11, it can be seen that the threshold shift increases as the irradiation wavelength becomes shorter.

  Table 1 below shows the threshold shift amount ΔVth (at a wavelength of 420 nm) obtained from the mobility and the IV characteristics before and after the monochrome light irradiation when the film forming pressure in the second film forming process is modulated. The measurement results are summarized. FIG. 12 is a graph plotting the relationship between the deposition pressure and the threshold shift amount ΔVth (at a wavelength of 420 nm) based on Table 1.

  As shown in Table 1 and FIG. 12, in the TFTs of Comparative Examples 1 to 3 in which the film formation pressure in the second region 508 in the second film formation step is less than 2.0 Pa or more than 13.0 Pa, with respect to light irradiation with a wavelength of 420 nm. In the TFTs of Examples 1 to 5 in which the absolute value | ΔVth | of the threshold shift amount exceeds 2 V but the film formation pressure in the second region 508 is 2.0 Pa or more and 13.0 Pa or less, the threshold for light irradiation The absolute value | ΔVth | of the shift amount was 2 V or less.

In addition, the mobility of both the TFTs of Examples 1 to 5 and the TFTs of Comparative Examples 1 to 3 was a high value exceeding 20 cm ² / Vs.

Therefore, it is possible to achieve both high mobility exceeding 20 cm ² / Vs and high light stability in which the absolute value | ΔVth | of the threshold shift amount is 2 V or less with respect to light irradiation with a wavelength of 420 nm. 2 It was found that the film formation pressure (at least at the start of film formation) in the second region 508 in the film formation process is preferably 2.0 Pa or more and 13.0 Pa or less.
The reason why the threshold shift amount is good at 2.0 Pa or more is considered to be due to the slow deposition of the second region 18B while suppressing plasma damage to the first region 18A. On the other hand, the reason why the threshold shift amount is poor at over 13.0 Pa is considered to be due to a change in the bonding state of each element due to a significant decrease in the film formation rate.

  As shown in FIG. 12, when the film formation pressure in the second region 508 in the second film formation step is 5.0 Pa or more and less than 12.0 Pa, the absolute value of the threshold shift amount with respect to light irradiation with a wavelength of 420 nm. The value | ΔVth | was 1 V or less. Therefore, it was found that the film formation pressure (at least at the start of film formation) in the second region 508 is preferably 5.0 Pa or more and less than 12.0 Pa. It was also confirmed that when the film formation pressure was adjusted to 5.0 Pa or more, the film formation pressure dependence of the threshold shift amount with respect to light irradiation with a wavelength of 420 nm could be relaxed. That is, if the film formation pressure is 5.0 Pa or more, even if the film formation pressure fluctuates, fluctuations in the threshold shift amount can be suppressed.

  Furthermore, as shown in FIG. 12, when the film formation pressure in the second film formation step is adjusted to 10.0 Pa or less, even if the film formation pressure fluctuates within the range of 10.0 Pa or less, the threshold value It was also confirmed that the shift amount can be suppressed. Therefore, it was found that the film formation pressure (at least at the start of film formation) in the second region 508 is preferably 10.0 Pa or less.

<Dependence of composition of first region on TFT characteristics>
-Fabrication of TFTs according to Examples 6-8-
Next, the composition dependence of the first region with respect to the TFT characteristics was verified by fabricating bottom gate top contact TFTs according to Examples 6 to 8 as described below. In the TFTs according to Examples 6 to 8, except for the manufacturing conditions described below, the same conditions as the TFT manufacturing conditions according to Example 1 described above were used.

  First, in the TFTs according to Examples 6 to 8, the film formation conditions of the first region 506 were as shown in Table 2 below.

  The film formation pressure in the second region 506 was fixed at 10.0 Pa.

Thus, bottom gate type and top contact type TFTs according to Examples 6 to 8 were obtained.

-Evaluation-
Table 3 below shows the results of calculating the mobility of the TFTs according to Examples 6 to 8 and the threshold shift amount ΔVth for light irradiation with a wavelength of 420 nm using the evaluation method described above.

  As shown in Table 3, the mobility and the threshold shift amount ΔVth were found to be good even when the composition conditions of the first region 506 were changed. Further, when the first region 506 includes In and Zn as in the sixth and seventh embodiments, the wavelength is larger than that in the case where the first region 506 includes In and Sn as in the eighth embodiment. It was found that the threshold shift amount with respect to light irradiation of 420 nm could be remarkably suppressed.

<Dependence of heat treatment temperature of first region on TFT characteristics>
Next, the heat treatment temperature dependency of the first region 506 with respect to TFT characteristics was examined.
The TFTs according to Examples 6 to 8 were heat-treated at 300 ° C. and 450 ° C. instead of being heat-treated at 350 ° C. before the heat treatment.

  Using the evaluation method described above, the TFTs according to Examples 6 to 8 were subjected to heat treatment at 300 ° C., 350 ° C. (same as the values in Table 3), and 450 ° C., and the threshold shift for light irradiation with a wavelength of 420 nm. The results of determining the amount ΔVth are shown in Table 4 below.

  As shown in Table 4, it was found that the mobility and the threshold shift amount ΔVth were good even when the heat treatment temperature was changed except for ITO. In the case of ITO, the mobility and the threshold shift amount ΔVth were good when the heat treatment was less than 450 ° C. However, when the heat treatment was performed at 450 ° C., the TFT did not operate normally, and the mobility and the threshold shift amount ΔVth could not be obtained. It was. This also indicates that it is preferable to contain In and Zn when heat treating the TFT of this example. It has also been found that when the heat treatment temperature is 300 ° C. or higher and lower than 450 ° C., the TFT operates reliably regardless of the composition of the first region 506.

  In each of the above examples and comparative examples, it is assumed that the heat treatment step is performed after the second film formation step. However, even when the heat treatment step is not performed, the film formation pressure, mobility, and threshold shift are performed. It has also been confirmed that the relationship with quantity does not change.

10, 30, 500 TFT (Field Effect Transistor)
14 Gate electrode 16 Gate insulating film 18 Oxide semiconductor layers 18A, 506 First region 18B, 508 Second region 20, 510 Source electrode 22, 512 Drain electrode 502 Substrate (gate electrode)
504 Thermal oxide film (gate insulating film)

Claims (13)

A method of manufacturing a bottom gate type field effect transistor for forming a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode,
As the step of forming the oxide semiconductor layer,
A first film forming step of forming a first region including at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge;
A second region containing at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge and having a lower electrical conductivity than the first region; A second film forming step of forming a film on the surface of the region by a sputtering method, and adjusting a film forming pressure at least at the start of film formation in the second region to 2.0 Pa or more and 13.0 Pa or less;
A method of manufacturing a field effect transistor in which the steps are sequentially performed. In the second film formation step, the film formation pressure at the start of the film formation is adjusted to 5.0 Pa or more and less than 12.0 Pa.
A method of manufacturing the field effect transistor according to claim 1. In the second film formation step, the film formation pressure at the start of the film formation is adjusted to 10.0 Pa or less.
A method for manufacturing the field effect transistor according to claim 1. In the second film formation step, a film formation pressure at the start of the film formation is adjusted to 8.0 Pa or less.
A method for manufacturing the field effect transistor according to claim 3. In the second film-forming step, the film-forming pressure is switched to a pressure lower than the film-forming pressure at the start of the film-forming during the film-forming process.
The manufacturing method of the field effect transistor of any one of Claims 1-4. Depositing the second region up to a first film thickness of 5 nm at the deposition pressure at the start of deposition, and depositing the remainder of the second region at a deposition pressure of less than 1.0 Pa.
A method for manufacturing a field effect transistor according to claim 5. The film thickness of the first region is 10 nm or less,
The film thickness of the second region is equal to or greater than the film thickness of the first region.
The manufacturing method of the field effect transistor of any one of Claims 1-6. In the first film formation step, the first region is formed so as to contain In and Zn.
The manufacturing method of the field effect transistor of any one of Claims 1-7. In the first film formation step and the second film formation step, the first region and the second region are formed so as to contain In, and the In atom composition ratio of the first region is set. , Higher than the In atom composition ratio of the second region,
The manufacturing method of the field effect transistor of any one of Claims 1-8. In the first film forming step and the second film forming step, the first region and the second region are formed so that Ga is contained, and the Ga atom composition ratio of the first region is set. , Lower than the Ga atom composition ratio of the second region,
The manufacturing method of the field effect transistor of any one of Claims 1-9. In the first film formation step and the second film formation step, the first region and the second region are formed using a sputtering method while flowing a gas containing oxygen gas into the film formation chamber, and In the first film formation step, a smaller amount of oxygen gas is flowed than the flow rate of oxygen gas flowed during the second film formation step.
The manufacturing method of the field effect transistor of any one of Claims 1-10. A heat treatment step of performing heat treatment at 300 ° C. or more and 600 ° C. or less during the oxide semiconductor layer formation step or after the second film formation step;
A method for producing the field effect transistor according to claim 8. A heat treatment step of performing heat treatment at 300 ° C. or higher and lower than 450 ° C. during the oxide semiconductor layer forming step or after the second film forming step;
The method for manufacturing a field effect transistor according to claim 1.

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