TWI580048B - Method for producing field-effect transistor - Google Patents

Method for producing field-effect transistor Download PDF

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TWI580048B
TWI580048B TW102116623A TW102116623A TWI580048B TW I580048 B TWI580048 B TW I580048B TW 102116623 A TW102116623 A TW 102116623A TW 102116623 A TW102116623 A TW 102116623A TW I580048 B TWI580048 B TW I580048B
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film
film formation
effect transistor
field effect
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TW201401516A (en
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望月文彦
高田真宏
小野雅司
田中淳
鈴木真之
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富士軟片股份有限公司
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Description

場效電晶體的製造方法 Field effect transistor manufacturing method

本發明是有關於一種場效電晶體的製造方法。 The present invention relates to a method of fabricating a field effect transistor.

近年來，將In-Ga-Zn-O系(以下稱為IGZO)的氧化物半導體薄膜用於氧化物半導體層(通道層)的場效電晶體、特別是薄膜電晶體(Thin Film Transistor：TFT)的研究開發正積極地進行。氧化物半導體薄膜由於可實現低溫成膜、且表現出比非晶矽高遷移率、而且對可見光為透明，因此可在塑膠板或膜等基板上形成可撓性TFT(例如C.S.莊等人，SID 08文摘，第13頁(C.S.Chuang et al.,SID 08 DIGEST,P-13))。 In recent years, an oxide semiconductor thin film of In-Ga-Zn-O system (hereinafter referred to as IGZO) is used for a field effect transistor of an oxide semiconductor layer (channel layer), particularly a thin film transistor (Thin Film Transistor: TFT). Research and development are actively carried out. Since the oxide semiconductor thin film can exhibit low-temperature film formation, exhibits higher mobility than amorphous germanium, and is transparent to visible light, a flexible TFT can be formed on a substrate such as a plastic plate or a film (for example, CS Zhuang et al. SID 08 Digest, page 13 (CSChuang et al., SID 08 DIGEST, P-13)).

作為將此種IGZO用於氧化物半導體層的TFT的變形例，在日本專利特開2010-21555號公報中揭示有使用二層結構的氧化物半導體層的TFT，其在靠近閘極電極之側配置包含氧化銦鋅(indium zinc oxide，IZO)或氧化銦錫(Indium Tin Oxide，ITO)的第1區域、在遠離閘極電極之側配置包含IGZO的第2區域。 As a modification of the TFT in which such IGZO is used for the oxide semiconductor layer, a TFT using an oxide semiconductor layer having a two-layer structure, which is on the side close to the gate electrode, is disclosed in Japanese Laid-Open Patent Publication No. 2010-21555 A first region including indium zinc oxide (IZO) or indium tin oxide (ITO) is disposed, and a second region including IGZO is disposed on a side away from the gate electrode.

另外，在日本專利特開2010-73881號公報中揭示有底部閘極型TFT的製造方法：其中作為上述二層結構的氧化物半導體層的形成步驟，是在包含IGZO的第1區域的表面上，藉由濺鍍 法以成膜壓力為0.4 Pa，將包含組成比與該第1區域的IGZO不同的IGZO的第2區域成膜。 Further, a method of manufacturing a bottom gate type TFT in which the step of forming the oxide semiconductor layer having the two-layer structure is on the surface of the first region including IGZO is disclosed in Japanese Laid-Open Patent Publication No. 2010-73881 By sputtering In the method, the film formation pressure was 0.4 Pa, and a second region including IGZO having a composition ratio different from that of the first region was formed.

然而，包含TFT的有機電致發光(Electro Luminescence，EL)顯示裝置或液晶顯示裝置中所用的藍色發光層，表現出具有波長450 nm左右的峰值的寬的發光，但若考慮到有機EL元件的藍色光的發光光譜的下擺持續至波長420 nm為止，藍色彩色濾光器通過70%左右的波長400 nm的光，則要求：對於小於波長450 nm的波長區域的光照射的特性劣化低。在假定IGZO膜的光學帶隙(bandgap)相對窄、且該區域具有光學吸收時，會引起電晶體的臨限值位移。 However, the blue light-emitting layer used in an organic electroluminescence (EL) display device or a liquid crystal display device including a TFT exhibits a broad light emission having a peak of a wavelength of about 450 nm, but considering the organic EL element The luminescence spectrum of the blue light continues until the wavelength of 420 nm, and the blue color filter passes about 70% of the wavelength of 400 nm. It is required that the characteristics of light irradiation in the wavelength region smaller than the wavelength of 450 nm are low. . It is assumed that the optical bandgap of the IGZO film is relatively narrow and the region has optical absorption, which causes a threshold shift of the transistor.

此處，例如，若設置相對於420 nm的光照射的臨限值位移量的絕對值|△Vth |為2 V以下的基準，以此作為對於光照射的穩定性的指標，則難以實現如相對於420 nm的光照射而滿足|△Vth |≦2 V的TFT。 Here, for example, if the absolute value |ΔVth | of the threshold displacement amount of the light irradiation with respect to 420 nm is set to be 2 V or less, it is difficult to realize as an index for the stability of light irradiation. A TFT satisfying |ΔVth |≦2 V with respect to light irradiation of 420 nm.

具體而言，在C.S.莊等人，SID 08文摘，第13頁(C.S.Chuang et al.,SID 08 DIGEST,P-13)中，對現有的將IGZO用於氧化物半導體層的TFT，而評價對於光照射的特性劣化，但其相對於波長420 nm的光照射的臨限值位移量的絕對值|△Vth |超過2 V。 Specifically, in CS Zhuang et al., SID 08 Abstract, page 13 (CSChuang et al., SID 08 DIGEST, P-13), the conventional TFT using IGZO for an oxide semiconductor layer is evaluated. The characteristic of light irradiation is deteriorated, but the absolute value |ΔVth | of the displacement amount of the light irradiation with respect to the light of the wavelength of 420 nm exceeds 2 V.

另一方面，隨著顯示器的大型化、高精細化，而要求顯示器驅動用TFT的進一步的高遷移率化(例如超過20 cm2/Vs)，亦提出了在如C.S.莊等人，SID 08文摘，第13頁(C.S.Chuang et al.,SID 08 DIGEST,P-13)的TFT的現有TFT(遷移率為10 cm2/Vs左右)中無法達到的高功能顯示器。 On the other hand, with the increase in size and definition of the display, it is required to further increase the mobility of the TFT for display driving (for example, more than 20 cm 2 /Vs), and it has also been proposed in such as CS Zhuang et al., SID 08 Abstract, page 13 (CSChuang et al., SID 08 DIGEST, P-13) is a high-performance display that cannot be achieved in TFTs of TFTs with a mobility of about 10 cm 2 /Vs.

在日本專利特開2010-21555號公報中，作為電流通道層(載子行進層)的第1區域包含IZO或ITO，而可實現高遷移率的TFT，但對於光照射特性並未提及。 In the Japanese Patent Laid-Open Publication No. 2010-21555, the first region of the current channel layer (carrier traveling layer) contains IZO or ITO, and a high mobility TFT can be realized, but the light irradiation characteristics are not mentioned.

另外，在日本專利特開2010-73881號公報中，雖然作為電流通道層的第1區域包含IGZO，但遷移率低於20 cm2/Vs，且對於光照射特性並未提及。 Further, in Japanese Laid-Open Patent Publication No. 2010-73881, although the first region as the current channel layer contains IGZO, the mobility is less than 20 cm 2 /Vs, and the light irradiation characteristics are not mentioned.

本發明鑒於上述情況而成，其目的是提供一種同時具有超過20 cm2/Vs的高遷移率、及相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為2 V以下的高光穩定性的場效電晶體的製造方法。 The present invention has been made in view of the above circumstances, and an object thereof is to provide a high mobility of more than 20 cm 2 /Vs and an absolute value of a threshold displacement amount with respect to light irradiation at a wavelength of 420 nm | ΔVth | A method of producing a field-effect transistor having a high light stability below V.

本發明的上述課題藉由下述方法而解決。 The above problems of the present invention are solved by the following methods.

<1>一種場效電晶體的製造方法，其是包括形成閘極電極、閘極絕緣膜、氧化物半導體層、源極電極、與汲極電極的底部閘極型場效電晶體的製造方法，且作為上述氧化物半導體層的形成步驟，包括依序進行：第1成膜步驟，其將包含選自於由銦(indium,In)、鎵(gallium,Ga)、鋅(zinc,Zn)、鎂(magnesium,Mg)、鋁(aluminum,Al)、錫(tin,Sn)、銻(antimony,Sb)、鎘(cadmium,Cd)及鍺(germanium,Ge)所組成的群組中的至少一種的第1區域成膜；第2成膜步驟，其將包含選自於由銦、鎵、鋅、鎂、鋁、 錫、銻、鎘及鍺所組成的群組中的至少一種且導電率小於上述第1區域的第2區域，在上述第1區域的表面藉由濺鍍法而成膜，且將上述第2區域的至少成膜開始時的成膜壓力調整為2.0 Pa以上、13.0 Pa以下。 <1> A method of manufacturing a field effect transistor, which is a method of manufacturing a bottom gate type field effect transistor including a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode And the forming step of the oxide semiconductor layer includes sequentially performing a first film forming step, which comprises selecting from indium (Indium), gallium (Ga), zinc (zinc, Zn). At least one of a group consisting of magnesium (magnesium, Mg), aluminum (aluminum, Al), tin (tin), tin (antimony, Sb), cadmium (Cd), and germanium (Ge) a first region film forming; a second film forming step comprising: selected from the group consisting of indium, gallium, zinc, magnesium, aluminum, At least one of the group consisting of tin, antimony, cadmium, and antimony has a conductivity lower than that of the second region of the first region, and a surface of the first region is formed by sputtering, and the second portion is formed At least the film formation pressure at the start of film formation in the region is adjusted to 2.0 Pa or more and 13.0 Pa or less.

<2>如上述<1>所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為5.0 Pa以上且未滿12.0 Pa。 In the second film forming step, the film forming pressure at the start of film formation is adjusted to 5.0 Pa or more and less than 12.0 Pa in the second film forming step. .

<3>如上述<1>或<2>所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為10.0 Pa以下。 In the second film forming step, the film forming pressure at the start of film formation is adjusted to 10.0 Pa or less in the method of producing a field effect transistor according to the above aspect of the invention.

<4>如上述<3>所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為8.0 Pa以下。 In the second film forming step, the film forming pressure at the start of film formation is adjusted to 8.0 Pa or less.

<5>如上述<1>至<4>中任一項所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，在成膜中途將成膜壓力切換成低於上述成膜開始時的成膜壓力的壓力。 The method for producing a field effect transistor according to any one of the above aspects of the present invention, wherein, in the second film forming step, the film forming pressure is switched to be lower than in the middle of film formation. The pressure of the film formation pressure at the start of the film formation described above.

<6>如上述<5>所述的場效電晶體的製造方法，其中，藉由上述成膜開始時的成膜壓力將上述第2區域成膜至最初的5 nm的膜厚為止，並藉由未滿1.0 Pa的成膜壓力將上述第2區域的其餘部分成膜。 The method of producing a field effect transistor according to the above aspect, wherein the second region is formed to a film thickness of the first 5 nm by the film formation pressure at the start of the film formation, and The remaining portion of the above second region was formed into a film by a film forming pressure of less than 1.0 Pa.

<7>如上述<1>至<6>中任一項所述的場效電晶體的製造方法，其中，將上述第1區域的膜厚設為10 nm以下，將上述 第2區域的膜厚設為上述第1區域的膜厚以上。 The method of producing a field effect transistor according to any one of the above aspects, wherein the film thickness of the first region is 10 nm or less, and the above The film thickness of the second region is set to be equal to or greater than the film thickness of the first region.

<8>如上述<1>至<7>中任一項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟中，以上述第1區域中含有銦與鋅的方式成膜。 The method for producing a field effect transistor according to any one of the above aspects, wherein the first film forming step includes the indium and zinc in the first region. Film formation.

<9>如上述<1>至<8>中任一項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，以上述第1區域及上述第2區域分別含有銦的方式成膜，且使上述第1區域的銦原子組成比率高於上述第2區域的銦原子組成比率。 The method for producing a field effect transistor according to any one of the above aspects of the present invention, wherein the first film forming step and the second film forming step are the first region And forming a film in which the second region contains indium, respectively, and the indium atomic composition ratio of the first region is higher than the indium atomic composition ratio of the second region.

<10>如上述<1>至<9>中任一項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，以上述第1區域及上述第2區域分別含有鎵的方式成膜，且使上述第1區域的鎵原子組成比率低於上述第2區域的鎵原子組成比率。 The method for producing a field effect transistor according to any one of the above aspects, wherein the first film forming step and the second film forming step are the first region And forming a film in which the second region contains gallium, and the gallium atom composition ratio of the first region is lower than the gallium atom composition ratio of the second region.

<11>如上述<1>至<10>中任一項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，使用濺鍍法在成膜室內一邊流通包含氧氣的氣體，一邊將上述第1區域及上述第2區域成膜；且在上述第1成膜步驟中，與在上述第2成膜步驟時所流通的氧氣的流量相比，而流通更少的流量的氧氣。 The method for producing a field effect transistor according to any one of the above aspects, wherein the first film forming step and the second film forming step are performed by sputtering. The first region and the second region are formed by flowing a gas containing oxygen while flowing through the deposition chamber; and in the first film formation step, the flow rate of oxygen flowing during the second film formation step is Than, while flowing less oxygen in the flow.

<12>如上述<8>所述的場效電晶體的製造方法，其中，在上述氧化物半導體層的形成步驟中、或上述第2成膜步驟後，具有以300℃以上、600℃以下進行熱處理的熱處理步驟。 The method of producing a field effect transistor according to the above <8>, wherein the step of forming the oxide semiconductor layer or the step of forming the second film forming step is 300° C. or higher and 600° C. or lower. A heat treatment step of performing heat treatment.

<13>如上述<1>至<11>中任一項所述的場效電晶體的製造方法，其中，在上述氧化物半導體層的形成步驟中、或上述第2成膜步驟後，具有以300℃以上且未滿450℃進行熱處理的熱處理步驟。 The method of producing a field effect transistor according to any one of the above aspects of the present invention, wherein, in the step of forming the oxide semiconductor layer or after the second film formation step, A heat treatment step of heat treatment at 300 ° C or more and less than 450 ° C.

根據本發明，可提供一種同時具有超過20 cm2/Vs的高遷移率、及相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為2 V以下的高光穩定性的場效電晶體的製造方法。 According to the present invention, it is possible to provide a high mobility of more than 20 cm 2 /Vs and an absolute value of the displacement amount of the threshold value with respect to the light irradiation of 420 nm | ΔVth | A method of manufacturing a field effect transistor.

10、10a、10b、30‧‧‧場效電晶體 10, 10a, 10b, 30‧‧‧ field effect transistor

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧閘極電極 14‧‧‧ gate electrode

16‧‧‧閘極絕緣膜 16‧‧‧Gate insulation film

18‧‧‧氧化物半導體層 18‧‧‧Oxide semiconductor layer

18A、506‧‧‧第1區域 18A, 506‧‧‧1st area

18B、508‧‧‧第2區域 18B, 508‧‧‧2nd area

20、510‧‧‧源極電極 20, 510‧‧‧ source electrode

22、512‧‧‧汲極電極 22, 512‧‧‧汲electrode

100‧‧‧液晶顯示裝置 100‧‧‧Liquid crystal display device

102‧‧‧鈍化層 102‧‧‧ Passivation layer

104‧‧‧畫素下部電極 104‧‧‧ pixel lower electrode

106‧‧‧對向上部電極 106‧‧‧for the upper electrode

108‧‧‧液晶層 108‧‧‧Liquid layer

110‧‧‧RGB彩色濾光器 110‧‧‧RGB color filter

112、220、320‧‧‧閘極配線 112, 220, 320‧‧‧ gate wiring

112a、112b‧‧‧偏光板 112a, 112b‧‧‧ polarizing plate

114、222、322‧‧‧資料配線 114, 222, 322‧‧‧ data wiring

116‧‧‧接觸孔 116‧‧‧Contact hole

118、226、310‧‧‧電容器 118, 226, 310‧‧‧ capacitors

200‧‧‧有機EL顯示裝置 200‧‧‧Organic EL display device

202‧‧‧基板絕緣層 202‧‧‧Substrate insulation

204‧‧‧彩色濾光器層 204‧‧‧Color filter layer

206‧‧‧畫素電極(陽極) 206‧‧‧ pixel electrodes (anode)

208‧‧‧連接電極 208‧‧‧Connecting electrode

210、316‧‧‧絕緣膜 210, 316‧‧ ‧ insulating film

212‧‧‧有機層 212‧‧‧Organic layer

214‧‧‧陰極 214‧‧‧ cathode

224‧‧‧驅動配線 224‧‧‧Drive wiring

300‧‧‧X射線感測器 300‧‧‧X-ray sensor

302‧‧‧電荷收集用電極 302‧‧‧Electrical electrodes for charge collection

304‧‧‧X射線轉變層 304‧‧‧X-ray transition layer

306‧‧‧上部電極 306‧‧‧Upper electrode

308‧‧‧鈍化膜 308‧‧‧passivation film

312‧‧‧電容器用下部電極 312‧‧‧The lower electrode for capacitors

314‧‧‧電容器用上部電極 314‧‧‧Upper electrode for capacitor

500‧‧‧TFT 500‧‧‧TFT

502‧‧‧p型Si基板 502‧‧‧p type Si substrate

504‧‧‧熱氧化膜 504‧‧‧ Thermal Oxide Film

圖1A是表示本發明的實施方式的TFT、且為底部閘極結構且頂部接觸型的TFT的一例的示意圖。 1A is a schematic view showing an example of a TFT having a bottom gate structure and a top contact type TFT according to an embodiment of the present invention.

圖1B是表示本發明的實施方式的TFT、且為底部閘極結構且底部接觸型的TFT的一例的示意圖。 1B is a schematic view showing an example of a TFT having a bottom gate structure and a bottom contact type TFT according to an embodiment of the present invention.

圖2是本發明的電光學裝置的一個實施方式的液晶顯示裝置的一部分的概略剖面圖。 2 is a schematic cross-sectional view showing a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention.

圖3是圖2所示的液晶顯示裝置的電氣配線的概略構成圖。 3 is a schematic configuration diagram of electric wiring of the liquid crystal display device shown in FIG. 2 .

圖4是本發明電光學裝置的一個實施方式的主動矩陣式有機EL顯示裝置的一部分的概略剖面圖。 4 is a schematic cross-sectional view showing a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the present invention.

圖5是圖4所示的電光學裝置的電氣配線的概略構成圖。 Fig. 5 is a schematic configuration diagram of electric wiring of the electro-optical device shown in Fig. 4;

圖6是作為本發明的感測器的一個實施方式的X射線感測器的一部分的概略剖面圖。 Fig. 6 is a schematic cross-sectional view showing a part of an X-ray sensor which is one embodiment of the sensor of the present invention.

圖7是圖6所示的感測器的電氣配線的概略構成圖。 Fig. 7 is a schematic configuration diagram of electrical wiring of the sensor shown in Fig. 6;

圖8A是實施例及比較例的TFT的平面圖。 Fig. 8A is a plan view showing TFTs of Examples and Comparative Examples.

圖8B是圖8A所示的TFT的A-A線箭頭所視剖面圖。 Fig. 8B is a cross-sectional view taken along line A-A of the TFT shown in Fig. 8A.

圖9是表示比較例1的TFT的單色光照射時的Vg-Id特性的圖。 FIG. 9 is a view showing Vg-Id characteristics at the time of monochromatic light irradiation of the TFT of Comparative Example 1. FIG.

圖10是表示實施例3的TFT的單色光照射時的Vg-Id特性的圖。 FIG. 10 is a view showing Vg-Id characteristics at the time of monochromatic light irradiation of the TFT of Example 3. FIG.

圖11是表示代表性的比較例1的TFT與實施例3的TFT中光照射波長與△Vth的關係的圖表。 FIG. 11 is a graph showing the relationship between the light irradiation wavelength and ΔVth in the TFT of the comparative comparative example 1 and the TFT of the third embodiment.

圖12是根據表1繪製成膜壓力與臨限值位移量△Vth(波長為420 nm時)的關係的圖表。 Fig. 12 is a graph showing the relationship between the film formation pressure and the threshold displacement amount ΔVth (when the wavelength is 420 nm) according to Table 1.

以下，一邊參照隨附的圖式，一邊對本發明的實施方式的場效電晶體的製造方法進行具體地說明。另外，圖中，對具有相同或對應的功能的構件(構成要素)給予相同的符號並適當省略說明。另外，在以下說明中，關於位置關係中所用的「上」及「下」的用語，是為了方便而使用，其方向不應受到限制。 Hereinafter, a method of manufacturing the field effect transistor according to the embodiment of the present invention will be specifically described with reference to the accompanying drawings. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and their description will be appropriately omitted. In addition, in the following description, the terms "upper" and "lower" used in the positional relationship are used for convenience, and the direction thereof should not be limited.

1. 場效電晶體的構成 1. Composition of field effect transistor

首先，在說明本發明的實施方式的場效電晶體的製造方法之前，對藉由該製造方法而製作的場效電晶體的構成進行概略說明。另外，作為本發明的實施方式的場效電晶體，可列舉TFT作為一例。 First, before explaining the method of manufacturing the field effect transistor according to the embodiment of the present invention, the configuration of the field effect transistor produced by the manufacturing method will be briefly described. Moreover, as a field effect transistor of embodiment of this invention, a TFT is mentioned as an example.

本發明的實施方式的TFT是具有閘極電極、閘極絕緣膜、氧化物半導體層(活性層)、源極電極及汲極電極，對閘極電極施加電壓，而控制在氧化物半導體層中流通的電流，並具有將源極電極與汲極電極間的電流進行開關的功能的主動元件。並且，本發明的實施方式的TFT中，氧化物半導體層進一步具備：在膜厚方向的第1區域、以及較該第1區域而配置於遠離閘極電極之側的第2區域。另外，本實施方式的TFT中，在第1區域與第2區域間不可插入電極層等氧化物半導體層以外的層。 A TFT according to an embodiment of the present invention has a gate electrode, a gate insulating film, an oxide semiconductor layer (active layer), a source electrode, and a drain electrode, and applies a voltage to the gate electrode to be controlled in the oxide semiconductor layer. An active current that has a function of switching a current between a source electrode and a drain electrode. Further, in the TFT of the embodiment of the present invention, the oxide semiconductor layer further includes a first region in the film thickness direction and a second region disposed on the side away from the gate electrode from the first region. Further, in the TFT of the present embodiment, a layer other than the oxide semiconductor layer such as an electrode layer is not interposed between the first region and the second region.

作為TFT的元件結構，根據閘極電極的位置，而有所謂的逆交錯(inverted-staggered)結構(亦稱為底部閘極型)及交錯結構(亦稱為頂部閘極型)的形態，但本實施方式中，使用底部閘極型TFT。 As the element structure of the TFT, depending on the position of the gate electrode, there is a so-called inverted-staggered structure (also referred to as a bottom gate type) and a staggered structure (also referred to as a top gate type), but In the present embodiment, a bottom gate type TFT is used.

但是，在底部閘極型TFT中，根據氧化物半導體層與源極電極及汲極電極(適當稱為「源極-汲極電極」)的接觸部分，亦有所謂的頂部接觸型、底部接觸型這2種形態，但也可為任一種形態。 However, in the bottom gate type TFT, there is also a so-called top contact type and bottom contact depending on the contact portion of the oxide semiconductor layer and the source electrode and the drain electrode (referred to as "source-drain electrode" as appropriate). There are two types of forms, but they may be of any form.

另外，所謂頂部閘極結構，是在閘極絕緣膜的上側配置有閘極電極、在閘極絕緣膜的下側形成有氧化物半導體層的形態，所謂底部閘極結構，是在閘極絕緣膜的下側配置有閘極電極、在閘極絕緣膜的上側形成有氧化物半導體層的形態。另外，所謂底部接觸型，是源極-汲極電極較氧化物半導體層先形成、而氧化物半導體層的下表面與源極-汲極電極接觸的形態；所謂頂部接觸型， 是氧化物半導體層較源極-汲極電極先形成、而氧化物半導體層的上表面與源極-汲極電極接觸的形態。 In addition, the top gate structure is a structure in which a gate electrode is disposed on the upper side of the gate insulating film and an oxide semiconductor layer is formed on the lower side of the gate insulating film, and the bottom gate structure is insulated at the gate. A gate electrode is disposed on the lower side of the film, and an oxide semiconductor layer is formed on the upper side of the gate insulating film. In addition, the bottom contact type is a form in which a source-drain electrode is formed earlier than an oxide semiconductor layer, and a lower surface of the oxide semiconductor layer is in contact with a source-drain electrode; The oxide semiconductor layer is formed first than the source-drain electrode, and the upper surface of the oxide semiconductor layer is in contact with the source-drain electrode.

圖1A是本發明的實施方式的TFT、且為底部閘極型且頂部接觸型的TFT的一例的示意圖。圖1A所示的TFT 10中，在基板12的厚度方向的一面依序積層：閘極電極14、閘極絕緣膜16、氧化物半導體層18的第1區域18A、與氧化物半導體層18的第2區域18B。並且，在該第2區域18B上(的表面)，源極電極20及汲極電極22彼此隔開而設置。 1A is a schematic view showing an example of a TFT of a bottom gate type and a top contact type TFT according to an embodiment of the present invention. In the TFT 10 shown in FIG. 1A, a gate electrode 14, a gate insulating film 16, a first region 18A of the oxide semiconductor layer 18, and an oxide semiconductor layer 18 are sequentially laminated on one surface in the thickness direction of the substrate 12. The second area 18B. Further, on the (surface of) the second region 18B, the source electrode 20 and the drain electrode 22 are provided apart from each other.

圖1B是本發明的實施方式的TFT、且為底部閘極型且底部接觸型的TFT的一例的示意圖。圖1B所示的TFT 30中，在基板12的厚度方向的一面依序積層：閘極電極14、與閘極絕緣膜16。並且，在該閘極絕緣膜16的表面，使源極電極20及汲極電極22彼此隔開而設置，而且在這些源極電極20及汲極電極22之上(表面)，依序積層：氧化物半導體層18的第1區域18A、與氧化物半導體層18的第2區域18B。 FIG. 1B is a schematic view showing an example of a TFT of the embodiment of the present invention and a bottom gate type and a bottom contact type TFT. In the TFT 30 shown in FIG. 1B, a gate electrode 14 and a gate insulating film 16 are sequentially laminated on one surface in the thickness direction of the substrate 12. Further, on the surface of the gate insulating film 16, the source electrode 20 and the drain electrode 22 are provided apart from each other, and on the surface (surface) of the source electrode 20 and the gate electrode 22, sequentially: The first region 18A of the oxide semiconductor layer 18 and the second region 18B of the oxide semiconductor layer 18.

另外，本實施方式的TFT除了上述以外，亦可為各種構成，可適當為在氧化物半導體層上具備保護層、或在基板上具備絕緣層等的構成。 In addition, the TFT of the present embodiment may have various configurations, and may have a configuration in which a protective layer is provided on the oxide semiconductor layer or an insulating layer is provided on the substrate.

另外，關於第1區域18A與第2區域18B的區別，可根據藉由氧化物半導體層18的剖面穿透型電子顯微鏡(Transmission Electron Microscope，TEM)分析所得的對比度的差異進行區別，或者根據藉由感應耦合電漿(Inductively Coupled Plasma，ICP) 發光分析裝置或螢光X射線分析裝置所得的組成或組成比的差異進行區別。 Further, the difference between the first region 18A and the second region 18B can be distinguished based on the difference in contrast obtained by the transmission electron microscope (TEM) analysis of the oxide semiconductor layer 18, or Inductively Coupled Plasma (ICP) The difference in composition or composition ratio obtained by the luminescence analysis device or the fluorescent X-ray analysis device is distinguished.

2. 場效電晶體的製造方法 2. Method for manufacturing field effect transistor

以上所說明的底部閘極型場效電晶體(TFT 10或TFT 30)的製造方法，是依序進行如下步驟：作為氧化物半導體層18的形成步驟的製造方法的第1成膜步驟，其將包含選自於由In、Ga、Zn、Mg、Al、Sn、Sb、Cd、及Ge所組成的群組中的至少一種的第1區域18A成膜；以及第2成膜步驟，其將包含選自於由In、Ga、Zn、Mg、Al、Sn、Sb、Cd、及Ge所組成的群組中的至少一種且導電率小於第1區域18A的第2區域18B，在第1區域18A的表面藉由濺鍍法而成膜，且將第2區域18B的至少成膜開始時的成膜壓力調整為2.0 Pa以上、13.0 Pa以下。 In the method of manufacturing the bottom gate type field effect transistor (TFT 10 or TFT 30) described above, the first film forming step of the manufacturing method of the step of forming the oxide semiconductor layer 18 is sequentially performed. Forming a first region 18A comprising at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge; and a second film forming step, which will a second region 18B including at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge and having a conductivity lower than that of the first region 18A, in the first region The surface of 18A is formed by a sputtering method, and the film formation pressure at the start of at least film formation of the second region 18B is adjusted to 2.0 Pa or more and 13.0 Pa or less.

根據此種製造方法，藉由使用第1區域18A、與導電率小於該第1區域的第2區域18B的積層結構，而第1區域18A成為所謂的「載子行進層」，第2區域18B成為所謂的「電阻層」。 According to such a manufacturing method, the first region 18A is a so-called "carrier traveling layer" and the second region 18B is formed by using the first region 18A and the laminated structure of the second region 18B having a smaller conductivity than the first region. Become a so-called "resistance layer".

並且認為，成為「載子行進層」的第1區域18A與成為「電阻層」的第2區域18B相比，因成膜時所受的損傷(例如電漿損傷)而產生的缺陷，對TFT特性、特別是光照射特性所造成的影響更大。 In addition, it is considered that the first region 18A which is the "carrier-transporting layer" has defects due to damage (for example, plasma damage) during film formation, compared with the second region 18B which is the "resistance layer". The characteristics, especially the effects of light illumination, are greater.

本實施方式中，在第2成膜步驟的至少成膜開始時，在藉由第1成膜步驟而成膜的第1區域18A的表面，藉由調整為2.0 Pa以上、13.0 Pa以下的成膜壓力而將第2區域18B成膜，因此可降 低對第1區域18A的表面造成該成膜損傷(例如電漿損傷)。其結果，可同時具有：超過20 cm2/Vs的高遷移率、及相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為2 V以下的高光穩定性。 In the present embodiment, at least the surface of the first region 18A formed by the first film formation step is adjusted to be 2.0 Pa or more and 13.0 Pa or less at the start of film formation in the second film formation step. Since the second region 18B is formed by the film pressure, it is possible to reduce the film formation damage (for example, plasma damage) on the surface of the first region 18A. As a result, it is possible to have both a high mobility exceeding 20 cm 2 /Vs and an absolute value of the displacement amount of the threshold value |ΔVth | of 2 V or less with respect to light irradiation at a wavelength of 420 nm.

具有高遷移率及高光穩定性是指，本實施方式的TFT 10或TFT 30可較佳地用於大面積、高精細的透明顯示器的驅動用TFT。另外，在有機EL或液晶顯示器(Liquid-Crystal Display，LCD)驅動用TFT中，無須設置遮斷光的層，而可大幅降低製造成本。 The high mobility and high light stability mean that the TFT 10 or the TFT 30 of the present embodiment can be preferably used for a TFT for driving a large-area, high-definition transparent display. Further, in the TFT for organic EL or liquid crystal display (LCD) driving, it is not necessary to provide a layer for blocking light, and the manufacturing cost can be greatly reduced.

另外，所謂「導電率」，是表示物質的導電的容易性的物性值，在將物質的載子濃度設為n、將基本電荷(elementary charge)設為e、將載子遷移率設為μ，並假定德魯德模型(Drude model)時，物質的導電率σ由以下式表示。 In addition, the "electrical conductivity" is a physical property value indicating the easiness of conductivity of a substance, and the carrier concentration of the substance is n, the elementary charge is e, and the carrier mobility is set to μ. And, assuming the Drude model, the conductivity σ of the substance is expressed by the following formula.

σ=neμ σ=neμ

在第1區域18A、或第2區域18B為n型半導體時，載子為電子，所謂載子濃度表示電子載子濃度，所謂載子遷移率表示電子遷移率。同樣，在第1區域18A、或第2區域18B為p型半導體時，載子為電洞，所謂載子濃度表示電洞載子濃度，所謂載子遷移率表示電洞遷移率。另外，物質的載子濃度與載子遷移率可藉由電洞測定而求出。 When the first region 18A or the second region 18B is an n-type semiconductor, the carrier is an electron, and the carrier concentration indicates the electron carrier concentration, and the carrier mobility indicates the electron mobility. Similarly, when the first region 18A or the second region 18B is a p-type semiconductor, the carrier is a hole, the carrier concentration indicates a hole carrier concentration, and the carrier mobility indicates a hole mobility. Further, the carrier concentration of the substance and the carrier mobility can be determined by hole measurement.

關於導電率的求法，可藉由測定厚度已知的膜的薄片電阻(sheet resistance)，而求出膜的導電率。半導體的導電率因溫度而變化，但本文記載的導電率表示室溫(20℃)下的導電率。 Regarding the method of determining the conductivity, the conductivity of the film can be determined by measuring the sheet resistance of a film having a known thickness. The conductivity of a semiconductor varies with temperature, but the conductivity described herein represents the conductivity at room temperature (20 ° C).

另外，所謂「成膜壓力」，是指濺鍍裝置成膜室的成膜時壓力。 In addition, the "film formation pressure" means the pressure at the time of film formation of the film formation chamber of a sputtering apparatus.

另外，所謂「電漿損傷」，是因成膜時所導入的氬氣及氧氣藉由施加電場而離子化、而生成的氬離子及氧離子所造成的物理性損傷，由於氬離子的質量比氧離子更大，因此影響更大。 In addition, the "plasma damage" is a physical damage caused by argon ions and oxygen ions generated by ionization of argon gas and oxygen gas introduced during film formation by application of an electric field, and mass ratio of argon ions. The oxygen ions are larger and therefore have a greater impact.

關於如以上的場效電晶體的製造方法，對作為代表例的圖1A所示的底部閘極型且頂部接觸型的TFT 10的製造方法進行具體地說明，但在底部閘極型且底部接觸型的TFT 30的製造方法中，亦可應用同樣的方法。 Regarding the manufacturing method of the field effect transistor as described above, a method of manufacturing the bottom gate type and top contact type TFT 10 shown in FIG. 1A as a representative example will be specifically described, but the bottom gate type and the bottom contact are provided. The same method can be applied to the method of manufacturing the TFT 30 of the type.

-閘極電極14的形成步驟- - Formation step of the gate electrode 14 -

首先，進行閘極電極14的形成步驟，如圖1A所示般，準備用以形成TFT 10的基板12後，在基板12的厚度方向的一個主面上，形成閘極電極14。 First, in the step of forming the gate electrode 14, as shown in FIG. 1A, after the substrate 12 for forming the TFT 10 is prepared, the gate electrode 14 is formed on one main surface in the thickness direction of the substrate 12.

關於所準備的基板12的形狀、結構、大小等，並無特別限制，可根據目的進行適當選擇。基板12的結構可為單層結構，亦可為積層結構。作為基板12，例如可使用包含：玻璃或釔穩定化氧化鋯(Yttria Stabilized Zirconia，YSZ)、矽(Si)等無機材料，聚對苯二甲酸乙二酯(polyethylene terephthalate)或聚萘二甲酸乙二酯(polyethylene naphthalate)、聚醯亞胺(polyimide)等樹脂，或與黏土礦物或具有雲母派生結晶結構的粒子的複合塑膠材料等 樹脂複合材料等的基板。其中，就輕量的方面、具有可撓性的方面而言，較佳為包含樹脂或樹脂複合材料的基板。另外，樹脂基板可具備：用以防止水分或氧氣透過的氣體阻隔層、或用以提高樹脂基板的平坦性或與下部電極的密接性的底塗層(undercoat)等。 The shape, structure, size, and the like of the prepared substrate 12 are not particularly limited, and may be appropriately selected depending on the purpose. The structure of the substrate 12 may be a single layer structure or a laminate structure. As the substrate 12, for example, an inorganic material such as glass or yttria stabilized zirconia (YSZ) or yttrium (Si), polyethylene terephthalate or polyethylene naphthalate can be used. a resin such as a polyethylene naphthalate or a polyimide, or a composite plastic material such as a clay mineral or a particle having a mica-derived crystal structure. A substrate such as a resin composite material. Among them, in terms of lightweightness and flexibility, a substrate comprising a resin or a resin composite material is preferred. Further, the resin substrate may include a gas barrier layer for preventing the permeation of moisture or oxygen, or an undercoat for improving the flatness of the resin substrate or the adhesion to the lower electrode.

並且，在閘極電極14的形成中，首先考慮與所使用的材料的適性，而自例如印刷方式、塗佈方式等的濕式方式，真空蒸鍍法、濺鍍法、離子電鍍法等的物理方式，化學氣相沈積(Chemical vapor deposition，CVD)、電漿CVD法等的化學方式等中適當選擇的方法，來將導電膜成膜。成膜後，藉由光刻法(photolithography)及蝕刻法(etching method)或剝離法(lift-off method)等，將導電膜圖案化為特定的形狀，藉此由導電膜形成閘極電極14。此時，較佳為將閘極電極14及閘極配線同時圖案化。 Further, in the formation of the gate electrode 14, first, considering the suitability of the material to be used, a wet method such as a printing method or a coating method, a vacuum deposition method, a sputtering method, an ion plating method, or the like. The conductive film is formed by a physical selection method, a chemical method such as chemical vapor deposition (CVD) or a plasma CVD method. After the film formation, the conductive film is patterned into a specific shape by photolithography, an etching method, a lift-off method, or the like, whereby the gate electrode 14 is formed of a conductive film. . At this time, it is preferable to simultaneously pattern the gate electrode 14 and the gate wiring.

作為構成閘極電極14的導電膜，較佳為使用具有高導電性者，例如可將鋁(aluminum,Al)、鉬(molybdenum,Mo)、鉻(chromium,Cr)、鉭(tantalum,Ta)、鈦(titanium,Ti)、金(gold,Au)、銀(silver,Ag)等金屬，鋁-釹(aluminum-neodymium Al-Nd)、銀(silver,Ag)合金，氧化錫(tin oxide)、氧化鋅(zinc oxide)、氧化銦(indium oxide)、氧化銦錫(indium tin oxide,ITO)、氧化銦鋅(indium zinc oxide,IZO)等金屬氧化物導電膜等，製成單層或2層以上的積層結構而使用。 As the conductive film constituting the gate electrode 14, it is preferable to use a material having high conductivity, for example, aluminum (aluminum), molybdenum (Mo), chromium (chromium, Cr), tantalum (Ta). , titanium (titanium, Ti), gold (gold), silver (silver, Ag) and other metals, aluminum-钕 (aluminum-neodymium Al-Nd), silver (silver, Ag) alloy, tin oxide (tin oxide) And a metal oxide conductive film such as zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), etc., made into a single layer or 2 It is used in a layered structure above the layer.

-閘極絕緣膜16的形成步驟- - Formation step of the gate insulating film 16 -

在形成閘極電極14後，進行閘極絕緣膜16的形成步驟，即：在該閘極電極14上及基板12的露出面上，形成閘極絕緣膜16。 After the gate electrode 14 is formed, a step of forming the gate insulating film 16 is performed, that is, a gate insulating film 16 is formed on the gate electrode 14 and the exposed surface of the substrate 12.

在閘極絕緣膜16的形成中，可使用與閘極電極14的形成方法相同的形成方法。 In the formation of the gate insulating film 16, the same formation method as that of the gate electrode 14 can be used.

構成閘極絕緣膜16的絕緣膜較佳為具有高絕緣性者，例如可製成二氧化矽(SiO2)、氮化矽(SiNx)、氮氧化矽(SiON)、氧化鋁(Al2O3)、氧化釔(Y2O3)、氧化鉭(Ta2O5)、氧化鉿(HfO2)等的絕緣膜、或者至少包含二種以上這些化合物的絕緣膜。 The insulating film constituting the gate insulating film 16 is preferably one having high insulating properties, for example, cerium oxide (SiO 2 ), cerium nitride (SiNx), cerium oxynitride (SiON), or aluminum oxide (Al 2 O). 3 ) An insulating film of yttrium oxide (Y 2 O 3 ), yttrium oxide (Ta 2 O 5 ), yttrium oxide (HfO 2 ), or an insulating film containing at least two or more of these compounds.

-氧化物半導體層18的形成步驟- - Formation step of the oxide semiconductor layer 18 -

在形成閘極絕緣膜16後，進行氧化物半導體層18的形成步驟，即：在該閘極絕緣膜16的表面，形成氧化物半導體層18。 After the gate insulating film 16 is formed, a step of forming the oxide semiconductor layer 18 is performed, that is, an oxide semiconductor layer 18 is formed on the surface of the gate insulating film 16.

在該形成步驟中，氧化物半導體層18可形成為非晶質膜或晶質膜的任一種。但是，為非晶質膜時，為了可在低溫下成膜，較佳為形成於具有可撓性的基板12上。另外，為非晶質膜時，不存在結晶晶界，而可獲得均勻性高的膜。另外，氧化物半導體層18是否為非晶質膜，可藉由X射線繞射測定進行確認。即，藉由X射線繞射測定，在未檢測到表示結晶結構的明確的波峰(peak)時，可判斷該氧化物半導體層18為非晶質膜。 In this forming step, the oxide semiconductor layer 18 can be formed as either an amorphous film or a crystalline film. However, in the case of an amorphous film, it is preferably formed on the flexible substrate 12 in order to form a film at a low temperature. Further, in the case of an amorphous film, there is no crystal grain boundary, and a film having high uniformity can be obtained. Further, whether or not the oxide semiconductor layer 18 is an amorphous film can be confirmed by X-ray diffraction measurement. In other words, when the peak of the crystal structure is not detected by the X-ray diffraction measurement, the oxide semiconductor layer 18 can be judged to be an amorphous film.

氧化物半導體層18中的包含第1區域18A與第2區域18B的膜厚(總膜厚)，並無特別限定，就實現膜的均勻性、及容易調整氧化物半導體層18中的總載子濃度的觀點而言，較佳為設為10 nm以上、200 nm以下。 The film thickness (total film thickness) including the first region 18A and the second region 18B in the oxide semiconductor layer 18 is not particularly limited, and uniformity of the film is achieved, and the total load in the oxide semiconductor layer 18 is easily adjusted. From the viewpoint of the sub-concentration, it is preferably 10 nm or more and 200 nm or less.

在該氧化物半導體層18的形成步驟中，依序進行第1成膜步驟與第2成膜步驟。另外，在第1成膜步驟與第2成膜步驟之間，可進行圖案化處理或熱處理等的中間處理步驟。 In the step of forming the oxide semiconductor layer 18, the first film formation step and the second film formation step are sequentially performed. Further, an intermediate treatment step such as a patterning treatment or a heat treatment may be performed between the first film formation step and the second film formation step.

-第1成膜步驟- - 1st film forming step -

在第1成膜步驟中，將包含選自於由In、Ga、Zn、Mg、Al、Sn、Sb、Cd、及Ge所組成的群組中的至少一種(例如In-Ga-Zn-O、In-Zn-O、In-Ga-O、In-Sn-O、In-Sn-Zn-O、In-Ga-Sn-O或In-O等)的第1區域18A進行成膜。 In the first film formation step, at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge (for example, In-Ga-Zn-O) is contained. The first region 18A of In-Zn-O, In-Ga-O, In-Sn-O, In-Sn-Zn-O, In-Ga-Sn-O, or In-O is formed into a film.

作為第1區域18A的成膜方法，例如可列舉：印刷方式或塗佈方式等的濕式方式，真空蒸鍍法或濺鍍法、離子電鍍法等的物理方式，CVD或電漿CVD法等的化學方式。在這些之中，就容易控制膜厚的觀點而言，較佳為使用真空蒸鍍法、濺鍍法、離子電鍍法、CVD或電漿CVD法等的氣相成膜法。在氣相成膜法中，更佳為濺鍍法、脈衝雷射蒸鍍法(Pulsed Laser Deposition，PLD法)。而且，就量產性的觀點而言，尤佳為濺鍍法。 Examples of the film formation method of the first region 18A include a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a CVD or plasma CVD method. The chemical way. Among these, from the viewpoint of easily controlling the film thickness, a vapor phase film formation method such as a vacuum deposition method, a sputtering method, an ion plating method, a CVD method, or a plasma CVD method is preferably used. In the vapor phase film formation method, a sputtering method or a pulsed laser deposition (PLD method) is more preferred. Moreover, in terms of mass production, it is particularly preferable to use a sputtering method.

為濺鍍法時，特別是，作為投入電力，直流電/射頻(Direct Current/Radio Frequency，DC/RF)並無特別限定。另外，在濺鍍法中亦可藉由調整了組成的單靶(single target)進行成膜、或藉由使用了多個靶的共濺鍍進行成膜，但較佳為單靶。為共濺鍍時，使用DC/RF兩者。例如為IGZO系時，In2O3與ZnO進行DC濺鍍，Ga2O3進行RF濺鍍。另外，為了控制所得的膜的導電率，而任意控制成膜時的成膜室內的氧氣分壓。作為控制成膜室內的氧氣分 壓的方法，可為改變導入至成膜室內的O2氣量的方法，亦可為改變氧自由基或臭氧氣體的導入量的方法。即便在停止氧氣導入的情況下，在電阻高時，亦可導入H2或N2等還原性氣體。在使用氧自由基時，若考慮到成膜壓力與平均自由行程的關係，直接噴射於成膜基板的效果大。 In the case of the sputtering method, in particular, direct current/radio frequency (DC/RF) is not particularly limited as the input power. Further, in the sputtering method, film formation may be performed by a single target having a composition adjusted, or by co-sputtering using a plurality of targets, but a single target is preferable. For total sputtering, both DC/RF are used. For example, in the case of the IGZO system, In 2 O 3 and ZnO are subjected to DC sputtering, and Ga 2 O 3 is subjected to RF sputtering. Further, in order to control the conductivity of the obtained film, the partial pressure of oxygen in the film forming chamber at the time of film formation was arbitrarily controlled. The method of controlling the partial pressure of oxygen in the deposition chamber may be a method of changing the amount of O 2 gas introduced into the deposition chamber, or a method of changing the introduction amount of oxygen radicals or ozone gas. Even when oxygen introduction is stopped, a reducing gas such as H 2 or N 2 can be introduced when the electric resistance is high. When oxygen radicals are used, the effect of directly spraying on the film formation substrate is large in consideration of the relationship between the film formation pressure and the average free path.

另外，在該第1成膜步驟中，較佳為以包含In、Ga、Sn、Zn、及Cd中至少一種的方式進行成膜，較佳為以包含In、Sn、Zn及Ga中至少一種的方式進行成膜，較佳為以包含In、Ga及Zn中至少1種的方式進行成膜(例如In-O系)。而且，較佳為以至少包含In的方式進行成膜。 Further, in the first film formation step, it is preferable to form a film so as to contain at least one of In, Ga, Sn, Zn, and Cd, and it is preferable to contain at least one of In, Sn, Zn, and Ga. In the film formation method, it is preferable to form a film (for example, In-O system) so as to contain at least one of In, Ga, and Zn. Further, it is preferred to form a film so as to contain at least In.

特別是，在第1成膜步驟及後述的第2成膜步驟中，較佳為以第1區域18A及第2區域18B分別含有In的方式進行成膜，且使第1區域18A的In原子組成比率高於第2區域18B的In原子組成比率。原因是，藉由提高第1區域18A的In組成比率，而可獲得電子親和力相對增大的傾向，並且傳導載子容易集中在第1區域18A中。另外的原因是，使In含有率增大，會容易使傳導載子濃度增大，因此容易獲得高載子遷移率。 In particular, in the first film formation step and the second film formation step to be described later, it is preferable that the first region 18A and the second region 18B are formed to contain In, and the In atom of the first region 18A is preferably formed. The composition ratio is higher than the In atomic composition ratio of the second region 18B. The reason is that by increasing the In composition ratio of the first region 18A, the electron affinity is relatively increased, and the conductive carriers are easily concentrated in the first region 18A. Another reason is that by increasing the In content, it is easy to increase the concentration of the conductive carrier, and thus it is easy to obtain a high carrier mobility.

就與上述相同的觀點而言，在第1成膜步驟及後述的第2成膜步驟中，較佳為以第1區域18A及第2區域18B分別含有Ga的方式進行成膜，且使第1區域18A的Ga原子組成比率低於第2區域18B的Ga原子組成比率。 In the first film forming step and the second film forming step to be described later, it is preferable that the first region 18A and the second region 18B contain Ga so as to form a film, and the film is formed. The Ga atomic composition ratio of the region 18A is lower than the Ga atom composition ratio of the second region 18B.

就與上述相同的觀點而言，在第1成膜步驟及後述的第2成 膜步驟中，較佳為使用濺鍍法在成膜室內，一邊流通包含氧氣的氣體，一邊將第1區域18A及第2區域18B成膜；且在第1成膜步驟中，與在第2成膜步驟時所流通的氧氣的流量相比，流通更少的流量的氧氣。 In the same viewpoint as described above, the first film forming step and the second film described later are In the film step, it is preferable to form the first region 18A and the second region 18B while flowing a gas containing oxygen in the film forming chamber by sputtering, and in the first film forming step, and in the second film forming step. At a flow rate of oxygen flowing through the film forming step, less flow of oxygen is circulated.

另外，關於上述組成或組成比、膜厚，可藉由螢光X射線分析裝置進行確認。 Further, the above composition or composition ratio and film thickness can be confirmed by a fluorescent X-ray analyzer.

另外，在第1成膜步驟中，較佳為以第1區域18A包含選自於由In、Ga、Zn、Mg、Al、Sn、Sb、Cd、及Ge所組成的群組中的至少二種的方式進行成膜(例如In-Zn-O系、In-Ga-O系、Ga-Zn-O系)，特別是，就相對於波長420 nm的光照射而可顯著地抑制臨限值位移量的觀點而言，較佳為以第1區域18A含有In與Zn的方式進行成膜。 Further, in the first film formation step, it is preferable that the first region 18A includes at least two selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge. Film formation (for example, In-Zn-O system, In-Ga-O system, Ga-Zn-O system), in particular, can significantly suppress the threshold value with respect to light irradiation at a wavelength of 420 nm. From the viewpoint of the amount of displacement, it is preferable to form a film so that the first region 18A contains In and Zn.

而且，在第1成膜步驟中，較佳為以第1區域18A含有In、Ga(或Sn)及Zn的全部的方式進行成膜。即較佳為，在第1區域18A的組成中含有In(a)Ga(b)Zn(c)O(d)(a,b,c,d>0)。 Further, in the first film formation step, it is preferable to form the film in such a manner that the first region 18A contains all of In, Ga (or Sn), and Zn. That is, it is preferable that In (a) Ga (b) Zn (c) O (d) (a, b, c, d > 0) is contained in the composition of the first region 18A.

特別是，較佳為第1區域18A將In、Ga(或Sn)、Zn以及O作為主要的構成元素。另外，所謂「主要的構成元素」，是指相對於第1區域18A的全部構成元素，In、Ga(或Sn)、Zn以及O的組成比例為全體的98%以上。因此，在第1區域18A中亦可包含如後述的Mg等其他元素。 In particular, it is preferable that the first region 18A has In, Ga (or Sn), Zn, and O as main constituent elements. In addition, the "main constituent element" means that the composition ratio of In, Ga (or Sn), Zn, and O is 98% or more of the total constituent elements of the first region 18A. Therefore, other elements such as Mg described later may be included in the first region 18A.

另外，在第1成膜步驟中，較佳為以第1區域18A的膜厚為10 nm以下的方式進行成膜。第1區域18A中，較佳為如上 所述般，使用容易實現高遷移率化的IZO或極富In的IGZO膜，但此種高遷移率膜由於載子濃度高，因此有相對難夾止(pinch off)、閾值大且向負側位移的可能性。因此，藉由將第1區域18A的膜厚設為10 nm以下，而可避免：氧化物半導體層18中的總載子濃度成為過量的狀態而難以夾止。 Further, in the first film formation step, it is preferable to form the film so that the film thickness of the first region 18A is 10 nm or less. In the first region 18A, preferably as above As described above, an IZO or an In-rich IGZO film which is easy to achieve high mobility is used, but such a high mobility film has a relatively high pinch concentration, and thus has a relatively difficult pinch off, a large threshold, and a negative The possibility of side displacement. Therefore, by setting the film thickness of the first region 18A to 10 nm or less, it is possible to avoid that the total carrier concentration in the oxide semiconductor layer 18 is excessive and it is difficult to pinch.

第1區域18A的導電率較佳為設為10-6 Scm-1以上且未滿102 Scm-1。導電率更佳為設為10-4 Scm-1以上且未滿102 Scm-1，尤佳為設為10-1 Scm-1以上且未滿102 Scm-1。 The electric conductivity of the first region 18A is preferably set to 10 -6 Scm -1 or more and less than 10 2 Scm -1 . The electric conductivity is more preferably 10 -4 Scm -1 or more and less than 10 2 Scm -1 , and particularly preferably 10 -1 Scm -1 or more and less than 10 2 Scm -1 .

-第2成膜步驟- -Second film forming step -

在第2成膜步驟中，將包含選自於由In、Ga、Zn、Mg、Al、Sn、Sb、Cd、及Ge所組成的群組中的至少一種且導電率小於第1區域18A的第2區域18B，在第1區域18A的表面藉由濺鍍法而成膜，且將第2區域18B的至少成膜開始時的成膜壓力調整為2.0 Pa以上、13.0 Pa以下。 In the second film formation step, at least one selected from the group consisting of In, Ga, Zn, Mg, Al, Sn, Sb, Cd, and Ge is included and the conductivity is smaller than the first region 18A. In the second region 18B, the surface of the first region 18A is formed by a sputtering method, and the film formation pressure at the start of at least film formation of the second region 18B is adjusted to 2.0 Pa or more and 13.0 Pa or less.

第2成膜步驟中的第2區域18B的成膜方法與第1成膜步驟不同，以使用濺鍍法為前提。濺鍍法的較佳的條件等與第1成膜步驟中所詳細闡述的條件相同。就提高生產性或抑制雜質混入的觀點而言，較佳為藉由濺鍍法連續進行第1成膜步驟與第2成膜步驟的成膜。 The film formation method of the second region 18B in the second film formation step is different from the first film formation step, and the sputtering method is used as a premise. The preferable conditions and the like of the sputtering method are the same as those described in detail in the first film formation step. From the viewpoint of improving productivity or suppressing the incorporation of impurities, it is preferred to continuously perform film formation in the first film formation step and the second film formation step by sputtering.

第2成膜步驟中的成膜開始時的成膜壓力較佳為5.0 Pa以上且未滿12.0 Pa。原因是，相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為1 V以下。另外的原因是，若將成 膜開始時的成膜壓力調整為5.0 Pa以上，則可緩和相對於波長420 nm的光照射的臨限值位移量的成膜壓力依存性。即原因是，若成膜壓力為5.0 Pa以上，則即便成膜壓力暫時變動，亦可抑制臨限值位移量的變動。 The film formation pressure at the start of film formation in the second film formation step is preferably 5.0 Pa or more and less than 12.0 Pa. The reason is that the absolute value of the temporary displacement amount |ΔVth | is 1 V or less with respect to the light irradiation at a wavelength of 420 nm. Another reason is that if it will become When the film formation pressure at the start of the film is adjusted to 5.0 Pa or more, the film formation pressure dependency with respect to the threshold displacement amount of the light irradiation at a wavelength of 420 nm can be alleviated. In other words, when the film formation pressure is 5.0 Pa or more, even if the film formation pressure temporarily changes, the fluctuation of the threshold displacement amount can be suppressed.

另外，第2成膜步驟中的成膜開始時的成膜壓力較佳為調整為10.0 Pa以下。原因是，即便成膜壓力在成膜壓力為10.0 Pa以下的範圍內暫時變動，亦可抑制臨限值位移量的變動。 In addition, the film formation pressure at the start of film formation in the second film formation step is preferably adjusted to 10.0 Pa or less. The reason is that even if the film formation pressure temporarily changes within a range in which the film formation pressure is 10.0 Pa or less, fluctuations in the threshold displacement amount can be suppressed.

而且，較佳為將第2成膜步驟中的成膜開始時的成膜壓力調整為8.0 Pa以下。原因是，可抑制成膜速度極端下降。另外，關於成膜壓力與成膜速度的關係，存在：隨著成膜壓力大致自1 Pa以上起變高，而成膜速度下降的關係。 Moreover, it is preferable to adjust the film formation pressure at the start of film formation in the second film formation step to 8.0 Pa or less. The reason is that the film formation speed can be suppressed from being extremely lowered. In addition, the relationship between the film formation pressure and the film formation rate is such that the film formation pressure is increased from approximately 1 Pa or more, and the film formation speed is lowered.

另外，在第2成膜步驟中，就縮短成膜時間的觀點而言，較佳為：在成膜中途，將成膜壓力切換成低於成膜開始時的成膜壓力的壓力。具體而言，藉由成膜開始時的成膜壓力將第2區域18B成膜至最初的5 nm為止，並藉由未滿1.0 Pa的成膜壓力將第2區域18B的其餘部分成膜。 Further, in the second film formation step, from the viewpoint of shortening the film formation time, it is preferable to switch the film formation pressure to a pressure lower than the film formation pressure at the start of film formation in the middle of film formation. Specifically, the second region 18B is formed by film formation pressure at the start of film formation to the first 5 nm, and the remaining portion of the second region 18B is formed by a film formation pressure of less than 1.0 Pa.

藉此，在成膜開始時，一邊將成膜壓力調整為2.0 Pa以上、13.0 Pa以下而抑制對第1區域18A的電漿損傷，一邊緩慢地將第2區域18B成膜，自成膜中途起，由於在第1區域18A的表面已存在第2區域18B的一部分，因此難以對第1區域18A造成電漿損傷，因此將成膜壓力調整為未滿1.0 Pa，將其餘的第2區域18B快速地成膜，而可縮短成膜時間。 In the meantime, the film formation pressure is adjusted to 2.0 Pa or more and 13.0 Pa or less, and the plasma damage to the first region 18A is suppressed, and the second region 18B is gradually formed into a film, and the film is formed halfway through the film formation. Since a part of the second region 18B is already present on the surface of the first region 18A, it is difficult to cause plasma damage to the first region 18A. Therefore, the film formation pressure is adjusted to less than 1.0 Pa, and the remaining second region 18B is used. Film formation is rapid, and film formation time can be shortened.

另外，第2區域18B的膜厚較佳為設為第1區域18A(例如設為10 nm以下)的膜厚以上。原因是，特別是，若膜厚超過10 nm，則可期待抑制開路電流(OFF current)的降低或S值的劣化。另外，第2區域18B的膜厚較佳為設為120 nm以下、特佳為設為未滿70 nm。原因是，源極電極20、汲極電極22與第1區域18A的電阻增大，結果可抑制導致遷移率的降低。 In addition, the film thickness of the second region 18B is preferably equal to or greater than the film thickness of the first region 18A (for example, 10 nm or less). The reason is that, in particular, when the film thickness exceeds 10 nm, it is expected to suppress a decrease in the open current (OFF current) or a deterioration in the S value. Further, the film thickness of the second region 18B is preferably 120 nm or less, and particularly preferably less than 70 nm. The reason is that the electric resistance of the source electrode 20 and the drain electrode 22 and the first region 18A is increased, and as a result, the decrease in mobility can be suppressed.

關於第2區域18B的組成的較佳的條件，與第1成膜步驟中所詳細闡述的條件相同。例如在第2成膜步驟中，較佳為以第2區域18B含有In、Ga(或Sn)及Zn的全部的方式進行成膜。 The preferable conditions regarding the composition of the second region 18B are the same as those described in detail in the first film formation step. For example, in the second film formation step, it is preferable to form the film in such a manner that the second region 18B contains all of In, Ga (or Sn), and Zn.

將第1區域18A及第2區域18B進行濺鍍成膜時的極限真空度(ultimate vacuum)，並無特別限定，較佳為2.0×10-5 Pa以下，更佳為1.0×10-6 Pa左右。由於與真空度相對應的H2O成分摻入薄膜內，並且載子密度依存於真空度而變化，因此為了進一步提高本實施方式的效果，較佳為上述真空度。 The ultimate vacuum when the first region 18A and the second region 18B are sputtered into a film is not particularly limited, but is preferably 2.0 × 10 -5 Pa or less, more preferably 1.0 × 10 -6 Pa. about. Since the H 2 O component corresponding to the degree of vacuum is incorporated in the film and the carrier density varies depending on the degree of vacuum, in order to further improve the effect of the present embodiment, the degree of vacuum is preferably used.

另外，就抑制磁力線橫切基板、樣品夾(sample folder)而電漿不穩定化(密度降低的因素)的觀點而言，使第1區域18A及第2區域18B進行濺鍍成膜時的基板12與靶的距離，較佳為50 mm以上。另外，就抑制成膜速率降低，而設為適合於製造的成膜速率的觀點而言，上述距離較佳為150 mm以下。 In addition, the substrate in which the first region 18A and the second region 18B are sputter-deposited is suppressed from the viewpoint of suppressing the magnetic field from crossing the substrate and the sample folder and destabilizing the plasma (a factor of density reduction). 12 The distance from the target is preferably 50 mm or more. Further, from the viewpoint of suppressing a decrease in the film formation rate and setting it as a film formation rate suitable for production, the above distance is preferably 150 mm or less.

第2區域18B的導電率以低於第1區域18A為前提，可取與第1區域18A相同的範圍，但較佳為設為10-7 Scm-1以上且未滿101 Scm-1。更佳為設為10-7 Scm-1以上且未滿10-1 Scm-1。 The conductivity of the second region 18B is lower than that of the first region 18A, and may be the same as the first region 18A. However, it is preferably 10 -7 Scm -1 or more and less than 10 1 Scm -1 . More preferably, it is set to 10 -7 Scm -1 or more and less than 10 -1 Scm -1 .

另外，氧化物半導體層18的各區域的載子濃度(換言之為導電率)的控制，除了藉由組成調變而進行外，亦可藉由控制成膜時的氧氣分壓而進行。 Further, the control of the carrier concentration (in other words, the conductivity) of each region of the oxide semiconductor layer 18 can be performed by controlling the oxygen partial pressure at the time of film formation, in addition to the composition modulation.

氧濃度的控制具體而言，可藉由分別控制第1區域18A及第2區域18B中的成膜時的氧氣分壓而進行。若提高成膜時的氧氣分壓，則可降低載子濃度，隨之可期待開路電流的降低。另一方面，若降低成膜時的氧氣分壓，則可增大載子濃度，隨之可期待場效遷移率的增大。另外，例如藉由在第2區域18B的成膜後實施照射氧自由基或臭氧的處理，亦可促進膜的氧化，並且降低第2區域18B中的氧缺陷量。 Specifically, the control of the oxygen concentration can be performed by controlling the partial pressure of oxygen at the time of film formation in the first region 18A and the second region 18B, respectively. When the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be lowered, and accordingly, the open circuit current can be expected to be lowered. On the other hand, if the partial pressure of oxygen at the time of film formation is lowered, the concentration of the carrier can be increased, and accordingly, the field-effect mobility can be expected to increase. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after film formation in the second region 18B, oxidation of the film can be promoted, and the amount of oxygen deficiency in the second region 18B can be reduced.

另外，藉由在氧化物半導體層18所含的例如Zn的一部分中摻雜帶隙更寬的元素離子，而可賦予伴隨光學帶隙增大的光照射穩定性。具體而言，可藉由摻雜Mg而增大膜的帶隙。例如藉由在氧化物半導體層18的各區域中摻雜Mg，而與控制In、Ga、Zn等的組成比的體系相比，可在保持積層膜的帶分布(profile)的狀態下增大帶隙。 In addition, by doping a part of Zn, which is contained in the oxide semiconductor layer 18, for example, a group ion having a wider band gap, it is possible to impart light irradiation stability accompanying an increase in optical band gap. Specifically, the band gap of the film can be increased by doping Mg. For example, by doping Mg in each region of the oxide semiconductor layer 18, it is possible to increase the band profile of the laminated film as compared with a system for controlling the composition ratio of In, Ga, Zn, or the like. Bandgap.

並且，有機EL所用的藍色發光層表現出在波長450 nm左右具有波峰的寬的發光，因此在假定氧化物半導體層18的光學帶隙相對窄、且在該區域具有光學吸收的情況下，會產生引起電晶體的臨限值位移的問題。因此，特別是作為有機EL驅動用途中所用的TFT，較佳為氧化物半導體層18所用的材料的帶隙更大。 Further, the blue light-emitting layer used for the organic EL exhibits a broad light emission having a peak at a wavelength of about 450 nm, and therefore, assuming that the optical band gap of the oxide semiconductor layer 18 is relatively narrow and optical absorption is performed in the region, There is a problem that causes a threshold shift of the transistor. Therefore, in particular, as the TFT used in the organic EL driving use, it is preferable that the material used for the oxide semiconductor layer 18 has a larger band gap.

另外，第1區域18A等的載子濃度亦可藉由摻雜陽離子而任 意地控制。在欲增加載子濃度時，只要摻雜容易成為價數相對大的陽離子的材料(例如Ti、Zr、Hf、Ta等)即可。但在摻雜價數大的陽離子時，由於氧化物半導體膜的構成元素數增加，因此在成膜製程的簡化、低成本化的方面不利，因此較佳為藉由氧濃度(氧缺陷量)控制載子濃度。 In addition, the carrier concentration of the first region 18A or the like can also be doped by doping cations. Controlled by intention. When it is desired to increase the concentration of the carrier, it is only necessary to dope the material (for example, Ti, Zr, Hf, Ta, etc.) which is likely to be a cation having a relatively large valence. However, when a cation having a large valence is used, the number of constituent elements of the oxide semiconductor film is increased, which is disadvantageous in terms of simplification and cost reduction of the film formation process, and therefore it is preferable to use oxygen concentration (oxygen deficiency amount). Control the carrier concentration.

-圖案化步驟- - Patterning steps -

接著，進行將氧化物半導體層18圖案化的圖案化步驟。圖案化可藉由光刻法及蝕刻進行。具體而言，在殘存的部分藉由光刻法形成光阻圖案(resist pattern)，藉由鹽酸、硝酸、稀硫酸、或磷酸、硝酸及乙酸的混合液等的酸溶液，進行濕式蝕刻而形成圖案。另外，亦可使用乾式蝕刻進行圖案化，並無特別限定。另外，氧化物半導體層18的圖案化可在第1成膜步驟後對第1區域18A隨時進行，亦可在第2成膜步驟後對第2區域18B隨時進行，但就抑制對第1區域造成蝕刻損傷等的觀點而言，較佳為在第2成膜步驟後將第1區域18A及第2區域18B圖案化。 Next, a patterning step of patterning the oxide semiconductor layer 18 is performed. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed by photolithography in the remaining portion, and wet etching is performed by an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid. Form a pattern. Further, it can be patterned by dry etching, and is not particularly limited. Further, the patterning of the oxide semiconductor layer 18 may be performed on the first region 18A at any time after the first film formation step, or may be performed on the second region 18B after the second film formation step, but the first region is suppressed. From the viewpoint of causing etching damage or the like, it is preferable to pattern the first region 18A and the second region 18B after the second film formation step.

另外，亦可不使用光刻法及蝕刻的圖案化方法，而根據用途(解析度)，在上述第1成膜步驟及第2成膜步驟中使用：在濺鍍成膜的同時，使用可圖案化的金屬遮罩的圖案化方法。 Further, in the first film forming step and the second film forming step, the first film forming step and the second film forming step may be used depending on the application (resolution) without using a patterning method of photolithography and etching, and a pattern may be used while being formed by sputtering. The patterning method of the metal mask.

-熱處理步驟- - heat treatment step -

在氧化物半導體層18的形成步驟中、或第2成膜步驟後，較佳為進行(將基板12)熱處理的熱處理步驟。另外，所謂「氧化物半導體層18的形成步驟中的熱處理」，是指成膜時的基板加熱。 另外，「第2成膜步驟後的熱處理」可在氧化物半導體層18剛成膜後進行，亦可在後述的源極電極20、汲極電極22的形成等全部完畢後進行。 In the step of forming the oxide semiconductor layer 18 or after the second film forming step, a heat treatment step of heat-treating (substrate 12) is preferably performed. In addition, the "heat treatment in the step of forming the oxide semiconductor layer 18" means heating of the substrate during film formation. In addition, the "heat treatment after the second film formation step" may be performed immediately after the formation of the oxide semiconductor layer 18, or may be performed after the formation of the source electrode 20 and the gate electrode 22, which will be described later.

為了抑制電氣特性的不均，熱處理溫度較佳為300℃以上、600℃以下。另外，後退火(post annealing)中的氣體環境可設為氧化性氣體環境或惰性氣體環境，較佳為設為含有氧氣的氣體環境。若在氧化性氣體環境中實施後退火，則氧化物半導體層中的氧難以逃逸而抑制產生多餘載子，並且難以引起電氣特性不均。熱處理可對基板逐個進行，亦可投入多個至潔淨烘箱等中而進行。另外，若熱處理溫度為600℃以下，則可抑制：在第1區域18A與第2區域18B之間引起陽離子的相互擴散而2個區域交合。 In order to suppress unevenness in electrical characteristics, the heat treatment temperature is preferably 300 ° C or more and 600 ° C or less. Further, the gas atmosphere in the post annealing may be an oxidizing gas atmosphere or an inert gas atmosphere, and is preferably a gas atmosphere containing oxygen. When post-annealing is performed in an oxidizing gas atmosphere, oxygen in the oxide semiconductor layer is hard to escape, and generation of excess carriers is suppressed, and it is difficult to cause uneven electrical characteristics. The heat treatment may be performed one by one on the substrate, or may be carried out in a plurality of places to a clean oven or the like. In addition, when the heat treatment temperature is 600 ° C or lower, it is possible to suppress mutual diffusion of cations between the first region 18A and the second region 18B and to form two regions.

另外，第1區域18A與第2區域18B中是否引起陽離子的相互擴散，例如可藉由進行剖面TEM的分析而確認。另外，亦可省略熱處理步驟。 Further, whether or not the cation is caused to diffuse in the first region 18A and the second region 18B can be confirmed, for example, by performing cross-sectional TEM analysis. In addition, the heat treatment step may also be omitted.

特佳為，將熱處理溫度設為300℃以上且未滿450℃。原因是，TFT不依存於第1區域的組成，而更可靠地運作。 Particularly preferably, the heat treatment temperature is set to 300 ° C or more and less than 450 ° C. The reason is that the TFT does not depend on the composition of the first area, but operates more reliably.

另外，在熱處理氣體環境的濕度極高時，膜中容易摻入水分，而容易引起電氣特性的不均，因此較佳為在室溫下的相對濕度為50%以下的環境進行熱處理。而且，熱處理時間並無特別限定，但考慮到膜溫度達到均勻所需要的時間等，較佳為至少保持10分鐘以上。 Further, when the humidity of the heat treatment gas atmosphere is extremely high, water is easily incorporated into the film, and unevenness in electrical characteristics is likely to occur. Therefore, it is preferred to heat-treat in an environment where the relative humidity at room temperature is 50% or less. Further, the heat treatment time is not particularly limited, but it is preferably kept at least for 10 minutes or more in consideration of the time required for the film temperature to be uniform.

-電極形成步驟- - Electrode forming step -

在氧化物半導體層18的形成步驟後、或熱處理步驟後，進行在第2區域18B上形成源極電極20及汲極電極22的電極形成步驟。但是，就形成歐姆接觸(ohmic contact)的觀點而言，較佳為在電極形成步驟後進行熱處理步驟。在電極形成步驟中，可使用與上述閘極電極的形成方法相同的形成方法。 After the step of forming the oxide semiconductor layer 18 or after the heat treatment step, an electrode forming step of forming the source electrode 20 and the drain electrode 22 in the second region 18B is performed. However, from the viewpoint of forming an ohmic contact, it is preferred to carry out the heat treatment step after the electrode forming step. In the electrode forming step, the same forming method as that of the above-described gate electrode can be used.

作為構成源極電極20、汲極電極22的導電膜，可使用具有高導電性者，例如使用Al、Mo、Cr、Ta、Ti、Au、Ag等金屬，Al-Nd、Ag合金，氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等金屬氧化物的導電膜等而形成。作為源極電極20、汲極電極22，可將這些導電膜製成單層結構、或2層以上的積層結構而使用。 As the conductive film constituting the source electrode 20 and the drain electrode 22, those having high conductivity can be used, for example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al-Nd, Ag alloy, and tin oxide can be used. A conductive film of a metal oxide such as zinc oxide, indium oxide, indium tin oxide (ITO) or indium zinc oxide (IZO) is formed. As the source electrode 20 and the drain electrode 22, these conductive films can be used in a single layer structure or a laminated structure of two or more layers.

在電極形成步驟的蝕刻時，在氧化物半導體層18上可具有用以蝕刻保護的保護膜。保護膜的形成可與氧化物半導體層18的成膜連續進行，亦可在氧化物半導體層18的圖案化後進行。 At the time of etching of the electrode forming step, a protective film for etching protection may be provided on the oxide semiconductor layer 18. The formation of the protective film may be performed continuously with the formation of the oxide semiconductor layer 18 or after the patterning of the oxide semiconductor layer 18.

另外，藉由使用本實施方式的TFT 10，而不在氧化物半導體層18上使用用以降低對於光照射的特性劣化的保護膜等，而可獲得高遷移率、與高光照射穩定性，當然亦可在氧化物半導體層18上設置如上所述的保護膜。例如藉由設置如將紫外區域(波長為400 nm以下)的光吸收、反射的保護膜，而亦可進一步提高對於光照射的穩定性。 In addition, by using the TFT 10 of the present embodiment, a high mobility and high light irradiation stability can be obtained without using a protective film or the like for reducing deterioration of characteristics against light irradiation on the oxide semiconductor layer 18. A protective film as described above may be provided on the oxide semiconductor layer 18. For example, by providing a protective film that absorbs and reflects light in an ultraviolet region (having a wavelength of 400 nm or less), the stability against light irradiation can be further improved.

根據以上順序，可製作如圖1A所示的底部閘極型且頂部接觸型的TFT 10。另外，根據本實施方式的TFT的製造方法， 第1區域18A或第2區域18B可根據其構成材料而在低溫(例如400℃以下)下成膜，因此，若基板12使用樹脂基板等，則整個TFT 10可在低溫下製作。 According to the above sequence, the bottom gate type and top contact type TFT 10 as shown in Fig. 1A can be fabricated. Further, according to the method of manufacturing the TFT of the present embodiment, The first region 18A or the second region 18B can be formed at a low temperature (for example, 400 ° C or lower) depending on the constituent material. Therefore, when the substrate 12 is made of a resin substrate or the like, the entire TFT 10 can be produced at a low temperature.

另外，對本發明的特定實施方式進行了詳細地說明，但本發明並不限定於這些實施方式，所屬技術領域具有通常知識者明白在本發明的範圍內可進行其他的各種實施方式，例如上述多個實施方式可適當組合而實施。 In addition, the specific embodiments of the present invention have been described in detail, but the present invention is not limited to the embodiments, and those skilled in the art will appreciate that various other embodiments can be made within the scope of the present invention, such as the above. Embodiments can be implemented in appropriate combination.

3. 應用 3. Application

以上所說明的本實施方式中所製造的場效電晶體，其用途並無特別限定，例如可較佳地用於電光學裝置(例如液晶顯示裝置、有機EL(Electro Luminescence)顯示裝置、無機EL顯示裝置等顯示裝置等)中的驅動元件、特別是大面積裝置(device)中。 The field effect transistor manufactured in the present embodiment described above is not particularly limited in use, and can be preferably used, for example, in an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, or an inorganic EL. A drive element in a display device or the like, such as a display device, in particular a large-area device.

而且，本實施方式的場效電晶體特別適合於：使用樹脂基板的、可在低溫製程中製作的裝置(例如可撓性顯示器等)，並且可較佳地用作X射線感測器等各種感測器、微機電系統(Micro Electro Mechanical System，MEMS)等各種電子裝置中的驅動元件(驅動電路)。 Further, the field effect transistor of the present embodiment is particularly suitable for a device (for example, a flexible display or the like) which can be fabricated in a low temperature process using a resin substrate, and can be preferably used as an X-ray sensor or the like. A driving element (drive circuit) in various electronic devices such as a sensor and a micro electro mechanical system (MEMS).

4. 電光學裝置及感測器 4. Electro-optical device and sensor

本實施方式的電光學裝置或感測器具備：上述場效電晶體(TFT 10)而構成。 The electro-optical device or the sensor of the present embodiment includes the field effect transistor (TFT 10).

作為電光學裝置的例子，有顯示裝置(例如液晶顯示裝置、有機EL顯示裝置、無機EL顯示裝置等)。 Examples of the electro-optical device include display devices (for example, liquid crystal display devices, organic EL display devices, inorganic EL display devices, and the like).

作為感測器的例子，較佳為電荷耦合元件(Charge Coupled Device，CCD)或互補金屬氧化物半導體(Complementary Metal Oxide Semiconductor，CMOS)等影像感測器、或X射線感測器等。 As an example of the sensor, an image sensor such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS), or an X-ray sensor or the like is preferable.

使用本實施方式的TFT的電光學裝置及感測器，任一者的特性的面內均勻性高。另外，此處所謂的「特性」，在為電光學裝置(顯示裝置)時是顯示特性，在為感測器時是靈敏度(sensitivity)特性。 The electro-optical device and the sensor using the TFT of the present embodiment have high in-plane uniformity of characteristics of either one. In addition, the "characteristic" as used herein is a display characteristic when it is an electro-optical device (display device), and is a sensitivity characteristic when it is a sensor.

以下，作為具備藉由本實施方式而製造的場效電晶體的電光學裝置或感測器的代表例，對液晶顯示裝置、有機EL顯示裝置、X射線感測器進行說明。 Hereinafter, a liquid crystal display device, an organic EL display device, and an X-ray sensor will be described as representative examples of an electro-optical device or a sensor including the field effect transistor manufactured by the present embodiment.

5. 液晶顯示裝置 5. Liquid crystal display device

圖2表示本發明的電光學裝置的一個實施方式的液晶顯示裝置的一部分的概略剖面圖，圖3表示該液晶顯示裝置的電氣配線的概略構成圖。 2 is a schematic cross-sectional view showing a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and FIG. 3 is a schematic configuration view showing electrical wiring of the liquid crystal display device.

如圖2所示，本實施方式的液晶顯示裝置100具備以下構成：圖1A所示的底部閘極型且頂部接觸型的TFT 10；被畫素下部電極104及其對向上部電極106夾持的液晶層108，所述畫素下部電極104位在TFT 10的藉由鈍化層(passivation layer)102保護的氧化物半導體層18上；以及RGB彩色濾光器110，對應於各畫素且用以發出不同顏色的光，並且，在TFT 10的基板12側及RGB彩色濾光器110上分別具備偏光板112a、偏光板112b。 As shown in FIG. 2, the liquid crystal display device 100 of the present embodiment has a bottom gate type and top contact type TFT 10 shown in FIG. 1A; a pixel lower electrode 104 and its upper electrode 106 are sandwiched. The liquid crystal layer 108, the pixel lower electrode 104 is located on the oxide semiconductor layer 18 of the TFT 10 protected by a passivation layer 102; and the RGB color filter 110 corresponds to each pixel and is used Light of a different color is emitted, and a polarizing plate 112a and a polarizing plate 112b are provided on the substrate 12 side of the TFT 10 and the RGB color filter 110, respectively.

另外，如圖3所示般，本實施方式的液晶顯示裝置100 具備：彼此平行的多個閘極配線112；以及，與該閘極配線112交叉，而彼此平行的資料配線114。此處，閘極配線112與資料配線114為電性絕緣。在閘極配線112與資料配線114的交叉部附近具備TFT 10。 In addition, as shown in FIG. 3, the liquid crystal display device 100 of the present embodiment is provided. A plurality of gate wirings 112 that are parallel to each other and a data wiring 114 that is parallel to the gate wirings 112 and are parallel to each other. Here, the gate wiring 112 and the data wiring 114 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection of the gate wiring 112 and the data wiring 114.

TFT 10的閘極電極14與閘極配線112連接，TFT 10的源極電極20與資料配線114連接。另外，TFT 10的汲極電極22經由設置於鈍化層102的接觸孔116(在接觸孔116中嵌入導電體)而與畫素下部電極104連接。該畫素下部電極104與接地的對向上部電極106一起構成電容器118。 The gate electrode 14 of the TFT 10 is connected to the gate wiring 112, and the source electrode 20 of the TFT 10 is connected to the data wiring 114. Further, the drain electrode 22 of the TFT 10 is connected to the pixel lower electrode 104 via a contact hole 116 provided in the passivation layer 102 (a conductor is embedded in the contact hole 116). The pixel lower electrode 104 and the grounded pair upper electrode 106 together form a capacitor 118.

本實施方式的TFT由於光照射時的穩定性非常高，因此液晶顯示裝置的可靠性增加。 Since the TFT of the present embodiment has a very high stability at the time of light irradiation, the reliability of the liquid crystal display device increases.

6. 有機EL顯示裝置 6. Organic EL display device

圖4表示本發明的電光學裝置的一個實施方式的主動矩陣式有機EL顯示裝置的一部分的概略剖面圖，圖5表示電氣配線的概略構成圖。 4 is a schematic cross-sectional view showing a part of an active matrix organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 5 is a schematic configuration view of the electric wiring.

有機EL顯示裝置的驅動方式具有：單純矩陣式與主動矩陣式這2種。單純矩陣式具有能以低成本製作的優點，但由於是一條一條選擇掃描線而使畫素發光，因此掃描線數與每條掃描線的發光時間成反比例。因此，難以實現高精細化、大畫面化。主動矩陣式由於在每個畫素中形成電晶體或電容器，因此製造成本變高，但不具有如單純矩陣式般不能增加掃描線數的問題，因此適合於高精細化、大畫面化。 The driving method of the organic EL display device has two types: a simple matrix type and an active matrix type. The simple matrix type has the advantage of being able to be manufactured at low cost, but since the pixels are illuminated by selecting one scanning line, the number of scanning lines is inversely proportional to the lighting time of each scanning line. Therefore, it is difficult to achieve high definition and large screen. Since the active matrix type has a transistor or a capacitor formed in each pixel, the manufacturing cost is high, but the problem that the number of scanning lines cannot be increased as in the simple matrix type is not suitable for high definition and large screen.

本實施方式的主動矩陣式有機EL顯示裝置200中，圖1A所示的底部閘極型且頂部接觸型的TFT 10是設置於基板12上。該基板12例如為可撓性支撐體、且為聚萘二甲酸乙二酯(polyethylene naphthalate，PEN)等塑膠膜，為了具有絕緣性，而在表面具有基板絕緣層202。在基板絕緣層202上設置有經圖案化的彩色濾光器層204。在驅動TFT部具有閘極電極14，進而閘極絕緣膜16設置於閘極電極14上。為了電性連接，而在閘極絕緣膜16的一部分開有連接孔(connection hole)。在驅動TFT部設置有氧化物半導體層18，在氧化物半導體層18上設置有源極電極20及汲極電極22。汲極電極22與有機EL元件的畫素電極(陽極)206為連續的一體，且由相同材料、相同步驟形成。開關TFT的汲極電極22與驅動TFT是：藉由連接電極208而經由連接孔進行電性連接。而且，由絕緣膜210覆蓋除畫素電極部的形成了有機EL元件的部分以外的全體。在畫素電極部上，形成設置有包含發光層的有機層212及陰極214的有機EL元件部。 In the active matrix organic EL display device 200 of the present embodiment, the bottom gate type and top contact type TFT 10 shown in FIG. 1A is provided on the substrate 12. The substrate 12 is, for example, a flexible support and a plastic film such as polyethylene naphthalate (PEN), and has a substrate insulating layer 202 on the surface in order to have insulating properties. A patterned color filter layer 204 is disposed on the substrate insulating layer 202. The driving TFT portion has a gate electrode 14, and further a gate insulating film 16 is provided on the gate electrode 14. For electrical connection, a connection hole is formed in a portion of the gate insulating film 16. The oxide semiconductor layer 18 is provided in the driving TFT portion, and the source electrode 20 and the drain electrode 22 are provided on the oxide semiconductor layer 18. The gate electrode 22 and the pixel electrode (anode) 206 of the organic EL element are continuously integrated, and are formed of the same material and the same steps. The drain electrode 22 of the switching TFT and the driving TFT are electrically connected via a connection hole by the connection electrode 208. In addition, the entire portion of the pixel electrode portion excluding the organic EL element is covered with the insulating film 210. An organic EL element portion provided with an organic layer 212 including a light-emitting layer and a cathode 214 is formed on the pixel portion.

另外，如圖5所示般，本實施方式的有機EL顯示裝置200具備：彼此平行的多個閘極配線220；以及，與該閘極配線220交叉、且彼此平行的資料配線222及驅動配線224。此處，閘極配線220與資料配線222、驅動配線224為電性絕緣。開關用TFT 10b的閘極電極14與閘極配線220連接，開關用TFT 10b的源極電極20與資料配線222連接。另外，開關用TFT 10b的汲極電極22與驅動用TFT 10的閘極電極14連接，並且藉由使用電容器226 而將驅動用TFT 10a保持為接通狀態。驅動用TFT 10a的源極電極20與驅動配線224連接，汲極電極22與有機層212連接。 In addition, as shown in FIG. 5, the organic EL display device 200 of the present embodiment includes a plurality of gate wirings 220 that are parallel to each other, and data wirings 222 and driving wirings that are parallel to the gate wirings 220 and are parallel to each other. 224. Here, the gate wiring 220 is electrically insulated from the data wiring 222 and the driving wiring 224. The gate electrode 14 of the switching TFT 10b is connected to the gate wiring 220, and the source electrode 20 of the switching TFT 10b is connected to the data wiring 222. Further, the drain electrode 22 of the switching TFT 10b is connected to the gate electrode 14 of the driving TFT 10, and by using the capacitor 226 The driving TFT 10a is kept in an ON state. The source electrode 20 of the driving TFT 10a is connected to the driving wiring 224, and the drain electrode 22 is connected to the organic layer 212.

藉由本發明而製造的TFT由於光照射時的穩定性非常高，因此適於製造可靠性高的有機EL顯示裝置。 The TFT manufactured by the present invention is highly stable in light irradiation, and is therefore suitable for manufacturing a highly reliable organic EL display device.

另外，在圖4所示的有機EL顯示裝置中，將有機層212的上部電極作為透明電極而製成頂部發光型，亦可藉由將有機層212的下部電極及TFT的各電極作為透明電極，而製成底部發光型。 Further, in the organic EL display device shown in FIG. 4, the upper electrode of the organic layer 212 is used as a transparent electrode to form a top emission type, and the lower electrode of the organic layer 212 and each electrode of the TFT can be used as a transparent electrode. And made the bottom light type.

7. X射線感測器 7. X-ray sensor

圖6表示作為本發明的感測器的一個實施方式的X射線感測器的一部分的概略剖面圖，圖7表示該X射線感測器的電氣配線的概略構成圖。 6 is a schematic cross-sectional view showing a part of an X-ray sensor which is one embodiment of the sensor of the present invention, and FIG. 7 is a schematic configuration view of the electric wiring of the X-ray sensor.

更具體而言，圖6是將X射線感測器陣列的一部分放大的概略剖面圖。本實施方式的X射線感測器300具備以下的構成：形成於基板12上的TFT 10及電容器310；形成於電容器310上的電荷收集用電極302；X射線轉變層304；以及上部電極306。在TFT 10上設置有鈍化膜308。 More specifically, FIG. 6 is a schematic cross-sectional view showing a part of the X-ray sensor array enlarged. The X-ray sensor 300 of the present embodiment includes a TFT 10 and a capacitor 310 formed on the substrate 12, a charge collection electrode 302 formed on the capacitor 310, an X-ray conversion layer 304, and an upper electrode 306. A passivation film 308 is provided on the TFT 10.

電容器310成為：由電容器用下部電極312與電容器用上部電極314夾持絕緣膜316的結構。電容器用上部電極314與TFT 10的源極電極20及汲極電極22的任一電極(圖6中為汲極電極22)連接。 In the capacitor 310, the insulating film 316 is sandwiched between the capacitor lower electrode 312 and the capacitor upper electrode 314. The capacitor upper electrode 314 is connected to any of the source electrode 20 and the drain electrode 22 of the TFT 10 (the gate electrode 22 in Fig. 6).

電荷收集用電極302設置於電容器310中的電容器用上 部電極314上，並與電容器用上部電極314接觸。 The charge collection electrode 302 is provided on the capacitor in the capacitor 310 The portion electrode 314 is in contact with the capacitor upper electrode 314.

X射線轉變層304為包含非晶硒的層，以覆蓋TFT 10及電容器310的方式設置。 The X-ray conversion layer 304 is a layer containing amorphous selenium, and is disposed to cover the TFT 10 and the capacitor 310.

上部電極306設置於X射線轉變層304上，並與X射線轉變層304接觸。 The upper electrode 306 is disposed on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.

如圖7所示般，本實施方式的X射線感測器300具備：彼此平行的多個閘極配線320；以及，與閘極配線320交叉、且彼此平行的多個資料配線322。此處，閘極配線320與資料配線322為電性絕緣。在閘極配線320與資料配線322的交叉部附近具備TFT 10。 As shown in FIG. 7 , the X-ray sensor 300 of the present embodiment includes a plurality of gate wirings 320 that are parallel to each other, and a plurality of data wirings 322 that cross the gate wirings 320 and are parallel to each other. Here, the gate wiring 320 and the data wiring 322 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection of the gate wiring 320 and the data wiring 322.

TFT 10的閘極電極14與閘極配線320連接，TFT 10的源極電極20與資料配線322連接。另外，TFT 10的汲極電極22與電荷收集用電極302連接，而且該電荷收集用電極302與電容器310連接。 The gate electrode 14 of the TFT 10 is connected to the gate wiring 320, and the source electrode 20 of the TFT 10 is connected to the data wiring 322. Further, the drain electrode 22 of the TFT 10 is connected to the charge collection electrode 302, and the charge collection electrode 302 is connected to the capacitor 310.

在本實施方式的X射線感測器300中，X射線在圖6中自上部(上部電極306側)照射，在X射線轉變層304中生成電子-電洞對。預先藉由上部電極306對該X射線轉變層304施加高電場，藉此所生成的電荷被蓄積於電容器310中，並依序掃描TFT 10而被讀出。 In the X-ray sensor 300 of the present embodiment, the X-rays are irradiated from the upper portion (the upper electrode 306 side) in FIG. 6 to generate an electron-hole pair in the X-ray conversion layer 304. A high electric field is applied to the X-ray conversion layer 304 by the upper electrode 306 in advance, whereby the generated charges are accumulated in the capacitor 310, and the TFTs 10 are sequentially scanned to be read.

本實施方式的X射線感測器300由於具備光照射時的穩定性高的TFT 10，因此可獲得均勻性優異的圖像。 Since the X-ray sensor 300 of the present embodiment includes the TFT 10 having high stability at the time of light irradiation, an image excellent in uniformity can be obtained.

[實施例] [Examples]

以下對實施例進行說明，但本發明並不受這些實施例的任何限定。 The examples are described below, but the invention is not limited by these examples.

<對於TFT特性的第2區域的成膜壓力依存性> <Dependence on film formation pressure in the second region of TFT characteristics>

-實施例1~實施例10及比較例1~比較例3的TFT的製作- - Preparation of TFTs of Examples 1 to 10 and Comparative Examples 1 to 3 -

首先，關於對於TFT特性的第2區域的成膜壓力依存性，藉由製作如以下的實施例1~實施例5及比較例1~比較例3的底部閘極型且頂部接觸型的TFT而進行驗證。 First, regarding the film formation pressure dependency of the second region of the TFT characteristics, the bottom gate type and the top contact type TFTs of the following Examples 1 to 5 and Comparative Examples 1 to 3 were produced. authenticating.

圖8A是實施例及比較例的TFT的平面圖，圖8B是圖8A所示的TFT的A-A線箭頭所視剖面圖。 Fig. 8A is a plan view of a TFT of an embodiment and a comparative example, and Fig. 8B is a cross-sectional view taken along line A-A of the TFT shown in Fig. 8A.

首先，實施例1~實施例5及比較例1~比較例3中，如圖8A及圖8B所示般，藉由使用附有熱氧化膜504的p型Si基板502(1英吋見方、厚度：525 μm、熱氧化膜(SiO2)：100 nm)作為基板，而製作使用熱氧化膜504作為閘極絕緣膜，使用p型Si基板502作為閘極電極的簡易型TFT 500。 First, in the first to fifth embodiments and the comparative example 1 to the comparative example 3, as shown in FIGS. 8A and 8B, a p-type Si substrate 502 with a thermal oxide film 504 is used (1 inch square, A thickness of 525 μm and a thermal oxide film (SiO 2 : 100 nm) were used as a substrate, and a simple TFT 500 using a thermal oxide film 504 as a gate insulating film and a p-type Si substrate 502 as a gate electrode was produced.

具體而言，在附有熱氧化膜504的p型Si基板502上，使用In2O3、Ga2O3、ZnO這3種靶，一邊藉由金屬遮罩覆蓋各區域的成膜部位以外的部位，一邊藉由共濺鍍，將氧化物半導體層的第1區域506與第2區域508成膜(第1成膜步驟及第2成膜步驟)。各區域的成膜條件如以下所述。 Specifically, on the p-type Si substrate 502 with the thermal oxide film 504, three kinds of targets of In 2 O 3 , Ga 2 O 3 , and ZnO are used, and the film formation portions of the respective regions are covered by a metal mask. The first region 506 and the second region 508 of the oxide semiconductor layer are formed by co-sputtering (the first film forming step and the second film forming step). The film formation conditions of the respective regions are as follows.

-第1成膜步驟(第1區域506)的成膜條件- - Film formation conditions of the first film formation step (first region 506) -

In：Ga：Zn組成比=1.0：1.0：1.0 In:Ga:Zn composition ratio =1.0:1.0:1.0

膜厚：10 nm Film thickness: 10 nm

平面尺寸：3 mm×4 mm Plane size: 3 mm × 4 mm

成膜壓力：0.4 Pa Film formation pressure: 0.4 Pa

到達真空度：8.0×10-6 Pa The degree of vacuum reached: 8.0×10 -6 Pa

成膜溫度：室溫(25℃) Film formation temperature: room temperature (25 ° C)

Ar流量：5.07×10-2 Pa．m3/s Ar flow rate: 5.07×10 -2 Pa. m 3 /s

O2流量：3.38×10-4 Pa．m3/s O 2 flow rate: 3.38 × 10 -4 Pa. m 3 /s

基板與靶的距離：120 mm Distance between substrate and target: 120 mm

-第2成膜步驟(第2區域508)的成膜條件- - Film formation conditions of the second film formation step (second region 508) -

In：Ga：Zn組成比=0.5：1.5：1.0 In:Ga:Zn composition ratio =0.5:1.5:1.0

膜厚：50 nm Film thickness: 50 nm

平面尺寸：3 mm×4 mm Plane size: 3 mm × 4 mm

成膜壓力：可變 Film formation pressure: variable

(可變為比較例1：0.4 Pa、比較例2：1.0 Pa、實施例1：2.0 Pa、實施例2：5.0 Pa、實施例3：10.0 Pa、實施例4：12.0 Pa、實施例5：13.0 Pa、比較例3：15.0 Pa這8個值) (variable to Comparative Example 1: 0.4 Pa, Comparative Example 2: 1.0 Pa, Example 1: 2.0 Pa, Example 2: 5.0 Pa, Example 3: 10.0 Pa, Example 4: 12.0 Pa, Example 5: 13.0 Pa, Comparative Example 3: 8 values of 15.0 Pa)

到達真空度：8.0×10-6 Pa The degree of vacuum reached: 8.0×10 -6 Pa

成膜溫度：室溫(25℃) Film formation temperature: room temperature (25 ° C)

Ar流量：5.07×10-2 Pa．m3/s Ar flow rate: 5.07×10 -2 Pa. m 3 /s

O2流量：3.38×10-4 Pa．m3/s O 2 flow rate: 3.38 × 10 -4 Pa. m 3 /s

基板與靶的距離：120 mm Distance between substrate and target: 120 mm

另外，為了獲得上述成膜壓力，而讀取成膜腔室(chamber)的真空度，藉由膜片閥(diaphragm valve)控制壓力。 該膜片閥藉由壓力控制器而以獲得設定壓力的方式進行控制，因此，作為真空度的精度，而要求成膜腔室的真空計的精度與膜片閥壓力控制器的精度這2者。 Further, in order to obtain the above film forming pressure, the degree of vacuum of the film forming chamber is read, and the pressure is controlled by a diaphragm valve. The diaphragm valve is controlled by a pressure controller to obtain a set pressure. Therefore, as the accuracy of the degree of vacuum, the accuracy of the vacuum gauge of the film forming chamber and the accuracy of the diaphragm valve pressure controller are required. .

此處，作為真空計，是使用測定誤差為1%的佳能安內華(Canon-Anelva)公司製造的數位電容計M-340DG-QA/C70，並且作為膜片閥用壓力控制器，是使用測定誤差為0.028 Pa的VAT股份有限公司製造的閥控制器PM-5。 Here, as a vacuum gauge, a digital capacitance meter M-340DG-QA/C70 manufactured by Canon-Anelva Co., Ltd. with a measurement error of 1% is used, and is used as a pressure controller for a diaphragm valve. The valve controller PM-5 manufactured by VAT Co., Ltd. with a measurement error of 0.028 Pa was used.

因此，若將目標成膜壓力設為x[Pa]，則成膜壓力的誤差為x×0.01+0.028[Pa]。 Therefore, when the target film formation pressure is x [Pa], the film formation pressure has an error of x × 0.01 + 0.028 [Pa].

另外，關於組成比的調整，控制投入至各靶的電力而進行。另外，作為組成比的值，使用藉由螢光X射線分析裝置而求出者。 In addition, adjustment of the composition ratio is performed by controlling the electric power input to each target. Further, as a value of the composition ratio, a person obtained by a fluorescent X-ray analyzer is used.

另外，關於在與實施例1~實施例5及比較例1~比較例3的第1區域506及第2區域508相同的條件下實施成膜並製作的成膜試樣，實施擴大電阻測定，在全部結果中，確認到第1區域506的電阻率低於第2區域508的電阻率。即確認到，第2區域508的導電率小於第1區域506的導電率。另外，藉由X射線繞射測定，而確認到全部的第1區域506及第2區域508為非晶質膜。 In addition, the film formation samples which were formed and formed under the same conditions as those of the first region 506 and the second region 508 of Examples 1 to 5 and Comparative Examples 1 to 3 were subjected to measurement of the expanded resistance. In all the results, it was confirmed that the resistivity of the first region 506 was lower than that of the second region 508. That is, it is confirmed that the conductivity of the second region 508 is smaller than the conductivity of the first region 506. Further, it was confirmed by X-ray diffraction measurement that all of the first region 506 and the second region 508 were amorphous films.

然後，在第2區域508的表面，藉由濺鍍將各尺寸：1 mm×1 mm、電極間距離：0.2 mm的源極電極510、汲極電極512成膜。源極電極510、汲極電極512的成膜藉由使用金屬遮罩的圖案成膜來進行，將Ti成膜10 nm後，將Au成膜50 nm。 Then, on the surface of the second region 508, the source electrode 510 and the drain electrode 512 each having a size of 1 mm × 1 mm and an interelectrode distance of 0.2 mm were formed by sputtering. The formation of the source electrode 510 and the drain electrode 512 was performed by forming a film using a pattern of a metal mask. After Ti was formed into a film of 10 nm, Au was formed into a film of 50 nm.

在電極層形成後，藉由可控制氣體環境的電爐，以350℃保持1小時，在大氣壓(Ar：O2=4：1)氣體環境下進行熱處理步驟。 After the formation of the electrode layer, the heat treatment step was carried out at 350 ° C for 1 hour in an electric furnace capable of controlling the gas atmosphere, under an atmosphere of atmospheric pressure (Ar: O 2 = 4: 1).

根據以上所述，獲得實施例1~實施例5及比較例1~比較例3的底部閘極型且頂部接觸型的TFT 500。 From the above, the bottom gate type and top contact type TFTs 500 of Examples 1 to 5 and Comparative Examples 1 to 3 were obtained.

-評價- -Evaluation-

對所製作的各TFT 500，使用半導體參數分析儀4156C(安捷倫科技(Agilent Technologies)公司製造)，進行電晶體特性(Vg-Id特性)及遷移率μ的測定。Vg-Id特性的測定是藉由以下方式進行：將汲極電壓(Vd)固定為10 V，在-30 V~+30 V的範圍內掃描閘極電壓(Vg)，並測定各閘極電壓(Vg)中的汲極電流(Id)。另外，遷移率是根據線形區域的Vg-Id特性算出線形遷移率而進行記錄，該線形區域的Vg-Id特性是在將汲極電壓(Vd)固定為1 V的狀態下，在-30 V~+30 V的範圍內掃描閘極電壓(Vg)而得。 For each of the TFTs 500 to be fabricated, a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies, Inc.) was used to measure the transistor characteristics (Vg-Id characteristics) and the mobility μ. The Vg-Id characteristic is measured by fixing the gate voltage (Vd) to 10 V, scanning the gate voltage (Vg) in the range of -30 V to +30 V, and measuring the gate voltages. The drain current (Id) in (Vg). Further, the mobility is recorded by calculating the linear mobility based on the Vg-Id characteristic of the linear region, and the Vg-Id characteristic of the linear region is -30 V at a state where the gate voltage (Vd) is fixed to 1 V. Scan gate voltage (Vg) in the range of ~+30 V.

另外，藉由對所製作的各TFT 500照射波長可變的單色(monochrome)光，而評價對於光照射的TFT特性的穩定性。 Further, the stability of the TFT characteristics for light irradiation was evaluated by irradiating each of the produced TFTs 500 with monochromatic light having a variable wavelength.

在該穩定性的評價中，在探針平台上放置各TFT 500，將乾燥大氣流通2小時以上後，在該乾燥大氣氣體環境下測定TFT特性。將單色光源的照射強度設為10 μW/cm2、將波長λ的範圍設為360 nm~700 nm，將單色光未照射時的Vg-Id特性、與單色光照射時的Vg-Id特性進行比較，藉此評價光照射穩定性(△Vth)。單色光照射下的TFT特性的測定是固定為Vd=10 V，在Vg=-15 V ~15 V的範圍內掃描閘極電壓而進行。另外，以下除了特別提及的情況外，全部的測定是在將單色光照射10分鐘後進行。將相對於420 nm的光照射的臨限值位移量△Vth作為TFT 500的光穩定性的指標。 In the evaluation of the stability, each TFT 500 was placed on the probe stage, and the dry atmosphere was allowed to flow for 2 hours or more, and then the TFT characteristics were measured in the dry atmosphere atmosphere. The irradiation intensity of the monochromatic light source is set to 10 μW/cm 2 , the range of the wavelength λ is set to 360 nm to 700 nm, and the Vg-Id characteristic when the monochromatic light is not irradiated and the Vg- when the monochromatic light is irradiated The Id characteristics were compared to evaluate the light irradiation stability (?Vth). The measurement of the TFT characteristics under monochromatic light irradiation was performed by fixing Vd = 10 V and scanning the gate voltage in the range of Vg = -15 V to 15 V. In addition, all the measurements were performed after irradiating monochromatic light for 10 minutes, except for the case specifically mentioned below. The threshold displacement amount ΔVth of the light irradiation with respect to 420 nm is used as an index of the light stability of the TFT 500.

將單色光照射時的Vg-Id特性的測定結果中代表性的Vg-Id特性，表示於圖9及圖10。圖9的Vg-Id特性是比較例1的TFT者，圖10的Vg-Id特性是實施例3的TFT者。另外，圖11是表示代表性的比較例1的TFT與實施例3的TFT中，光照射波長與△Vth的關係的圖表。 Typical Vg-Id characteristics in the measurement results of the Vg-Id characteristics when the monochromatic light is irradiated are shown in FIGS. 9 and 10. The Vg-Id characteristic of FIG. 9 is the TFT of Comparative Example 1, and the Vg-Id characteristic of FIG. 10 is the TFT of Embodiment 3. In addition, FIG. 11 is a graph showing the relationship between the light irradiation wavelength and ΔVth in the TFT of Comparative Example 1 and the TFT of Example 3.

如圖9及圖10所示般可知，照射波長變得越短，則Vg-Id特性越向負側位移。並且，如圖11所示般可知，照射波長變得越短波，則臨限值位移越大。 As shown in FIG. 9 and FIG. 10, the shorter the irradiation wavelength is, the more the Vg-Id characteristic shifts to the negative side. Further, as shown in FIG. 11, it is understood that as the irradiation wavelength becomes shorter, the threshold displacement is larger.

另外，以下的表1中匯總了：調變第2成膜步驟時的成膜壓力後的遷移率、及根據單色光照射前後的I-V特性求出的臨限值位移量△Vth(波長為420 nm時)的測定結果。另外，圖12表示根據表1繪製了成膜壓力與臨限值位移量△Vth(波長為420 nm時)的關係的圖表。 In addition, Table 1 below summarizes the mobility after the film formation pressure in the second film formation step, and the threshold displacement amount ΔVth (the wavelength is obtained from the IV characteristics before and after the monochromatic light irradiation). The measurement result at 420 nm). In addition, FIG. 12 is a graph showing the relationship between the film formation pressure and the threshold displacement amount ΔVth (when the wavelength is 420 nm), according to Table 1.

如表1及圖12所示，第2成膜步驟的第2區域508的成膜壓力未滿2.0 Pa或超過13.0 Pa的比較例1~3的TFT中，相對於波長420 nm的光照射的臨限值位移量的絕對值|△Vth |超過2 V，但是，第2區域508的成膜壓力為2.0 Pa以上、13.0 Pa以下的實施例1~實施例5的TFT中，相對於光照射的臨限值位移量的絕對值|△Vth |為2 V以下。 As shown in Table 1 and FIG. 12, in the TFTs of Comparative Examples 1 to 3 in which the film formation pressure of the second region 508 in the second film formation step was less than 2.0 Pa or more than 13.0 Pa, the light was irradiated with respect to the light having a wavelength of 420 nm. In the TFTs of Examples 1 to 5 in which the film formation pressure of the second region 508 is 2.0 Pa or more and 13.0 Pa or less, the absolute value of the threshold amount of displacement is ΔVth | The absolute value of the temporary displacement amount |ΔVth | is 2 V or less.

另外，實施例1~實施例5的TFT及比較例1~比較例3的TFT中，遷移率均為超過20 cm2/Vs的高的值。 Further, in the TFTs of Examples 1 to 5 and the TFTs of Comparative Examples 1 to 3, the mobility was higher than 20 cm 2 /Vs.

因此，可知，上述TFT可同時具有超過20 cm2/Vs的高遷移率、及相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為2 V以下的高光穩定性，因此，較佳為第2成膜步驟中的第2區域508的(至少成膜開始時的)成膜壓力為2.0 Pa以上、13.0 Pa以下。 Therefore, it is understood that the TFT can have a high mobility of more than 20 cm 2 /Vs at the same time and an absolute value of the displacement amount of the threshold value with respect to the light irradiation of 420 nm | ΔVth | is a high light stability of 2 V or less. Therefore, it is preferable that the film formation pressure of the second region 508 in the second film formation step (at least at the start of film formation) is 2.0 Pa or more and 13.0 Pa or less.

另外，為2.0 Pa以上時臨限值位移量良好的原因認為，一邊對第1區域18A抑制電漿損傷，一邊緩慢地將第2區域18B成膜。 另一方面，超過13.0 Pa時臨限值位移量不良的原因認為，因成膜速率明顯降低引起的各元素的結合狀態的變化。 In addition, when it is 2.0 Pa or more, it is considered that the displacement of the threshold value is good, and the second region 18B is slowly formed while suppressing the plasma damage to the first region 18A. On the other hand, when the amount exceeds 13.0 Pa, the reason why the displacement amount is poor is considered to be a change in the bonding state of each element due to a significant decrease in the film formation rate.

另外，如圖12所示般，若第2成膜步驟中的第2區域508的成膜壓力為5.0 Pa以上且未滿12.0 Pa，則相對於波長420 nm的光照射而臨限值位移量的絕對值|△Vth |為1 V以下。因此，可知，較佳為第2區域508的(至少成膜開始時的)成膜壓力為5.0 Pa以上且未滿12.0 Pa。另外，亦確認到，若將成膜壓力調整為5.0 Pa以上，則可緩和相對於波長420 nm的光照射的臨限值位移量的成膜壓力依存性。即，若成膜壓力為5.0 Pa以上，則即便成膜壓力暫時變動，亦可抑制臨限值位移量的變動。 In addition, as shown in FIG. 12, when the film formation pressure of the second region 508 in the second film formation step is 5.0 Pa or more and less than 12.0 Pa, the amount of displacement is limited with respect to light irradiation at a wavelength of 420 nm. The absolute value of |ΔVth | is 1 V or less. Therefore, it is understood that the film formation pressure of the second region 508 (at least at the start of film formation) is preferably 5.0 Pa or more and less than 12.0 Pa. In addition, it has been confirmed that when the film formation pressure is adjusted to 5.0 Pa or more, the film formation pressure dependency with respect to the threshold displacement amount of the light irradiation at a wavelength of 420 nm can be alleviated. In other words, when the film formation pressure is 5.0 Pa or more, even if the film formation pressure temporarily changes, the fluctuation of the threshold displacement amount can be suppressed.

進而，亦確認到，如圖12所示般，若將第2成膜步驟中的成膜壓力調整為10.0 Pa以下，則即便成膜壓力在成膜壓力為10.0 Pa以下的範圍內暫時變動，亦可抑制臨限值位移量的變動。因此，可知，較佳為第2區域508的(至少成膜開始時的)成膜壓力為10.0 Pa以下。 In addition, as shown in FIG. 12, when the film formation pressure in the second film formation step is adjusted to 10.0 Pa or less, the film formation pressure temporarily changes within a range of the film formation pressure of 10.0 Pa or less. It is also possible to suppress fluctuations in the amount of displacement of the threshold. Therefore, it is understood that the film formation pressure of the second region 508 (at least at the start of film formation) is preferably 10.0 Pa or less.

<對於TFT特性的第1區域的組成依存性> <Conditional dependence on the first region of the TFT characteristics>

-實施例6~實施例8的TFT的製作- - Production of TFTs of Examples 6 to 8 -

接著，關於對於TFT特性的第1區域的組成依存性，藉由製作如以下的實施例6~實施例8的底部閘極型且頂部接觸型的TFT而驗證。另外，實施例6~實施例8的TFT中，除了以下所說明的製作條件外，使用與上述實施例1的TFT的製作條件相同的條件。 Next, the composition dependence of the first region of the TFT characteristics was verified by fabricating the bottom gate type and top contact type TFTs of Examples 6 to 8 below. Further, in the TFTs of Examples 6 to 8, the same conditions as those of the TFT of the above-described Example 1 were used except for the production conditions described below.

首先，在實施例6~實施例8的TFT中，使第1區域506的成膜條件如以下的表2所述。 First, in the TFTs of Examples 6 to 8, the film formation conditions of the first region 506 were as described in Table 2 below.

另外，第2區域506的成膜壓力固定為10.0 Pa。 Further, the film formation pressure of the second region 506 is fixed to 10.0 Pa.

根據以上所述，獲得實施例6~實施例8的底部閘極型且頂部接觸型的TFT。 According to the above, the bottom gate type and top contact type TFTs of Examples 6 to 8 were obtained.

-評價- -Evaluation-

使用上述的評價方法，求出實施例6~實施例8的TFT的遷移率、及相對於波長420 nm的光照射的臨限值位移量△Vth，將結果表示於以下的表3。 The mobility of the TFTs of Examples 6 to 8 and the threshold displacement amount ΔVth of the light irradiation with respect to the wavelength of 420 nm were obtained by the above-described evaluation methods, and the results are shown in Table 3 below.

如表3所示般可知，即便改變第1區域506的組成條件，遷移率與臨限值位移量△Vth亦良好。另外，可知，若如實施例6與實施例7般第1區域506含有In與Zn，則與如實施例8般第1區域506含有In與Sn的情形相比，可顯著地抑制相對於波長420 nm的光照射的臨限值位移量。 As shown in Table 3, even if the composition conditions of the first region 506 were changed, the mobility and the threshold displacement amount ΔVth were also good. In addition, when the first region 506 contains In and Zn as in the sixth embodiment and the seventh embodiment, it is understood that the first region 506 contains In and Sn as compared with the case of the first embodiment. The amount of displacement of the 420 nm light exposure.

<對於TFT特性的第1區域的熱處理溫度依存性> <The heat treatment temperature dependence of the first region of the TFT characteristics>

接著，研究對於TFT特性的第1區域506的熱處理溫度依存 性。 Next, the heat treatment temperature dependence of the first region 506 of the TFT characteristics was investigated. Sex.

實施例6~實施例8的TFT中，將熱處理前的TFT不以350℃進行熱處理，而以300℃、450℃進行熱處理。 In the TFTs of Examples 6 to 8, the TFT before the heat treatment was not heat-treated at 350 ° C, but was heat-treated at 300 ° C and 450 ° C.

使用上述的評價方法，對實施例6~實施例8的TFT，求出以300℃、350℃(與表3的值相同)、450℃進行熱處理時的遷移率、及相對於波長420 nm的光照射的臨限值位移量△Vth，將結果表示於以下的表4。 The TFTs of Examples 6 to 8 were subjected to the above-described evaluation methods to obtain a mobility at 300 ° C, 350 ° C (the same as the value of Table 3), heat treatment at 450 ° C, and a wavelength of 420 nm. The threshold displacement amount ΔVth of the light irradiation is shown in Table 4 below.

如表4所示般可知，除了使用ITO的情況以外，即便改變熱處理溫度，遷移率與臨限值位移量△Vth亦良好。使用ITO時，在未滿450℃的熱處理中，遷移率與臨限值位移量△Vth良好，但若以450℃進行熱處理，則TFT並未正常運作，無法求出遷移率與臨限值位移量△Vth。據此，亦可知，在將本實施例的TFT進行熱處理時，較佳為含有In與Zn。另外，亦可知，若熱處理溫度為300℃以上且未滿450℃，則TFT並不依存於第1區域506的組成而可靠地運作。 As shown in Table 4, in addition to the case of using ITO, even if the heat treatment temperature was changed, the mobility and the threshold displacement amount ΔVth were also good. When ITO is used, the mobility and the threshold displacement amount ΔVth are good in the heat treatment at less than 450 ° C. However, if the heat treatment is performed at 450 ° C, the TFT does not operate normally, and the mobility and the threshold shift cannot be obtained. The amount ΔVth. Accordingly, it is also known that when the TFT of the present embodiment is subjected to heat treatment, it is preferable to contain In and Zn. Further, it is also known that when the heat treatment temperature is 300 ° C or more and less than 450 ° C, the TFT does not depend on the composition of the first region 506 and reliably operates.

另外，在上述各實施例及比較例中，在第2成膜步驟後進行熱處理步驟，但在未進行熱處理步驟時，亦確認到可獲得同 樣的成膜壓力與遷移率及臨限值位移量的關係。 Further, in each of the above examples and comparative examples, the heat treatment step was performed after the second film formation step, but when the heat treatment step was not performed, it was confirmed that the same was obtained. The relationship between the film formation pressure and the mobility and the amount of displacement.

日本專利申請案2012-110605的揭示是藉由參照而併入本說明書中。 The disclosure of Japanese Patent Application No. 2012-110605 is incorporated herein by reference.

關於本說明書所記載的全部文獻、專利申請案、及技術標準，藉由參照併入各文獻、專利申請案、及技術標準，是與具體且分別記載的情形同等程度地，藉由參照而併入本說明書中。 All the documents, patent applications, and technical standards described in the present specification are incorporated by reference to the respective documents, patent applications, and technical standards, to the extent that they are specifically and separately described, Into this manual.

10‧‧‧場效電晶體 10‧‧‧ Field Effect Crystal

12‧‧‧基板 12‧‧‧Substrate

14‧‧‧閘極電極 14‧‧‧ gate electrode

16‧‧‧閘極絕緣膜 16‧‧‧Gate insulation film

18‧‧‧氧化物半導體層 18‧‧‧Oxide semiconductor layer

18A‧‧‧第1區域 18A‧‧‧1st area

18B‧‧‧第2區域 18B‧‧‧2nd area

20‧‧‧源極電極 20‧‧‧Source electrode

22‧‧‧汲極電極 22‧‧‧汲electrode

Claims (13)

一種場效電晶體的製造方法，其是包括形成閘極電極、閘極絕緣膜、氧化物半導體層、源極電極、與汲極電極的底部閘極型的場效電晶體的製造方法，其特徵在於，作為上述氧化物半導體層的形成步驟，包括依序進行：第1成膜步驟，將包含選自於由銦、鎵、鋅、鎂、鋁、錫、銻、鎘及鍺所組成的群組中的至少一種的第1區域成膜；第2成膜步驟，將包含選自於由銦、鎵、鋅、鎂、鋁、錫、銻、鎘及鍺所組成的群組中的至少一種且導電率小於上述第1區域的第2區域，在上述第1區域的表面藉由濺鍍法成膜，且將上述第2區域的至少成膜開始時的成膜壓力調整為2.0 Pa以上、13.0 Pa以下。 A method of manufacturing a field effect transistor, which is a method of manufacturing a field effect transistor including a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a gate electrode of a gate electrode, which is a method of manufacturing a field effect transistor The step of forming the oxide semiconductor layer includes sequentially performing a first film forming step comprising: consisting of indium, gallium, zinc, magnesium, aluminum, tin, antimony, cadmium, and antimony. Forming a first region of at least one of the groups into a film; and forming a second film forming step comprising at least one selected from the group consisting of indium, gallium, zinc, magnesium, aluminum, tin, antimony, cadmium, and antimony a second region having a conductivity lower than that of the first region, wherein a surface of the first region is formed by a sputtering method, and at least a film formation pressure at the start of film formation of the second region is adjusted to 2.0 Pa or more , 13.0 Pa or less. 如申請專利範圍第1項所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為5.0 Pa以上且未滿12.0 Pa。 The method of producing a field effect transistor according to the first aspect of the invention, wherein the film formation pressure at the start of the film formation is adjusted to 5.0 Pa or more and less than 12.0 Pa in the second film formation step. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為10.0 Pa以下。 In the second film forming step, the film forming pressure at the start of film formation is adjusted to 10.0 Pa or less, in the method of producing a field effect transistor according to the first or second aspect of the invention. 如申請專利範圍第3項所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，將上述成膜開始時的成膜壓力調整為8.0 Pa以下。 The method of producing a field effect transistor according to the third aspect of the invention, wherein the film formation pressure at the start of the film formation is adjusted to 8.0 Pa or less in the second film formation step. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述第2成膜步驟中，在成膜中途將成膜壓力切換為低於上述成膜開始時的成膜壓力的壓力。 The method for producing a field effect transistor according to the first or second aspect of the invention, wherein, in the second film forming step, the film forming pressure is switched to be lower than the film forming start in the film forming process. The pressure of the film formation pressure. 如申請專利範圍第5項所述的場效電晶體的製造方法，其中，藉由上述成膜開始時的成膜壓力將上述第2區域成膜至最初的5 nm的膜厚為止，並藉由未滿1.0 Pa的成膜壓力將上述第2區域的其餘部分成膜。 The method for producing a field effect transistor according to the fifth aspect of the invention, wherein the second region is formed to a film thickness of the first 5 nm by the film formation pressure at the start of the film formation, and The remaining portion of the second region described above was formed into a film by a film forming pressure of less than 1.0 Pa. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，將上述第1區域的膜厚設為10 nm以下，將上述第2區域的膜厚設為上述第1區域的膜厚以上。 The method for producing a field effect transistor according to the first aspect of the invention, wherein the film thickness of the first region is 10 nm or less, and the film thickness of the second region is the same. The film thickness of the 1 region is more than or equal to. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟中，以上述第1區域中含有In與Zn的方式成膜。 The method of producing a field effect transistor according to the first or second aspect of the invention, wherein in the first film formation step, the first region is formed to contain In and Zn. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，以上述第1區域及上述第2區域分別含有銦的方式成膜，且使上述第1區域的銦原子組成比率高於上述第2區域的銦原子組成比率。 The method for producing a field effect transistor according to the first or second aspect of the invention, wherein the first region and the second region are in the first film formation step and the second film formation step The film is formed to contain indium, and the indium atomic composition ratio of the first region is higher than the indium atomic composition ratio of the second region. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，以上述第1區域及上述第2區域分別含有鎵的方式成膜，且使上述第1區域的鎵原子組成比率低於上述第2區域的鎵原子組成比率。 The method for producing a field effect transistor according to the first or second aspect of the invention, wherein the first region and the second region are in the first film formation step and the second film formation step The film is formed by containing gallium, and the gallium atom composition ratio of the first region is lower than the gallium atom composition ratio of the second region. 如申請專利範圍第1項或第2項所述的場效電晶體的製造 方法，其中，在上述第1成膜步驟及上述第2成膜步驟中，使用濺鍍法在成膜室內一邊流通包含氧氣的氣體，一邊將上述第1區域及上述第2區域成膜，且在上述第1成膜步驟中，與在上述第2成膜步驟時所流通的氧氣的流量相比，而流通更少的流量的氧氣。 Manufacture of field effect transistors as described in claim 1 or 2 In the first film forming step and the second film forming step, the first region and the second region are formed by depositing a gas containing oxygen gas in the film forming chamber by a sputtering method, and In the first film forming step, oxygen having a smaller flow rate is supplied than the flow rate of the oxygen gas flowing through the second film forming step. 如申請專利範圍第8項所述的場效電晶體的製造方法，其中，在上述氧化物半導體層的形成步驟中、或上述第2成膜步驟後，具有：以300℃以上、600℃以下進行熱處理的熱處理步驟。 The method for producing a field effect transistor according to the eighth aspect of the invention, wherein the step of forming the oxide semiconductor layer or the step of forming the second film forming step is performed at 300 ° C or more and 600 ° C or less A heat treatment step of performing heat treatment. 如申請專利範圍第1項或第2項所述的場效電晶體的製造方法，其中，在上述氧化物半導體層的形成步驟中、或上述第2成膜步驟後，具有：以300℃以上且未滿450℃進行熱處理的熱處理步驟。 The method for producing a field effect transistor according to the first or second aspect of the invention, wherein, in the step of forming the oxide semiconductor layer or after the second film formation step, the method is: 300 ° C or higher And a heat treatment step of heat treatment at 450 ° C.
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112014005486B4 (en) * 2013-12-02 2024-08-22 Semiconductor Energy Laboratory Co., Ltd. Display device
US9349751B2 (en) 2013-12-12 2016-05-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
TWI545777B (en) * 2014-01-15 2016-08-11 Kobe Steel Ltd Thin film transistor
TW201606861A (en) * 2014-08-06 2016-02-16 中華映管股份有限公司 Fabricating method of thin film transistor
WO2016167277A1 (en) * 2015-04-17 2016-10-20 シャープ株式会社 Imaging panel and x-ray imaging device equipped with same
CN105355661A (en) * 2015-10-10 2016-02-24 无锡盈芯半导体科技有限公司 Thin film transistor and preparation method for semiconductor channel layer of thin film transistor
KR20170126398A (en) * 2016-05-09 2017-11-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and display device including the semiconductor device
TWI684283B (en) * 2017-06-07 2020-02-01 日商日新電機股份有限公司 Manufacturing method of thin film transistor
JP7317282B2 (en) * 2019-07-19 2023-07-31 日新電機株式会社 Method for manufacturing thin film transistor
CN113223927B (en) * 2021-04-16 2023-02-10 西安电子科技大学 Preparation method for realizing p-type doped gallium oxide by utilizing bending stress

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060108636A1 (en) * 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
US20110049508A1 (en) * 2009-09-03 2011-03-03 Hitachi, Ltd. Thin film transistor and method for manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101270172B1 (en) * 2007-08-29 2013-05-31 삼성전자주식회사 Oxide thin film transistor and manufacturing method for the same
JP5345359B2 (en) * 2008-09-18 2013-11-20 富士フイルム株式会社 Thin film field effect transistor and display device using the same
KR102094683B1 (en) * 2008-09-19 2020-03-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device
CN102386236B (en) 2008-10-24 2016-02-10 株式会社半导体能源研究所 Semiconductor device and the method for the manufacture of this semiconductor device
JP2010205798A (en) 2009-02-27 2010-09-16 Japan Science & Technology Agency Method of manufacturing thin-film transistor
JP2011077450A (en) * 2009-10-01 2011-04-14 Fujifilm Corp Thin film transistor and method of manufacturing thin film transistor
KR101768433B1 (en) * 2009-12-18 2017-08-16 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
KR20130099074A (en) * 2010-09-03 2013-09-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Sputtering target and method for manufacturing semiconductor device
JP5626978B2 (en) * 2010-09-08 2014-11-19 富士フイルム株式会社 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND APPARATUS HAVING THE THIN FILM TRANSISTOR

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060108636A1 (en) * 2004-11-10 2006-05-25 Canon Kabushiki Kaisha Amorphous oxide and field effect transistor
US20110049508A1 (en) * 2009-09-03 2011-03-03 Hitachi, Ltd. Thin film transistor and method for manufacturing the same

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