KR20120006338A - Package of image sensor - Google Patents

Package of image sensor Download PDF

Info

Publication number
KR20120006338A
KR20120006338A KR1020100067014A KR20100067014A KR20120006338A KR 20120006338 A KR20120006338 A KR 20120006338A KR 1020100067014 A KR1020100067014 A KR 1020100067014A KR 20100067014 A KR20100067014 A KR 20100067014A KR 20120006338 A KR20120006338 A KR 20120006338A
Authority
KR
South Korea
Prior art keywords
image sensor
external connection
sensor chip
sensor package
package
Prior art date
Application number
KR1020100067014A
Other languages
Korean (ko)
Other versions
KR101195264B1 (en
Inventor
박희진
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100067014A priority Critical patent/KR101195264B1/en
Publication of KR20120006338A publication Critical patent/KR20120006338A/en
Application granted granted Critical
Publication of KR101195264B1 publication Critical patent/KR101195264B1/en

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto

Abstract

PURPOSE: An image sensor package is provided to arrange an insulation dam near a solder ball, thereby securing dielectric isolation between chips adjacent to the solder ball or between the solder balls. CONSTITUTION: One surface of a transparent substrate(200) includes a bond finger and an outer connection terminal. A wiring(210) including a ball land(213) is arranged on the transparent substrate. An image sensor chip(100) comprises an image sensor part and a connection member arranged in the outside of the image sensor part. An insulation dam is arranged on the transparent substrate exposed by the image sensor chip. A dielectric layer(220) is arranged with a thickness shielding a lateral surface of a solder ball(310).

Description

Image sensor package {Package of image sensor}

TECHNICAL FIELD The present invention relates to package technology, and more particularly, to an image sensor package.

As the size of the package gradually decreases, a chip is mounted on a module substrate in a flip chip manner using bumps and connected to a bump through a distribution layer. There is a great demand for a chip scale package that is connected to a board substrate using solder balls. When mounting an image sensor chip such as a CMOS sensor chip using bumps on a module substrate and attaching a solder ball to form a package, the spacing between the image sensor chip and the solder ball is narrow. And a short-circuit may cause a short circuit electrically. When a package configured in a flip chip method is mounted on a board substrate by surface mount technology (SMT) using solder balls, the solder balls are pressed and spread, and the solder ball and the image sensor chip adjacent to each other are electrically shorted. Can cause problems. In addition, a problem may occur that the solder balls and the adjacent solder balls are shorted.

In order to prevent such short circuit between the solder ball and the solder ball or the solder ball and the image sensor chip, a method of designing a wider spacing between the solder ball and the solder ball or the spacing between the solder ball and the chip may be considered, but in this case, the solder ball attachment position may be considered as a package. It has to be moved to the outside of, which leads to the disadvantage that the overall package size becomes large. In addition, since the ball land of the module substrate to which the solder ball is attached or the ball land of the printed circuit board (PCB), which is a board substrate, must be moved to the outside, design freedom in the board design is reduced, resulting in a lack of ball design. Difficulties may arise in arranging land positions. Therefore, even if the spacing between the solder balls and the solder balls or the spacing between the solder balls and the image sensor chip is narrow, there is a need to develop a method that can effectively suppress the electrical short between the solder balls and the image sensor chip when solder packages are mounted on the substrate. have.

The present invention provides an image sensor package capable of effectively suppressing an electrical short between the solder ball and the image sensor chip when mounting the package on a substrate, even if the spacing between the solder ball and the solder ball or the spacing between the solder ball and the image sensor chip is narrow. I would like to.

One aspect of the invention,

Embodiments of the present invention may provide a chip scale package and a manufacturing method for forming an insulation dam around the solder ball to ensure insulation isolation between the solder ball and the adjacent solder ball or the solder ball and the adjacent chip. Even if the spacing between the solder balls and the solder balls or the spacing between the solder balls and the image sensor chip is small, the electrical short between the solder ball and the image sensor chip can be effectively blocked by an insulating dam when solder balls are mounted on the board.

1 to 5 are diagrams illustrating an image sensor package according to a first embodiment of the present invention.
6A and 6B to 11 are diagrams illustrating an image sensor package according to a second embodiment of the present invention.

Embodiments of the present invention provide an image sensor package and a manufacturing method for forming an insulation dam around a solder ball to ensure insulation isolation between the solder ball and the adjacent solder ball or the solder ball and the adjacent image sensor chip.

Referring to FIG. 1, a solder bump 110 is formed as a connection member on a wafer on which an image sensor chip 100 is manufactured. In addition to the solder bumps 110, wires or metal pins may be introduced as connection members. Solder bump 110 forms a seed layer (not shown) for plating on the wafer, forms a photoresist pattern (not shown), and contacts a portion exposed to the photoresist pattern. After electroplating the copper (Cu) layer 112, the solder layer 114 may be formed by plating a solder layer 114 with a tin-silver alloy (SnAg). In this case, the copper layer 112 may be formed to a thickness of 10㎛, the solder layer 114 may be formed to a thickness of 30㎛. Thereafter, the photoresist layer is stripped, and the lower seed layer is removed to form the bump 110. Thereafter, the wafer is diced and separated into individual chips 100. Accordingly, the image sensor chip 100 having the bumps 110 on the surface is prepared.

Referring to FIG. 2, the image sensor chip 100 introduces a transparent substrate to be flip chip bonded into a glass substrate 200. The transparent substrate may be made of silicon, quartz or transparent plastic in addition to the glass substrate. A bump land 211 and a solder ball as a subsequent external connection member may be connected as a bond finger to which the bump 110 of the image sensor chip 100 is connected on the glass substrate 200. A wiring 210 including a ball land 213 as an external speed terminal is formed. The external connection member may be made of metal pins or bumps in addition to the solder balls. The bump lands 211 and the ball lands 213 may be formed by a process of forming a redistribution layer (RDL). The bump lands 211 and the ball lands 213 are formed at positions required for the circuit configuration and are interconnected.

After the bump lands 211 and the ball lands 213 are formed, the dielectric layer 220 covering the bump lands 211 and the ball lands 213 is formed as a first insulating member. The dielectric layer 220 is formed to have a relatively thick thickness so that a part is interposed between the subsequently attached solder ball and the image sensor chip 100 to isolate and laterally block the dielectric layer 220. For example, the dielectric layer 220 may be formed to have a thick thickness that is lower than the height of the solder ball to be attached and higher than the height of the upper surface of the image sensor chip. The dielectric layer 220 may include a photosensitive resin such as a photosensitive dielectric material, for example, a polyimide (PI) -based resin, to enable patterning by exposure. In this case, the dielectric layer 220 may be formed by coating a polyimide resin such as a screen print to open a portion of the glass substrate 200 to which the image sensor chip 100 is attached. When the photosensitive resin layer for the dielectric layer 220 is introduced in the form of a film, the photosensitive resin layer may be exposed and developed in a subsequent process to open a portion of the glass substrate 200 to which the image sensor chip 100 is attached.

Referring to FIG. 3, a bump for via 221 for opening the bump land 211 and a ball for solder ball 223 for opening the ball land 213 are formed through the dielectric layer 220. . A process of selectively exposing a portion of the photosensitive resin layer constituting the dielectric layer 220 is performed, and the exposed portion is removed to form the bump via 221 and the ball via 223. When the dielectric layer 220 is introduced in the form of a film, the image sensor chip 100 may be opened together during the exposure and development.

Referring to FIG. 4, the image sensor chip 100 is flip chip bonded onto the glass substrate 200 such that the bump 110 is connected to the bump land 211 through the bump via 221. At this time, the bonding is performed by a pressing and heating process, and by this heating and pressing process, the portion of the dielectric layer 220 adjacent to the bump land 211 is pressed against the edge of the image sensor chip 100 and the image sensor chip. The edge portion of 100 may be impregnated in the dielectric layer 220. Accordingly, the side surface of the image sensor chip 100 is blocked by the dielectric layer 220 to be isolated from the ball via 223 for the solder ball.

After the flip chip bonding, the solder balls 310 are attached to the ball lands 213 through the ball vias 223. Since the dielectric layer 220 is formed to have a thickness at least shielding the side surface of the solder ball 310, the solder fire 310 is opened but the side surface is covered by the dielectric layer 220 is blocked. Accordingly, the side surface of the image sensor chip 100 and the side surface of the solder ball 310 are blocked by portions of the dielectric layer 220 interposed therebetween, so that the side surface of the solder ball 310 and the image sensor chip 100 are separated. The sides will be isolated. For this isolation, the dielectric layer 220 is formed to a thicker thickness with a lower surface than the height of the solder ball 310 and higher than the surface height of the image sensor chip. As such, the solder balls 310 are attached to form an image sensor chip package at a chip scale.

Referring to FIG. 5, the image sensor chip package is mounted on the board substrate 300 so that the solder balls 310 are aligned with the connection pads 311, pressurized and heated to solder balls 310 and the connection pads 311. Board mounting is implemented. At this time, the solder ball 310 may be spread by pressing and heating to expand laterally, but the portion of the dielectric layer 220 is interposed 225 between the solder ball 310 and the side surface of the image sensor chip 100. The portion of the dielectric layer 220 serves as a barrier or dam 225 that prevents the solder balls 310 from contacting the image sensor chip 100. Since the contact between the image sensor chip 100 and the solder ball 310 is blocked by the dam portion of the dielectric layer 220, current leakage due to the contact can be effectively prevented. Therefore, in order to suppress current leakage due to contact, the design burden of shifting or rearranging the position of the solder ball 310 to the outside can be alleviated, and design freedom can be ensured. In addition, since the portion 225 of the dielectric layer 100 is high around the solder ball 310, the portion of the dielectric layer 100 may act as an insulating dam 225 around the solder ball 310. As a result, the solder balls 310 and the neighboring solder balls 310 can be effectively prevented from being mutually contacted by spreading.

The first embodiment of the present invention as described with reference to FIGS. 1 to 5 may be modified and applied as in the second embodiment described with reference to FIGS. 6A to 11.

6A and 6B, an image sensor chip (100 of FIG. 1) introduces a substrate to be flip chip bonded into a glass substrate 1200. The bump land 1211 as a bond finger to which the bump 110 as a connection member of the image sensor chip 100 is to be connected and the solder ball as a subsequent external connection member to the glass substrate 1200 are connected. A wiring 1210 including a ball land 1213 as a connection terminal is formed. The bump lands 1211 and the ball lands 1213 may be formed by forming a redistribution layer (RDL). As illustrated in FIG. 6B, the glass substrate 1200 may include an image sensor chip mounting area including a bond finger and an image sensor chip, and an external connection area including an external connection terminal. As illustrated in FIG. 6B, the external connection region may have a rectangular frame shape surrounding the image sensor chip mounting region, or may have a shape defined only at both sides of the image sensor chip mounting region.

After the bump lands 1211 and the ball lands 1213 are formed, a dielectric layer 1220 as a first insulating member covering the bump lands 1211 and 1213 is formed. The dielectric layer 1220 may be formed of a photosensitive resin such as a photosensitive dielectric material, for example, a polyimide (PI) -based resin, to enable patterning by exposure. In this case, the dielectric layer 1220 may be formed by coating a polyimide resin such as a screen print to open the glass substrate portion 1201 to which the image sensor chip 100 is attached. When the photosensitive resin layer for the dielectric layer 1220 is introduced in the form of a film, it may be exposed and developed in a subsequent process to open the glass substrate portion 1201 to which the image sensor chip 100 is attached. Unlike the first embodiment, the second embodiment of the present invention forms a thinner dielectric layer 1220. Accordingly, the dielectric layer 1220 is formed to be lower than at most 1/2 the height of the solder ball (310 of FIG. 4) to be subsequently attached. Accordingly, the outermost protruding side portion of the solder ball 310, for example, a half height portion, is positioned and exposed on the dielectric layer 1220. In the case where the thickness of the dielectric layer 1220 cannot be made thick, the second embodiment of the present invention can be applied.

Referring to FIG. 7, a via for bump 1221 opening the bump land 1211 through the dielectric layer 1220 and a first via for opening the ball land 1213 may be formed. Form. A process of selectively exposing a portion of the photosensitive resin layer constituting the dielectric layer 1220 is performed, and the exposed portion is removed to form the bump via 1221 and the first ball via 1223. When the dielectric layer 1220 is introduced in the form of a film, the image sensor chip 100 may be opened together during the exposure and development process. This exposure process may be performed to form the bump via 1221 and the first ball via 1223 in a more sophisticated pattern due to the relatively thin thickness of the dielectric layer 1220. Accordingly, bumps (110 of FIG. 1) are formed to have finer sizes, and solder balls 310 of finer sizes are introduced, and finer bump vias 1221 and first ball vias 1223 may be required. In this case, the second embodiment of the present invention can be effectively applied.

Referring to FIG. 8, the glass substrate portion 1201 to which the image sensor chip 100 is to be bonded is opened by opening a second ball via 1233 aligned with the first ball via 1223 on the dielectric layer 1220. An insulating dam 1230 that opens an adjacent portion of the bump land 1211 is formed as a second insulating member. The dam 1230 may be formed of an insulating material, and it is simpler than the process to be formed by a screen print method, rather than performing the layer coating, exposure, and developing processes. For example, an insulating resin layer, such as epoxy resin, is screen printed as shown in FIG. 9 to form dam 1230. At this time, the thickness of the dam 1230 is formed so that the height of the upper surface of the dam 1230 is lower than the height (height) of the solder ball to be subsequently attached and maintained higher than 1/2 the height of the solder ball.

Referring to FIG. 10, the image sensor chip 100 is flip chip bonded onto the glass substrate 1200 such that the bump 110 is connected to the bump land 1211 through the bump via 1221. In this case, the bonding may be performed by pressing and heating. The edge portion of the image sensor chip 100 may be flip chip bonded to be mounted on the dielectric layer 1220. The side surface of the image sensor chip 100 is shielded off by the side surface of the insulating dam 120.

After the flip chip bonding, the solder balls 1310 are attached to the ball lands 1213 through the first ball vias 1223 and the second ball vias 1233. Since the insulating dam 1230 is formed to have a thickness at least shielding the side surface of the solder ball 1310, the solder fire 1310 is opened, but the side surface is covered by the insulating dam 1230 is blocked. Accordingly, the side surface of the image sensor chip 100 and the side surface of the solder ball 1310 are blocked by an insulating dam 1230 interposed therebetween, so that the side surface of the solder ball 1310 and the image sensor chip 100 are separated. The sides will be isolated. In addition, since the insulating dam 1230 shields and shields the side surface of the solder ball 1310, the solder ball 1310 and another solder ball 1310 neighboring are isolated by the insulating dam 1230 as shown in FIG. 11. For this isolation, the insulation dam 1230 is formed to a thickness having a surface height lower than the height of the solder ball 1310 attached thereto and higher than half the height of the solder ball 1310. In this way, the solder balls 1310 are attached to form the image sensor chip package at the chip scale. Thereafter, the image sensor chip package may be aligned and mounted on the board substrate (300 of FIG. 5). Since the contact between the image sensor chip 100 and the solder ball 1310 is blocked, current leakage or short circuit due to contact and contact leakage or short circuit between the solder ball 1310 can be effectively prevented.

100: image sensor chip, 110: bump
200: glass substrate 213: Borland
220: dielectric layer for insulation dam 1230: insulation dam
310, 1310: solder balls.

Claims (13)

A transparent substrate including a bond finger on one surface and an external connection terminal outside the bond finger;
An image sensor chip including an image sensor unit and a connection member disposed outside the image sensor unit, and bonding the connection member and the bond finger so that the one surface of the image sensor unit and the transparent substrate correspond to each other;
An external connection member mounted on the external connection terminal; And
And an insulation member introduced between the bond finger and the external connection terminal and between the external connection member corresponding to a side surface of the image sensor chip.
The method of claim 1,
The transparent substrate is
An image sensor chip mounting area including the bond finger and the image sensor chip; And
An image sensor package including an external connection area including the external connection terminal.
The method of claim 2,
The external connection area is
An image sensor package having a rectangular frame shape surrounding the image sensor chip mounting area.
The method of claim 2,
The external connection area is
An image sensor package having a shape disposed on both sides of the image sensor chip mounting area.
The method of claim 1,
The transparent substrate is
An image sensor package comprising any one transparent material selected from the group consisting of glass, silicon, quartz and transparent plastics.
The method of claim 1,
The connecting member
An image sensor package comprising any one selected from the group consisting of bumps, wires, and metal pins.
The method of claim 1,
The external connection member
An image sensor package comprising any one selected from the group consisting of solder balls, metal pins and bumps.
The method of claim 1,
The insulating member
Higher than the height of the mounted upper surface of the image sensor chip,
The image sensor package having a height of the surface lower than the height of the external connection member.
The method of claim 1,
The insulation member is an image sensor package including a polyimide-based photosensitive resin layer.
The method of claim 1,
The image sensor package further comprises an additional insulating member surrounding the connection member and the external connection member on the insulating member.
The method of claim 10,
And an insulating dam formed as said additional insulating member and said insulating member formed on said transparent substrate exposed by said image sensor chip.
The method of claim 11,
The insulating dam is an image sensor package to expose the external connection member.
The method of claim 11,
The insulation dam is an image sensor package including a screen-printed epoxy-based resin.
KR1020100067014A 2010-07-12 2010-07-12 Package of image sensor KR101195264B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100067014A KR101195264B1 (en) 2010-07-12 2010-07-12 Package of image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100067014A KR101195264B1 (en) 2010-07-12 2010-07-12 Package of image sensor

Publications (2)

Publication Number Publication Date
KR20120006338A true KR20120006338A (en) 2012-01-18
KR101195264B1 KR101195264B1 (en) 2012-11-14

Family

ID=45612100

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100067014A KR101195264B1 (en) 2010-07-12 2010-07-12 Package of image sensor

Country Status (1)

Country Link
KR (1) KR101195264B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102341840B1 (en) * 2015-01-14 2021-12-22 엘지이노텍 주식회사 Sensor Package
KR102589281B1 (en) * 2020-06-26 2023-10-16 주식회사 네패스 Semiconductor package

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6548759B1 (en) 2001-06-28 2003-04-15 Amkor Technology, Inc. Pre-drilled image sensor package
JP4160851B2 (en) 2003-03-31 2008-10-08 富士通株式会社 Semiconductor device for fingerprint recognition
US6864116B1 (en) 2003-10-01 2005-03-08 Optopac, Inc. Electronic package of photo-sensing semiconductor devices, and the fabrication and assembly thereof
JP2008219041A (en) 2008-05-12 2008-09-18 Matsushita Electric Ind Co Ltd Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
KR101195264B1 (en) 2012-11-14

Similar Documents

Publication Publication Date Title
US10692918B2 (en) Electronic device package and fabricating method thereof
US7719104B2 (en) Circuit board structure with embedded semiconductor chip and method for fabricating the same
US10475760B2 (en) Semiconductor device
US20120013002A1 (en) Package structure
KR102319407B1 (en) A substrate strip and a method of manufacturing semiconductor packages by using the same
JP2010245455A (en) Substrate and semiconductor device
US9462704B1 (en) Extended landing pad substrate package structure and method
TW201727850A (en) Semiconductor device and manufacturing method thereof
JP7001445B2 (en) Semiconductor devices and their manufacturing methods
KR20130030054A (en) Printed circuit board and method of manufacturing the same
US9066458B2 (en) Fabricating method of circuit board and circuit board
KR101195264B1 (en) Package of image sensor
US8243462B2 (en) Printed wiring board, semiconductor device, and method for manufacturing printed wiring board
KR102509049B1 (en) Fan out package including vertically stacked chips
KR20110028939A (en) Solder ball and semiconductor package
TW201528446A (en) Manufacturing method of wafer-embedding package structure
KR101340348B1 (en) Embedded chip package board using mask pattern and method for manufacturing the same
KR20110013902A (en) Package and manufacturing method thereof
JP3949077B2 (en) Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method
KR20160032524A (en) Printed circuit board and manufacturing method thereof
JP2012256956A (en) Semiconductor device and semiconductor device mounting body
KR101115476B1 (en) Embedded PCB and Manufacturing method of the same
KR20100025436A (en) Flip chip package and method for packaging the same
KR20210071148A (en) Semiconductor package
TWI544846B (en) Package carrier and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20150921

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20160923

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20170925

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee