TW201528446A - Manufacturing method of wafer-embedding package structure - Google Patents

Abstract

There is provided a manufacturing method of wafer-embedding package structure, including: preparing a carrying plate formed a first wiring layer thereon, the first wiring layer has a plurality of first electrical connection pads and second electrical connection pads; the first electrical connection pad flip-chip in contact with at least one wafer; forming a dielectric layer on the carrying plate to cover the wafer and the first wiring layer, the dielectric layer has a first surface and an opposite second surface to connect the carrying plate; forming a conductive through-hole to penetrate the dielectric layer and connect the second electrical connection pad; forming a second wiring layer that electrically connects the conductive through-hole on the second surface of the dielectric layer; and removing the carrying plate. This invention can enhance the yield of wafer in the electrical connection and reliability test.

Description

Method for manufacturing a package structure in which a wafer is embedded

The invention provides a method for manufacturing a package structure, in particular to a method for manufacturing a package structure in which a wafer is embedded.

Due to the popularity of mobile computing devices, more and more electronic devices need to be light and thin, especially the semiconductor components and their packaging structures that play a central role, and the pursuit of smaller and thinner designs is constantly being embedded. The package structure has also evolved.

Referring to FIGS. 1A to 1H, there are shown cross-sectional views of a conventional method of fabricating a package structure in which a wafer is embedded, and each step of the method of fabricating the package structure will be described in detail below with reference to the drawings.

Referring to FIG. 1A, first, a carrier board 10 is provided having a patterned conductive layer 11 thereon. The patterned conductive layer 11 includes a first conductive film 111 and a second conductive film 112, and the carrier board 10 and patterned conductive A first resist layer 12 is formed on the layer 11, wherein the first resist layer 12 has a first resistive opening 12a to expose the first conductive film 111.

Referring to FIG. 1B and FIG. 1C, second, an electrical connection pad 13 is formed on the first conductive film 111 in the first barrier opening 12a by electroplating, and The first resist layer 12 is subsequently removed.

Referring to FIG. 1D, a second resist layer 14 is formed on the carrier 10, the patterned conductive layer 11 and the electrical connection pad 13, wherein the second resist layer 14 has a second resist opening 14a to expose the second Conductive film 112.

Referring to FIG. 1E and FIG. 1F, the conductive via 15 is formed by electroplating on the second conductive film 112 in the second resist opening 14a, and the second resist layer 14 is removed. When the resist layer 14 is not completely removed, the second resist layer 14 is easily left on the electrical connection pad 13.

Referring to FIG. 1G, the wafer 16 is flip-chip mounted on the electrical connection pad 13. In detail, the wafer 16 is used by the solder 162 on the bump 161 on the surface thereof. The soldering method 162 electrically connects the solder 162 to the electrical connection pad 13 to electrically connect the wafer 16 to the electrical connection pad 13. However, if the second resist layer 14 remains on the electrical connection pad 13, the soldering between the solder 162 and the electrical connection pad 13 will cause a problem of non-wetting, thereby causing cold soldering and emptying. The condition of soldering or false soldering and the poor yield reduction of the electrical connection failure of the wafer 16 or the reliability test (such as thermal cycling test and high temperature storage test).

Referring to FIG. 1H , finally, a dielectric layer 17 covering the patterned conductive layer 11 , the electrical connection pads 13 , the conductive vias 15 , the bumps 161 , the solder 162 , and the wafer 16 is formed on the carrier 10 . The electrical layer 17 has an opening 17a to expose the conductive via 15 and remove the carrier 10 after the dielectric layer 17 is formed.

Therefore, how to overcome the conventional method of embedding the package structure of the chip is caused by the fact that the resist material on the electrical connection pad is not completely removed. The problem of diluting the tin, thereby avoiding the failure of the electrical connection of the wafer or the yield reduction of the poor reliability test, is a major issue for those skilled in the art.

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for fabricating a package structure in which a wafer is embedded, comprising: preparing a carrier board on which a first circuit layer is formed, the first circuit layer having a plurality of first An electrical connection pad and a second electrical connection pad; and at least one wafer is flip-chip mounted on the first electrical connection pad; a dielectric layer is formed on the carrier plate to encapsulate the wafer and the first line a layer, and the dielectric layer has a second surface opposite to the first surface of the carrier plate; a plurality of conductive vias extending through the dielectric layer and connected to the second electrical connection pad; a second wiring layer of the conductive via is formed on the second surface of the dielectric layer; and the carrier is removed.

The invention further provides a method for fabricating a package structure embedded with a wafer, comprising: preparing a carrier board on which a first circuit layer is formed, the first circuit layer having a plurality of first electrical connection pads and a second electricity a connection pad; the at least one wafer is attached to the first electrical connection pad in a flip chip manner; and a dielectric layer covering the wafer and the first circuit layer is formed on the carrier plate, so that the dielectric layer has a connection a first surface opposite to the second surface of the carrier; a plurality of vias extending through the dielectric layer and correspondingly exposing the second electrical connection pad; and a pattern having a plurality of patterned resist openings formed on the second surface Forming a resist layer to expose the via hole to the patterned resistive layer opening; integrally forming a conductive via and a second wiring layer, wherein the conductive via is formed in the via and connecting the second electrical connection a pad, and the second circuit layer is formed in the Patterning the barrier layer opening and electrically connecting the conductive via; and removing the carrier and the patterned resist layer.

The method for fabricating a wafer-embedded package of the present invention can be formed by first forming an electrical connection pad on a carrier board and then directly attaching the wafer to the electrical connection pad, thereby avoiding the formation of an electrical connection pad in the prior art. After the resist layer is removed, the resistive layer is left on the electrical connection pad, thereby preventing the problem of non-stick soldering when the wafer and the electrical connection pad are soldered, so as to improve the electrical connection and reliability of the wafer. Yield of sex test.

10, 20‧‧‧ carrier board

11‧‧‧ patterned conductive layer

111‧‧‧First conductive film

112‧‧‧Second conductive film

12‧‧‧First resistance layer

12a‧‧‧First barrier opening

13‧‧‧Electrical connection pads

14‧‧‧Second resistance layer

14a‧‧‧second barrier opening

15, 25‧‧‧ conductive through holes

16, 23‧‧‧ wafer

161, 231‧‧ ‧ bumps

162, 232‧‧‧ solder

17, 24‧‧‧ dielectric layer

17a‧‧‧ Opening

21‧‧‧First line layer

211‧‧‧First electrical connection pad

212‧‧‧Second electrical connection pad

22‧‧‧resist

221‧‧‧Resistance opening

24a‧‧‧ first surface

24b‧‧‧second surface

241‧‧‧through hole

26‧‧‧Second circuit layer

261‧‧‧The third electrical connection pad

27‧‧‧First insulation protection layer

271‧‧‧First insulating protective layer opening

28‧‧‧Second insulation protection layer

281‧‧‧Second insulation protection opening

29‧‧‧Electronic components

291‧‧‧Conductive components

292‧‧‧electrode pads

293‧‧‧welding line

30‧‧‧Package colloid

31‧‧‧ patterned resist

311‧‧‧ patterned barrier opening

32‧‧‧Metal film

1A to 1H are cross-sectional views showing a method of manufacturing a package structure in which a wafer is embedded in the prior art; and FIGS. 2A to 2J are cross-sectional views showing a method of manufacturing a package structure in which a wafer is embedded in the present invention, 2J' 2A" and 2G" are respectively another embodiment of the 2F and 2G drawings; and 3A to 3D are 2A to A cross-sectional view of another embodiment of Fig. 2C.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Please refer to FIG. 2A to FIG. 2J, which are cross-sectional views showing the manufacturing method of the embedded package structure of the present invention, wherein the steps of the method for fabricating the package structure embedded with the wafer will be referred to the respective figures. The details are as follows.

Referring to FIGS. 2A-2C, first, a carrier board 20 having a first circuit layer 21 formed thereon, the first circuit layer 21 having a plurality of first electrical connection pads 211 and a second electrical connection pad 212 .

In detail, as shown in FIG. 2A, a carrier 20 is provided and a resist layer 22 is formed thereon, and the resist layer 22 has a plurality of barrier openings 221 to expose a portion of the surface of the carrier 20. Next, referring to FIG. 2B, a first circuit layer 21 is formed on the carrier 20 in the barrier opening 221, and the first circuit layer 21 has a plurality of first electrical connection pads 211 and second electrical connection pads 212. . Next, please refer to FIG. 2C to remove the resist layer 22.

Referring to FIG. 2D, at least one wafer 23 is flip-chip mounted on the first electrical connection pad 211. In detail, the surface of the wafer 23 has a bump 231, but the invention is not limited thereto. The solder 232 is provided on the bump 231. However, the present invention is not limited thereto. The solder 23 can be electrically connected to the first electrical connection pad 211 by reflow, so that the wafer 23 and the first electrical connection pad are connected. 211 electrical connection.

Referring to FIG. 2E, a dielectric layer 24 covering the wafer 23 and the first wiring layer 21 is formed on the carrier 20, and the material of the dielectric layer 24 may be ABF (Ajinomoto Build-up Film), but the present invention does not. To be limited thereto, the dielectric layer 24 has a first surface 24a connecting the carrier 20 and a second surface 24b opposite thereto. In a non-limiting aspect of the invention, the dielectric layer 24 and the carrier sheet 20 may have a layer that is not limited to the release layer.

Referring to FIG. 2F and FIG. 2G, a plurality of through holes 241 are formed through the dielectric layer 24 and expose the second electrical connection pads 212, and after the through holes 241 are formed, in the through holes 241. A plurality of conductive vias 25 are formed through the dielectric layer 24 and connected to the second electrical connection pads 212.

Referring to FIG. 2H, a second circuit layer 26 electrically connecting the conductive vias 25 is formed on the second surface 24b of the dielectric layer 24. The second circuit layer 26 has a plurality of third electrical connection pads. 261.

Referring to FIG. 2I, subsequently, the carrier 20 is removed from the first surface 24a. However, the present invention may also form a first insulation on the second surface 24b of the dielectric layer 24 after forming the second wiring layer 26. The protective layer 27 covers the second circuit layer 26. The material of the first insulating protective layer 27 may be a solder resist material, but the invention is not limited thereto, and the first insulating protective layer 27 has a plurality of first insulating protective layer openings. 271, in order to expose each of the third electrical connection pads 261. Therefore, the present invention can form the first insulating protective layer 27 before or after the carrier sheet 20 is removed. In addition, the second insulation protection layer 28 is formed on the first surface 24a of the dielectric layer 24 to cover the first circuit layer 21, and the material of the second insulation protection layer 28 may be The solder resist material, but the invention is not limited thereto, and the second insulating protective layer 28 has a plurality of second insulating protective layer openings 281 to expose a portion of the first wiring layer 21.

Referring to FIG. 2J, finally, the present invention can form a conductive member 291 electrically connected to the first circuit layer 21 in each of the second insulating protective layer openings 281, and then the electronic component 29 can be electrically connected by reflow soldering. The conductive element 291 is arranged to connect the electronic component 29 to the first electrical connection pad 211, but the invention is not limited thereto, wherein the electronic component 29 can be a wafer or a package junction And, after the electronic component 29 is attached, the encapsulant 30 can be formed on the second insulating protective layer 28 to cover the electronic component 29, however, in the case where the second insulating protective layer 28 is not formed (not shown) In this case, the encapsulant 30 is formed on the first surface 24a to encapsulate the electronic component 29. In another aspect of the present invention, the conductive element 291 can be formed on the surface of the electronic component 29. Therefore, the electronic component 29 can be electrically connected to the first line by using the reflow method. The layer 21 is such that the electronic component 29 is attached to the first wiring layer 21. In addition, when the conductive elements 291 electrically connected to the first circuit layer 21 are formed in the second insulating protective layer openings 281, the first insulating protective layer openings 271 may also be electrically connected to the third electrical The connecting pads 261 are, for example, conductive elements of solder balls (not shown).

In addition, in another aspect of the present invention, the electronic component 29 can be attached to the second circuit layer 26, the electronic component 29 is connected as described in FIG. 2J, and the encapsulant 30 is coated with the electronic component. 29 and the first insulating protective layer 27 (this case is not shown). In this case, a conductive member such as a solder ball electrically connected to the first wiring layer 21 may be formed in each of the second insulating protective layer openings 281 (not shown).

Please refer to FIG. 2J', which is another embodiment of FIG. 2J, and the difference between this embodiment and FIG. 2J is that the electronic component 29 is electrically connected first by wire bonding in the first embodiment. The circuit layer 21, in particular, has an electrode pad 292 on the surface of the wafer 29, and is electrically connected to the electrode pad 292 and the second electrical connection pad 212 by a bonding wire 293, so that the wafer 29 is electrically connected to the first line. Layer 21.

Furthermore, please refer to the 2F" and 2G" diagrams, which are another embodiment of the 2F and 2G diagrams, and the difference between the present embodiment and the 2F and 2G diagrams is that In this embodiment, the conductive vias 25 and the second wiring layer 26 are integrally formed.

In detail, as shown in FIG. 2F, the embodiment may form a plurality of through dielectric layers 24 after forming the dielectric layer 24 and correspondingly expose the vias 241 of the second electrical connection pads 212, and then form The patterning resist layer 31 having the plurality of patterned resistive openings 311 is formed, and the patterned resistive opening 311 is at least exposed to the vias 241. Alternatively, in this embodiment, the patterning of the plurality of patterned resistive openings 311 may be formed. The resist layer 31 is formed to expose at least a surface of the dielectric layer 24 on which the plurality of vias 241 are to be opened, and then a plurality of vias 241 corresponding to the second electrical connection pads 212 are formed.

Referring to FIG. 2G", the conductive vias 25 and the second wiring layer 26 are integrally formed. In detail, in this embodiment, the conductive vias 25 in the vias 241 and the patterned resist opening 311 can be formed. The second circuit layer 26 is formed at the same time, and the second circuit layer 26 has a plurality of third electrical connection pads 261, and at least one third electrical connection pad 261 is electrically connected to the conductive vias 25. More specifically, the present invention In an embodiment, a seed layer may be formed on the dielectric layer 24 and the exposed second electrical connection pads 212 and the vias 241 (not shown), and then the plating method may be used in the seed crystal. The conductive via 25 and the second wiring layer 26 are integrally formed on the layer, and then the patterned resist layer 31 is removed. Thereafter, the package structure in which the wafer 23 is embedded can be formed as shown in FIGS. 2H to 2J ( Not shown.) Referring to FIGS. 3A to 3D, the drawings are another embodiment of FIGS. 2A to 2C.

In detail, in the method of FIGS. 3A to 3D, first, as depicted in FIG. 3A, a carrier 20 is provided, one surface of which has a metal film 32, and secondly, as depicted in FIG. 3B, A resist layer 22 having a plurality of resistive opening 221 is formed on the metal film 32 for exposing a portion of the metal film 32 to the plurality of resistive openings 221, and then forming a plurality of first holes in the resist opening 221 by electroplating. The first connection layer 21 of the electrical connection pad 211 and the second electrical connection pad 212, after which the resist layer 22 and the metal film 32 covered thereon are removed, and thereafter, as shown in FIG. 2D to FIG. 2J A package structure (not shown) in which the wafer 23 is embedded is formed.

In summary, compared with the prior art, the present invention avoids the prior art in the prior art by forming an electrical connection pad on the carrier board and then directly attaching the wafer to the electrical connection pad. After the resist layer is formed on the pad, the resistive layer is removed, and the resistive layer remains on the electrical connection pad, thereby preventing the problem of non-stick tin generated when the wafer is soldered to the electrical connection pad. Therefore, compared with the previous According to the technology, the invention can greatly reduce the problem of the failure of the electrical connection failure of the wafer and the poor reliability test of the reliability.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

21‧‧‧First line layer

211‧‧‧First electrical connection pad

212‧‧‧Second electrical connection pad

23‧‧‧ wafer

231‧‧‧Bumps

232‧‧‧ solder

24‧‧‧ dielectric layer

24a‧‧‧ first surface

24b‧‧‧second surface

241‧‧‧through hole

25‧‧‧ conductive vias

26‧‧‧Second circuit layer

261‧‧‧The third electrical connection pad

27‧‧‧First insulation protection layer

271‧‧‧First insulating protective layer opening

28‧‧‧Second insulation protection layer

281‧‧‧Second insulation protection opening

Claims (22)

A method for fabricating a package structure with a wafer, comprising: preparing a carrier board on which a first circuit layer is formed, the first circuit layer having a plurality of first electrical connection pads and a second electrical connection pad; Forming at least one wafer on the first electrical connection pad in a flip chip manner; forming a dielectric layer covering the wafer and the first circuit layer on the carrier plate, so that the dielectric layer has a connection to the carrier plate a first surface opposite to the second surface; forming a plurality of conductive vias penetrating the dielectric layer and connecting the second electrical connection pads; forming a conductive connection on the second surface of the dielectric layer a second circuit layer; and removing the carrier board. The method for manufacturing a package structure with a wafer embedded according to claim 1, wherein after forming the second circuit layer, forming a first insulating protective layer on the second surface of the dielectric layer to cover The second circuit layer, wherein the second circuit layer has a plurality of third electrical connection pads, and the first insulation protection layer has a plurality of first insulation protection layer openings to correspondingly expose the third electrical connection pad. The method for manufacturing a package structure with a wafer embedded according to claim 2, further comprising forming a conductive element in each of the openings of the first insulating protective layer. The method for manufacturing a package structure in which a wafer is embedded according to the second aspect of the invention, wherein the material of the first insulating protective layer is a solder resist material. The method for manufacturing a package structure with a wafer embedded as described in claim 1, after the carrier board is removed, the electronic component is connected to the first circuit layer. The method for manufacturing a package structure with a wafer embedded according to claim 5, after the electronic component is connected, forming a package colloid on the first surface of the dielectric layer to encapsulate the electronic component With the first circuit layer. The method of fabricating a package structure with a wafer as described in claim 5, wherein the electronic component is a wafer or a package structure. The method for manufacturing a package structure with a wafer embedded according to claim 1, after removing the carrier plate, forming a second insulating protective layer on the first surface of the dielectric layer, and the The second insulating protective layer has a plurality of second insulating protective layer openings to expose a portion of the first wiring layer. The method for fabricating a package structure with a wafer as described in claim 8 further comprises forming a conductive element in each of the openings of the second insulating protective layer. The method for manufacturing a package structure having a wafer embedded substrate according to claim 8, wherein the material of the second insulating protective layer is a solder resist material. A package structure embedded with a wafer as described in claim 1 The method for forming the dielectric layer is ABF (Ajinomoto Build-up Film). The method for manufacturing a package structure with a wafer embedded according to claim 1, wherein the step of forming the first circuit layer comprises: providing the carrier plate, a surface of the carrier plate having a metal film; Forming a resist layer having a plurality of resistive opening openings on the metal film for partially exposing the metal film to the opening of the plurality of resist layers; forming the first circuit layer by plating in the opening of the resist layer; and removing the resist layer And the metal film it covers. A method for fabricating a package structure with a wafer, comprising: preparing a carrier board on which a first circuit layer is formed, the first circuit layer having a plurality of first electrical connection pads and a second electrical connection pad; Depositing at least one wafer on the first electrical connection pad in a flip chip manner; forming a dielectric layer covering the wafer and the first circuit layer on the carrier plate, so that the dielectric layer has a connection to the carrier plate a second surface opposite to the surface; forming a plurality of through holes penetrating the dielectric layer and correspondingly exposing the second electrical connection pads; and forming a patterned resist layer having a plurality of patterned resist openings on the second surface, The via hole is exposed to the patterned resistive layer opening; the conductive via hole and the second circuit layer are integrally formed, wherein the conductive via is formed in the via hole and connected to the second electrical connection pad, and The second circuit layer is formed in the patterned resistive layer opening and electrically connected to the conductive via; and the carrier board and the patterned resist layer are removed. The method for manufacturing a package structure with a wafer embedded according to claim 13, wherein after forming the patterned resist layer and the via hole, the dielectric layer and the exposed second electrical connection pad are A seed layer is formed on the via hole. The method of fabricating a package structure with a wafer according to claim 14, wherein the conductive via and the second circuit layer are formed by electroplating. The method for manufacturing a package structure with a wafer embedded according to claim 13 , after removing the patterned resist layer, forming a first insulating protective layer on the second surface of the dielectric layer, Covering the second circuit layer, wherein the second circuit layer has a plurality of third electrical connection pads, and the first insulation protection layer has a plurality of first insulation protection layer openings to correspondingly expose the third electrical properties Connection pad. The method for fabricating a package structure with a wafer as described in claim 16 further comprises forming a conductive element in each of the openings of the first insulating protective layer. The method for manufacturing a package structure in which a wafer is embedded according to claim 16, wherein the material of the first insulating protective layer is a solder resist material. The method for manufacturing a package structure with a wafer embedded according to claim 13 is further included in the first circuit layer after the carrier board is removed. Connect the electronic components. The method for manufacturing a package structure with a wafer embedded according to claim 19, after the electronic component is connected, forming a package colloid on the first surface of the dielectric layer to encapsulate the electronic component With the first circuit layer. The method of fabricating a package structure with a wafer as described in claim 20, wherein the electronic component is a wafer or a package structure. The method for manufacturing a package structure with a wafer embedded according to claim 13 , wherein the step of forming the first circuit layer comprises: providing the carrier plate, a surface of the carrier plate having a metal film; Forming a resist layer having a plurality of resistive opening openings on the metal film for partially exposing the metal film to the opening of the resist layer; forming the first circuit layer by plating in the opening of the resist layer; and removing the resist layer and The metal film it covers.