KR102589281B1 - Semiconductor package - Google Patents

Abstract

The technical idea of the present invention is to include a redistribution structure including a wiring pattern and an insulating layer covering the wiring pattern; a chip connection bump connected to the wiring pattern through a first opening of the insulating layer; a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump; and a connection terminal connected to the wiring pattern through the second opening of the insulating layer, wherein the vertical height of the connection terminal measured with respect to the first surface of the redistribution structure is the first height of the redistribution structure. A semiconductor package including a vertical height equal to or greater than the vertical height of the semiconductor chip measured based on the plane is provided.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The technical idea of the present invention relates to a semiconductor package.

In accordance with the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. Accordingly, semiconductor packages are required to have high density input/output terminals while being small in size. Recently, research and development on a semiconductor package with a fan-out structure that forms input/output terminals outside the area where the semiconductor chip is placed and connects the input/output terminal to the semiconductor chip through rewiring has been continuously conducted.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor package.

In order to solve the above-described problem, the technical idea of the present invention is to include a re-wiring structure including a wiring pattern and an insulating layer covering the wiring pattern; a chip connection bump connected to the wiring pattern through a first opening of the insulating layer; a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump; and a connection terminal connected to the wiring pattern through the second opening of the insulating layer, wherein the vertical height of the connection terminal measured with respect to the first surface of the redistribution structure is the first height of the redistribution structure. A semiconductor package including a vertical height equal to or greater than the vertical height of the semiconductor chip measured based on the surface is provided.

In exemplary embodiments, the insulating layer includes polyimide, and the light transmittance of the insulating layer is 90% or more.

In example embodiments, the semiconductor chip is a sensing chip including a sensing unit provided on a surface of the redistribution structure that faces the first surface.

In example embodiments, the method further includes a sidefill material layer extending along a circumference of the semiconductor chip and sealing a space between the semiconductor chip and the first surface of the redistribution structure.

In example embodiments, the method further includes a dam structure disposed on the first side of the redistribution structure, wherein the dam structure faces the sidefill material layer and the first side of the redistribution structure. It is disposed at least one of the center of the lower surface of the chip and the side fill material layer and the connection terminal.

In example embodiments, the method further includes a molding layer covering a side surface of the semiconductor chip and a side surface of the connection terminal, wherein the connection terminal has an upper surface exposed to the outside and on the same plane as the upper surface of the molding layer. and a side wall having a profile extending convexly outward, wherein the connection terminal includes solder.

In example embodiments, the method further includes a transparent substrate disposed on a second side of the redistribution structure opposite to the first side.

In example embodiments, the transparent substrate includes an upper surface facing the redistribution structure and a lower surface opposite to the upper surface, and further includes a lens layer disposed on the lower surface of the transparent substrate.

In exemplary embodiments, the top surface of the transparent substrate, the bottom surface of the wiring pattern, and the bottom surface of the insulating layer are on the same plane.

In example embodiments, the semiconductor chip is a light-emitting chip configured to emit light toward the first side of the redistribution structure, and the semiconductor chip is configured to face the first side of the redistribution structure. a first connection pad provided on the lower surface and electrically connected to the wiring pattern through the chip connection bump; a second connection pad provided on the upper surface of the semiconductor chip opposite to the lower surface of the semiconductor chip and exposed to the outside; a guide pattern provided on a second side of the redistribution structure opposite to the first side; and at least one of a lens structure supported on the guide pattern and a lens layer provided on the second surface of the redistribution structure.

In example embodiments, the semiconductor chip includes a light-emitting chip configured to emit light toward the first side of the redistribution structure, and a lower surface of the semiconductor chip facing the first side of the redistribution structure. a first connection pad provided on and electrically connected to the wiring pattern through the chip connection bump; and a second connection pad provided on the upper surface of the semiconductor chip opposite to the lower surface of the semiconductor chip and exposed to the outside, and provided on the second surface opposite to the first surface of the redistribution structure. guide pattern; It includes at least one of a lens structure and a lens layer on the second surface of the redistribution structure based on the guide pattern.

In example embodiments, the upper surface of the semiconductor chip is positioned lower than the upper surface of the molding layer, and the molding layer includes a step provided near an edge of the upper surface of the semiconductor chip.

In example embodiments, the redistribution structure includes a hollow portion.

In example embodiments, the method further includes a lens structure provided on a second side of the redistribution structure opposite the first side of the redistribution structure, the lens structure comprising: a central area overlapping with and provided with a lens portion; and an outer region contacting and supporting the second surface of the redistribution structure.

In example embodiments, the semiconductor chip is a sensing chip including a sensing unit provided on a second surface opposite to a surface facing the first surface of the redistribution structure, and covering at least a portion of a side surface of the semiconductor chip, It further includes a molding layer filled between the semiconductor chip and the first surface of the redistribution structure.

In example embodiments, a package substrate; at least one lower semiconductor chip on the package substrate; a lower molding layer provided on the package substrate to cover the at least one lower semiconductor chip; and a conductive post extending through the lower molding layer from the lower surface to the upper surface of the lower molding layer, and electrically connected to the wiring pattern of the package substrate, wherein the first surface of the redistribution structure is formed on the lower surface. Facing the molding layer, the connection terminal extends between the conductive post and the wiring pattern of the redistribution structure.

In example embodiments, an external conductive shielding layer covering at least a portion of the surface of the lower molding layer; and an internal conductive shielding layer extending within the lower molding layer.

According to exemplary embodiments of the present invention, a semiconductor chip, for example, an image sensor chip or a light emitting chip, is mounted on the redistribution structure, thereby providing a miniaturized semiconductor package.

1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
2A to 2C are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 1.
3 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
4 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
5 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
6 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
7 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
8 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
9 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 10A to 10C are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 9.
11 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 12A and 12B are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 11.
13 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
14 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 15A to 15D are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 14.
16 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
17 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.
18 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
19 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
Figure 20 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
21 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
Figure 22 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.
23 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
Figure 24 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.
Figure 25 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
26 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
Figure 27 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.
Figure 28 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.
Figure 29 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
Figure 30 is a cross-sectional view showing a semiconductor package according to example embodiments of the present invention.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the exemplary embodiments of the present disclosure may be modified in various other forms, and the scope of the present disclosure should not be construed as being limited to the embodiments described in detail below. It is preferred that the exemplary embodiments of the present disclosure be interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. Identical symbols refer to identical elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative sizes or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and conversely, the second component may be named a first component without departing from the scope of the present disclosure.

The terminology used in this disclosure is only used to describe specific embodiments and is not intended to limit the concept of this disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, expressions such as “comprises” or “has” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features or It should be understood that this does not preclude the presence or addition of numbers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those skilled in the art in the technical field to which the concept of the present disclosure pertains. Additionally, commonly used terms, as defined in dictionaries, should be interpreted to have meanings consistent with what they mean in the context of the relevant technology, and should not be used in an overly formal sense unless explicitly defined herein. It will be understood that this is not to be interpreted.

1 is a cross-sectional view showing a semiconductor package 10 according to exemplary embodiments of the present invention.

Referring to FIG. 1, the semiconductor package 10 may include a transparent substrate 101, a redistribution structure 120, a first semiconductor chip 130, a chip connection bump 150, and a conductive connection terminal 140. You can.

The transparent substrate 101 may be made of a material with high light transmittance. The transparent substrate 101 may include, for example, glass, silicon, ceramic, plastic, polymer, or a combination thereof. For example, the transparent substrate 101 may have a circular shape or a polygonal shape such as a square in plan view. For example, the transparent substrate 101 may be a panel glass original.

The redistribution structure 120 may be disposed on the upper surface of the transparent substrate 101 . The redistribution structure 120 may include a first surface 128 on which the first semiconductor chip 130 is mounted, and a second surface 129 opposite to the first surface 128. The second surface 129 of the redistribution structure 120 may face the upper surface of the transparent substrate 101. Hereinafter, the horizontal direction is defined as a direction parallel to the first surface 128 of the redistribution structure 120 (for example, the It is defined as a direction perpendicular to the first surface 128 (eg, Z direction). In addition, the horizontal width of any member is defined as the length along the horizontal direction (e.g., X direction and/or Y direction), and the vertical height of any member is defined as the length along the vertical direction (e.g., Z direction). It is defined as the length along the length.

The redistribution structure 120 may be a build-up layer formed on the top surface of the transparent substrate 101. The redistribution structure 120 may include a wiring pattern 121 and an insulating layer 123.

The wiring pattern 121 may extend along the top surface of the transparent substrate 101. The wiring pattern 121 may electrically connect the first semiconductor chip 130 and the conductive connection terminal 140. The wiring pattern 121 includes, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), It may include cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or a combination thereof.

The insulating layer 123 may cover the wiring pattern 121 . The insulating layer 123 is disposed on the upper surface of the transparent substrate 101 and may cover the wiring pattern 121. The insulating layer 123 may be formed of, for example, insulating polymer, epoxy, or a combination thereof. In example embodiments, the insulating layer 123 may include polyimide.

In example embodiments, the insulating layer 123 and the wiring pattern 121 may contact the top surface of the transparent substrate 101. In example embodiments, the lower surface of the insulating layer 123 is in contact with the upper surface of the transparent substrate 101, the lower surface of the wiring pattern 121 is in contact with the upper surface of the transparent substrate 101, and the lower surface of the transparent substrate 101 is The upper surfaces may be on the same plane.

In example embodiments, the redistribution structure 120 may include a center area 120R1 and an outer area 120R2. From a two-dimensional perspective, the outer area 120R2 of the redistribution structure 120 may surround the central area 120R1 in a two-dimensional view. An insulating layer 123 with high light transmittance is disposed in the central region 120R1 of the redistribution structure 120, and the wiring pattern 121 may not be disposed. The wiring pattern 121 may be disposed within the outer area 120R2. As the insulating layer 123 is formed on the upper surface of the transparent substrate 101, the transparent substrate 101 and the wiring pattern 121 are protected during the manufacturing process of the semiconductor package 10. Carrier handling in the process can be performed more easily.

The first semiconductor chip 130 may be mounted on the first surface 128 of the redistribution structure 120. The first semiconductor chip 130 may be attached to the first surface 128 of the redistribution structure 120 through the chip connection bump 150. The chip connection bump 150 is disposed on the outer area 120R2 of the redistribution structure 120 and may be connected to the wiring pattern 121 through the first opening OP1 of the insulating layer 123. The lower end of the chip connection bump 150 may be connected to the wiring pattern 121, and the upper end of the chip connection bump 150 may be connected to the connection pad 133 of the first semiconductor chip 130. The chip connection bump 150 may electrically connect the connection pad 133 of the first semiconductor chip 130 and the wiring pattern 121.

In example embodiments, the chip connection bump 150 may protrude from the first surface 128 of the redistribution structure 120 . As the chip connection bump 150 protrudes from the first surface 128 of the redistribution structure 120, the first semiconductor chip 130 is spaced a certain distance away from the first surface 128 of the redistribution structure 120. A space may be formed between the first semiconductor chip 130 and the first surface 128 of the redistribution structure 120.

In example embodiments, the chip connection bump 150 is formed of solder, tin (Sn), silver (Ag), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), and zinc (Zn). ), lead (Pb), and/or alloys thereof.

The conductive connection terminal 140 may be connected to the wiring pattern 121 through the second opening OP2 of the insulating layer 123. The conductive connection terminal 140 may be electrically connected to the connection pad 133 of the first semiconductor chip 130 through the wiring pattern 121 and the chip connection bump 150. The conductive connection terminal 140 may be a portion connected to an external device, such as an external module board on which the semiconductor package 10 is mounted. Electrical signals may be transmitted between an external device and the first semiconductor chip 130 through the conductive connection terminal 140. For example, the conductive connection terminal 140 may include solder.

In example embodiments, the second vertical height H2 of the conductive connection terminal 140 measured with respect to the first side 128 of the redistribution structure 120 is the first side of the redistribution structure 120. It may be equal to or greater than the first vertical height H1 of the first semiconductor chip 130 measured based on 128. That is, the vertical level of the top surface 141 or the top of the conductive connection terminal 140 may be equal to or greater than the vertical level of the top surface of the first semiconductor chip 130.

In example embodiments, the conductive connection terminal 140 may have a generally ball shape. That is, the conductive connection terminal 140 may have a sidewall that is convex outward. The horizontal width of the lower portion of the conductive connection terminal 140 may become smaller as it approaches the first surface 128 of the redistribution structure 120, and the horizontal width of the upper portion of the conductive connection terminal 140 may decrease as the horizontal width of the upper portion of the redistribution structure 120 increases. ) may become smaller as the distance from the first side 128 increases.

In other example embodiments, the conductive connection terminal 140 may have a generally pillar shape. For example, the conductive connection terminal 140 may have a circular pillar shape extending in the vertical direction (eg, Z direction) with a generally uniform horizontal width. For example, the sidewall of the conductive connection terminal 140 may have a profile extending in a generally straight shape.

In example embodiments, the semiconductor package 10 may further include a first side-fill material layer (side-fill portion) 161 extending along the circumference of the first semiconductor chip 130. The first sidefill material layer 161 may have a ring shape continuously extending along the circumference of the first semiconductor chip 130 when viewed from a plan view. The first sidefill material layer 161 may cover at least a portion of the side surface of the first semiconductor chip 130, and may cover the edge of the first semiconductor chip 130 and the first surface 128 of the redistribution structure 120. It can be extended in between. The first sidefill material layer 161 extends continuously along the circumference of the first semiconductor chip 130, between the lower surface of the first semiconductor chip 130 and the first surface 128 of the redistribution structure 120. It can be configured to seal the space in. For example, the first sidefill material layer 161 may include epoxy.

In example embodiments, the first semiconductor chip 130 may be a sensor chip including a sensing unit 135. For example, the first semiconductor chip 130 may include a substrate 131 and a sensing unit 135 provided on the substrate 131. For example, the substrate 131 may be a semiconductor substrate and may include, for example, silicon (Si). The substrate 131 may have an active surface and an inactive surface that are opposite to each other, and in FIG. 1, the active surface of the substrate 131 may face the first surface 128 of the redistribution structure 120. The sensing unit 135 may be provided on the active surface of the substrate 131. The sensing unit 135 may be provided on the lower surface of the first semiconductor chip 130 facing the first surface 128 of the redistribution structure 120. The first semiconductor chip 130 may be mounted on the redistribution structure 120 so that the lower surface of the first semiconductor chip 130 on which the sensing unit 135 is provided faces the redistribution structure 120 . The sensing unit 135 of the first semiconductor chip 130 may overlap the central region 120R1 of the redistribution structure 120.

In example embodiments, the first semiconductor chip 130 may be an image sensor chip configured to convert incident light into an electrical signal. For example, the first semiconductor chip 130 may include a CMOS image sensor. The sensing unit 135 of the first semiconductor chip 130 may include an image sensing area. The sensing unit 135 includes a sensor array, and the sensor array may include a plurality of unit pixels. A plurality of color filters and/or a plurality of micro lenses may be provided on the plurality of unit pixels.

The first semiconductor chip 130 is an image sensor chip and includes a light sensing area where light provided on the lower surface of the first semiconductor chip 130 facing the first surface 128 of the redistribution structure 120 is input. can do. The first semiconductor chip 130 may be configured to receive light through the transparent substrate 101 and the central region 120R1 of the redistribution structure 120.

In exemplary embodiments, the insulating layer 123 may be formed of a material that has a high light transmittance for light input to the sensing unit 135. Since light incident on the first semiconductor chip 130 passes through the insulating layer 123, the insulating layer 123 may be formed to have the optical characteristics of the insulating layer 123. In example embodiments, the insulating layer 123 may be formed of polyimide. In example embodiments, the light transmittance of the insulating layer 123 may be 90% or more. In example embodiments, the refractive index of the insulating layer 123 may be between 1.6 and 1.7.

FIGS. 2A to 2C are cross-sectional views showing a method of manufacturing the semiconductor package 10 of FIG. 1 .

Referring to FIG. 2A, a panel-shaped transparent substrate 101 is prepared, and a redistribution process is performed to form a redistribution structure 120 on the transparent substrate 101. For example, to form the redistribution structure 120, a wiring pattern 121 may be formed on the upper surface of the transparent substrate 101, and an insulating layer 123 covering the wiring pattern 121 may be formed. . The insulating layer 123 may include a first opening (OP1) and a second opening (OP2) exposing the wiring pattern 121.

Referring to FIG. 2B, a conductive connection terminal 140 connected to the wiring pattern 121 is formed through the second opening OP2 of the insulating layer 123. For example, the conductive connection terminal 140 may be formed through a reflow process using solder balls.

Referring to FIG. 2C, the first semiconductor chip 130 is mounted on the redistribution structure 120. The first semiconductor chip 130 may be mounted on the redistribution structure 120 through the chip connection bump 150. The chip connection bump 150 may be connected to the wiring pattern 121 through the first opening OP1 of the insulating layer 123. The first semiconductor chip 130 is mounted on the redistribution structure 120 so that the lower surface where the sensor unit is provided faces the redistribution structure 120 . Additionally, the first semiconductor chip 130 may be mounted on the redistribution structure 120 so that the sensing unit overlaps the central region 120R1 of the redistribution structure 120 in a vertical direction (e.g., Z direction). .

After mounting the first semiconductor chip 130 on the redistribution structure 120, as shown in FIG. 1, a first sidefill material layer 161 is formed along the perimeter of the first semiconductor chip 130. can do. The first side fill material layer 161 may seal the space between the first semiconductor chip 130 and the redistribution structure 120, and may seal the space between the first semiconductor chip 130 and the redistribution structure 120. It can block other substances from penetrating. After forming the first sidefill material layer 161, a sawing process may be performed on the panel-level structure to separate the panel-level structure into individual semiconductor packages.

In some example embodiments, the first semiconductor chip 130 is an image sensor chip and may be formed from a wafer on which image sensor elements are formed. In exemplary embodiments, the first semiconductor chip 130 includes preparing a wafer on which an image sensor element is formed, forming a protective layer on the wafer, cutting the wafer, and forming the wafer into a plurality of dies ( It can be formed through a sawing step of separating with a die, and a step of removing the protective layer.

In example embodiments, the protective layer may be configured to prevent problems caused by electrostatic discharge (ESD) that may occur during processes. In addition, the protective layer can prevent problems of contamination of the sensing area due to foreign substances, such as contamination of the sensor area due to particles generated during the sawing process. Furthermore, the protective layer can prevent physical damage to the wafer and/or die that may occur during wafer transfer, die transfer, etc. In the step of forming the protective layer, the protective layer may be applied on the wafer to cover one side of the wafer on which the sensing unit or sensing array is formed through a semiconductor coating process. In the removal step of the protective layer, the protective layer may be partially or completely removed as needed.

3 to 8 are cross-sectional views showing semiconductor packages 10a, 10b, 10c, 10d, 10e, and 10f, respectively, according to exemplary embodiments of the present invention. Hereinafter, the semiconductor packages 10a, 10b, 10c, 10d, 10e, and 10f shown in FIGS. 3 to 8 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1.

Referring to FIG. 3 , the semiconductor package 10a may further include a passive component 171 mounted on the redistribution structure 120 . The passive component 171 may be laterally spaced from the side of the first semiconductor chip 130 . The passive component 171 may be electrically connected to the wiring pattern 121 through a connection bump.

Referring to FIG. 4 , the semiconductor package 10b may further include an insulating adhesive layer 103 disposed between the transparent substrate 101 and the redistribution structure 120 . The insulating adhesive layer 103 may be formed to cover the upper surface of the transparent substrate 101. The insulating adhesive layer 103 may include a material different from the material constituting the insulating layer 123. The insulating adhesive layer 103 may include, for example, an oxide. In exemplary embodiments, the insulating adhesive layer 103 may be an oxide film formed through oxidation treatment on the upper surface of the transparent substrate 101. The redistribution structure 120 is formed on the insulating adhesive layer 103, and the wiring pattern 121 may be in contact with the insulating adhesive layer 103. Since the redistribution structure 120 is formed on the insulating adhesive layer 103 with high adhesive strength, the structural safety of the redistribution structure 120 can be improved.

Referring to FIG. 5 , the semiconductor package 10c may further include a lens layer 173 disposed on the lower surface of the transparent substrate 101. The lens layer 173 may be configured to limit scattering and dispersion of light as much as possible. For example, the lens layer 173 may include glass, polymer, ceramic, silicon, quartz, or a combination thereof.

Referring to FIG. 6 , the semiconductor package 10d may include a lens layer 173a including a plurality of unit lenses arranged in an array on the lower surface of the transparent substrate 101. The plurality of unit lenses may be arranged in a two-dimensional array on the lower surface of the transparent substrate 101. For example, the lens layer 173a can be formed by processing glass or polymer using a method such as etching. For example, the lens layer 173a can be formed into a desired shape by processing glass or polymer through reactive ion etching (RIE).

Referring to FIG. 7 , the semiconductor package 10e may be substantially the same as the semiconductor package 10 of FIG. 1 with the first sidefill material layer 161 omitted. Similarly, in example embodiments, in the semiconductor packages 10a, 10b, 10c, and 10d shown in FIGS. 3 to 6, the first sidefill material layer 161 may be omitted.

Referring to FIG. 8 , the semiconductor package 10f may further include a molding layer 180 disposed on the first surface 128 of the redistribution structure 120. The molding layer 180 may cover the side and top surfaces of the first semiconductor chip 130 and surround the sidewall of the conductive connection terminal 140. The upper surface 141 of the conductive connection terminal 140 may be exposed to the outside without being covered by the molding layer 180. In example embodiments, the top surface 141 of the conductive connection terminal 140 may be on the same plane as the top surface 181 of the molding layer 180. For example, the molding layer 180 may include an epoxy-based molding resin or a polyimide-based molding resin. For example, the molding layer 180 may be formed of epoxy molding compound (EMC).

9 is a cross-sectional view showing a semiconductor package 10g according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10g shown in FIG. 9 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1.

Referring to FIG. 9, the semiconductor package 10g may not include a transparent substrate (101 in FIG. 1). Additionally, the insulating layer 123 of the redistribution structure 120 may cover even the lower surface of the wiring pattern 121 . In addition, the semiconductor package 10g, similar to the semiconductor package 10f described with reference to FIG. 8, is disposed on the first side 128 of the redistribution structure 120 and forms a side surface of the first semiconductor chip 130. And it may further include a molding layer 180 covering the upper surface and the side walls of the connection terminal 140.

FIGS. 10A to 10C are cross-sectional views showing a method of manufacturing the semiconductor package 10g of FIG. 9. Hereinafter, descriptions that overlap with those described above will be omitted or simplified.

Referring to FIG. 10A, the redistribution structure 120 is formed on the carrier substrate CA, and the first semiconductor chip 130 is mounted on the redistribution structure 120 using the chip connection bump 150. .

After the first semiconductor chip 130 is mounted on the redistribution structure 120, a first side fill material layer 161 is formed along the circumference of the first semiconductor chip 130. The first side fill material layer 161 may be formed to seal the space between the first semiconductor chip 130 and the redistribution structure 120.

After forming the first side fill material layer 161, a conductive connection terminal 140 is formed on the outer area 120R2 of the redistribution structure 120.

Referring to FIG. 10B, a molding material 180m covering the first semiconductor chip 130 and the conductive connection terminal 140 may be formed on the first surface 128 of the redistribution structure 120. Since the space between the first semiconductor chip 130 and the redistribution structure 120 is sealed by the first sidefill material layer 161, the molding material 180m is formed between the first semiconductor chip 130 and the redistribution structure ( 120) Penetration into the space between them may be blocked. Accordingly, the molding material 180m is not formed in the space between the first semiconductor chip 130 and the redistribution structure 120.

Referring to FIG. 10C together with FIG. 10B, a polishing process may be performed from the upper side of the result of FIG. 10B until the conductive connection terminal 140 is exposed. The polishing process may include, for example, a chemical mechanical polishing process and/or back grinding. Through the polishing process, a portion of the molding material 180m and a portion of the conductive connection terminal 140 may be removed. Through the polishing process, the upper surface 181 of the molding layer 180 and the upper surface 141 of the conductive connection terminal 140 may be flattened. After performing the polishing process, the carrier substrate (CA) is removed.

Figure 11 is a cross-sectional view showing a semiconductor package 10h according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10h shown in FIG. 11 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1.

Referring to FIG. 11 , the semiconductor package 10h may include a redistribution structure 120, a first semiconductor chip 130a, a chip connection bump 150, and a molding layer 180a.

The redistribution structure 120 may include a wiring pattern 121, an external pad 125, and an insulating layer 123. The external pad 125 may be exposed to the lower side of the redistribution structure 120 . The external pad 125 may be electrically connected to the first semiconductor chip 130a through the wiring pattern 121 and the chip connection bump 150.

The first semiconductor chip 130a may include a substrate 131, a sensing unit 135 on the substrate 131, and a conductive via 137 extending through the substrate 131. The substrate 131 includes an active surface and an inactive surface that are opposite to each other, and the inactive surface of the substrate 131 may face the redistribution structure 120 . The sensing unit 135 may be provided on the active surface of the substrate 131. The sensing unit 135 may be provided on the top surface of the first semiconductor chip 130a. Although not specifically shown, the sensing unit 135 is connected to the conductive via 137 through a conductive pattern extending on the top surface of the first semiconductor chip 130a, and the conductive via 137 is connected to the chip connection bump 150. can be connected In example embodiments, the first semiconductor chip 130a may further include a cover protection layer 139 formed to cover the sensing unit 135. For example, the cover protective layer 139 may cover and protect a micro lens provided on the sensing unit 135. In example embodiments, the cover protective layer 139 may be a transparent material. In exemplary embodiments, the cover protective layer 139 may be formed of polyimide.

The molding layer 180a may be disposed on the first surface 128 of the redistribution structure 120. The molding layer 180a may cover at least a portion of the side surface of the first semiconductor chip 130a and may surround the side surface of the first semiconductor chip 130a in a planar manner. Additionally, the molding layer 180a may fill the gap between the first semiconductor chip 130a and the redistribution structure 120 and surround the chip connection bump 150.

FIGS. 12A and 12B are cross-sectional views showing a method of manufacturing the semiconductor package 10h of FIG. 11. Hereinafter, descriptions that overlap with those described above will be omitted or simplified.

Referring to FIG. 12A, the redistribution structure 120 is formed on the carrier substrate CA, and the first semiconductor chip 130a is mounted on the redistribution structure 120. The first semiconductor chip 130a may be disposed on the redistribution structure 120 so that the surface where the sensing unit 135 is provided does not face the redistribution structure 120. The chip connection bump 150 connected to the conductive via 137 may be connected to the wiring pattern 121 through an opening in the insulating layer 123.

Referring to FIG. 12B, after mounting the first semiconductor chip 130a on the redistribution structure 120, a molding layer 180a is formed. For example, the molding layer 180a may be formed through an underfill molded process to fill the gap between the first semiconductor chip 130a and the redistribution structure 120.

Figure 13 is a cross-sectional view showing a semiconductor package 10i according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 10i shown in FIG. 13 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1.

Referring to FIG. 13 , the semiconductor package 10i may include a dam structure 169 disposed around the sidefill material layer 161 . The dam structure 169 may limit the formation range of the sidefill material layer 161 by restricting the flow of the material constituting the sidefill material layer 161 during the formation process of the sidefill material layer 161. .

The dam structure 169 is configured to prevent the material constituting the sidefill material layer 161 from penetrating into the sensing unit 135 of the semiconductor chip 130 and the central region 120R1 of the redistribution structure 120. You can. The dam structure 169 may be disposed on the outer area 120R2 of the redistribution structure 120. For example, the dam structure 169 may be disposed between the sidefill material layer 161 and the center of the lower surface of the semiconductor chip 130, or between the sidefill material layer 161 and the chip connection bump 150. . The dam structure 169 may have a ring shape surrounding the sensing unit 135 of the semiconductor chip 130 and the central region 120R1 of the redistribution structure 120 from a plan view. The dam structure 169 may extend from the first surface 128 of the redistribution structure 120 to the lower surface of the semiconductor chip 130. For example, dam structure 169 may include an insulating material.

Additionally, a dam structure may be disposed outside the sidefill material layer 161. For example, between the sidefill material layer 161 and the conductive connection terminal 140, a dam structure configured to block the material constituting the sidefill material layer 161 from flowing to the conductive connection terminal 140 is disposed. It can be. The dam structure may have a ring shape surrounding the sidefill material layer 161 and the semiconductor chip 130 in plan view.

Figure 14 is a cross-sectional view showing a semiconductor package 20 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 20 shown in FIG. 14 will be described, focusing on differences from the semiconductor package 10g described with reference to FIG. 9.

Referring to FIG. 14, the semiconductor package 20 includes a redistribution structure 120, a first semiconductor chip 210, a chip connection bump 150, a conductive connection terminal 140, and a first side fill material layer 161. , and may include a molding layer 180.

The first semiconductor chip 210 may be a light-emitting chip configured to emit light. For example, the first semiconductor chip 210 may include a laser diode, a light emitting diode (LED), and/or a vertical cavity surface emitting laser (VCSEL). there is.

The first semiconductor chip 210 may include a substrate 211 and a light emitting unit 215 provided on the substrate 211. For example, the substrate 211 may be a semiconductor substrate and may include, for example, silicon (Si). The substrate 211 may have an active surface and an inactive surface that are opposite to each other, and in FIG. 14, the active surface of the substrate 211 may face the first surface 128 of the redistribution structure 120. The light emitting unit 215 may be provided on the active surface of the substrate 211. The light emitting unit 215 is provided on the lower surface of the first semiconductor chip 210 facing the redistribution structure 120, and may be configured to emit light toward the redistribution structure 120. The light emitting unit 215 overlaps the central region 120R1 of the redistribution structure 120 in a vertical direction (e.g., Z direction), and the light emitted from the light emitting unit 215 is of the redistribution structure 120. It is possible to proceed to the outside by passing through the central area 120R1.

The first semiconductor chip 210 is a light emitting chip and may include a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer. For example, the first semiconductor layer, the second semiconductor layer, and the active layer may be made of a gallium nitride-based compound semiconductor. For example, the first semiconductor layer may be made of an n-type GaN layer that supplies electrons to the active layer in response to power supply. The second semiconductor layer may be made of a p-type GaN layer that supplies holes to the active layer according to power supply. The active layer can emit light with a predetermined energy by recombination of electrons and holes. The active layer may have a structure in which quantum well layers and quantum barrier layers are alternately stacked at least once.

The first semiconductor chip 210 may include a first connection pad 212 electrically connected to the first semiconductor layer, and a second connection pad 213 electrically connected to the second semiconductor layer. For example, the first connection pad 212 may be a cathode electrode, and the second connection pad 213 may be an anode electrode. Alternatively, the first connection pad 212 may be an anode electrode and the second connection pad 213 may be a cathode electrode.

In example embodiments, the first connection pad 212 and the second connection pad 213 may be located on different surfaces of the first semiconductor chip 210 . For example, the first connection pad 212 may be provided on the lower surface of the first semiconductor chip 210, and the second connection pad 213 may be provided on the upper surface 219 of the first semiconductor chip 210. there is. The first connection pad 212 may be electrically connected to the wiring pattern 121 through the chip connection bump 150 . The second connection pad 213 may be electrically and physically connected to the pad of the external module board when the semiconductor package 20 is mounted on the pad of the external module board. To allow connection between the second connection pad 213 and the pad of the external module substrate, the molding layer 180 is formed not to cover the upper surface 219 of the first semiconductor chip 210, and the first semiconductor chip ( The upper surface 219 of 210) may be exposed. The second connection pad 213 may have a planar shape extending from the lower surface of the first semiconductor chip 210, and may function as a reflector that reflects light toward the lower surface of the first semiconductor chip 210. there is.

In exemplary embodiments, the top surface 219 of the first semiconductor chip 210 is positioned lower than the top surface 181 of the molding layer 180, and the molding layer 180 is located on the top surface 219 of the first semiconductor chip 210. It may include a step provided near the edge of the upper surface 219. The step of the molding layer 180 includes the inner wall of the molding layer 180 extending between the edge of the top surface 219 of the first semiconductor chip 210 and the top surface 181 of the molding layer 180, It may be defined by the top surface 181 of the molding layer 180. In other exemplary embodiments, the molding layer 180 further covers at least a portion of the top surface 219 of the first semiconductor chip 210. It may also be formed. For example, the molding layer 180 may cover a portion of the top surface 219 of the first semiconductor chip 210 and may include an opening that exposes a portion of the top surface of the second connection pad 213. For example, the molding layer 180 may entirely cover the upper surface 219 of the first semiconductor chip 210. In this case, the second connection pad 213 of the first semiconductor chip 210 is connected to the first semiconductor chip 210. It may be connected to the wiring pattern 121 through a connection conductor such as a conductive via provided at 210 .

The semiconductor package 20 may include a guide pattern 220 and a lens structure 230 disposed on the second surface 129 of the redistribution structure 120 .

The guide pattern 220 is disposed on the second surface 129 of the redistribution structure 120 and may be disposed on the outer area 120R2 of the redistribution structure 120. The guide pattern 220 may be configured to support the lens structure 230. For example, the guide pattern 220 may have a rectangular frame shape with a hollow center portion.

The lens structure 230 is fixed on the second surface 129 of the redistribution structure 120 through the guide pattern 220, and may be aligned at a predetermined position by the guide pattern 220. For example, a step portion is provided at the edge of the lens structure 230, and the step portion of the lens structure 230 engages with the guide pattern 220, thereby aligning the lens structure 230 with the guide pattern 220. It can be supported. The guide pattern 220 can improve the placement precision of the lens structure 230 and make it easier to automate the process of placing the lens structure 230.

The lens structure 230 is disposed on the path of light emitted from the first semiconductor chip 210 to improve light efficiency. The lens structure 230 may be provided with a lens portion processed into a lens shape to function as a lens. For example, the lens structure 230 may include a micro-lens array (Micro-Lens Array, MLA).

In some example embodiments, molding layer 180 may be omitted. In this case, the polishing process for the molding material 180m to expose the conductive connection terminal 140, which will be described later with reference to FIG. 15C, may be omitted. As the polishing process is omitted, unlike that shown in FIG. 14, the conductive connection terminal 140 does not include a flattened upper surface, and may have a curved profile up to the top similar to the conductive connection terminal 140 of FIG. 1. there is.

FIGS. 15A to 15D are cross-sectional views showing a method of manufacturing the semiconductor package 20 of FIG. 14. Hereinafter, descriptions that overlap with those described above will be omitted.

Referring to FIG. 15A, the redistribution structure 120 is formed on the carrier substrate CA, and the first semiconductor chip 210 is mounted on the redistribution structure 120. The first semiconductor chip 210 is mounted on the redistribution structure 120 so that the lower surface where the light emitting unit 215 and the first connection pad 212 are provided faces the redistribution structure 120 . The first semiconductor chip 210 is mounted on the redistribution structure 120 through the chip connection bump 150 disposed between the first connection pad 212 and the wiring pattern 121 of the redistribution structure 120. You can. As shown in FIG. 15A, an electrode protective material 281 covering the second connection pad 213 may be disposed on the upper surface 219 of the first semiconductor chip 210. The electrode protective material 281 may entirely cover the upper surface 219 of the first semiconductor chip 210.

After the first semiconductor chip 210 is mounted on the redistribution structure 120, a first sidefill material layer 161 extending along the circumference of the first semiconductor chip 210 is formed.

After forming the first side fill material layer 161, a conductive connection terminal 140 is formed on the wiring pattern 121 exposed through the opening of the insulating layer 123.

Referring to FIG. 15B , a molding material 180m covering the first semiconductor chip 210 and the conductive connection terminal 140 may be formed on the first surface 128 of the redistribution structure 120. Since the space between the first semiconductor chip 210 and the redistribution structure 120 is sealed by the first sidefill material layer 161, the molding material 180m is formed between the first semiconductor chip 210 and the redistribution structure ( 120) Penetration into the space between them can be blocked.

Referring to FIG. 15C together with FIG. 15B, a polishing process may be performed from the upper side of the result of FIG. 15B until the conductive connection terminal 140 and the electrode protection material 281 are exposed. The polishing process may include, for example, a chemical mechanical polishing process and/or back grinding. Through the polishing process, a portion of the molding material 180m and a portion of the conductive connection terminal 140 may be removed. Through the polishing process, the upper surface 181 of the molding layer 180 and the upper surface 141 of the conductive connection terminal 140 may be flattened.

Referring to FIG. 15D together with FIG. 15C, the electrode protection material 281 may be removed to expose the upper surface 219 of the first semiconductor chip 210. For example, the electrode protective material 281 may be removed through a heat treatment process.

In example embodiments, the vertical level of the top surface 219 of the first semiconductor chip 210 exposed as the electrode protection material 281 is removed may be lower than the vertical level of the top surface 181 of the molding layer 180. there is. The difference between the vertical level of the top surface 219 of the first semiconductor chip 210 and the vertical level of the top surface 181 of the molding layer 180 may be substantially equal to the thickness of the electrode protective material 281.

In example embodiments, as the electrode protective material 281 is removed, a portion of the inner wall of the molding layer 180 along with the top surface 219 of the first semiconductor chip 210 may be exposed. A portion of the exposed inner wall of the molding layer 180 and the top surface 219 of the first semiconductor chip 210 may form a space recessed from the top surface 181 of the molding layer 180.

After removing the electrode protective material 281, the carrier substrate (CA) is removed.

After removing the carrier substrate CA, as shown in FIG. 14, a guide pattern 220 is formed on the second surface of the redistribution structure 120, and the lens structure 230 is formed using the guide pattern 220. ) is disposed on the second side 129 of the redistribution structure 120.

16 to 20 are cross-sectional views showing semiconductor packages 20a, 20b, 20c, 20d, and 20e, respectively, according to exemplary embodiments of the present invention. Hereinafter, the semiconductor packages 20a, 20b, 20c, 20d, and 20e shown in FIGS. 16 to 20 will be described, focusing on differences from the semiconductor package 20 described with reference to FIG. 14.

Referring to FIG. 16 , the semiconductor package 20a may further include a lens layer 240 disposed on the second surface 129 of the redistribution structure 120 . The lens layer 240 may be disposed between the second surface 129 of the redistribution structure 120 and the lens structure 230. For example, the lens layer 240 may include glass, polymer, ceramic, silicon, quartz, or a combination thereof. In example embodiments, the lens layer 240 may include a plurality of unit lenses arranged in an array on the second surface 129 of the redistribution structure 120. For example, the plurality of unit lenses may be arranged in a two-dimensional array on the second surface 129 of the redistribution structure 120.

Referring to FIG. 17 , the semiconductor package 20b may further include a lens layer 241 disposed on the first surface 128 of the redistribution structure 120 . The lens layer 241 may be disposed between the first surface 128 of the redistribution structure 120 and the lower surface of the first semiconductor chip 210. For example, the lens layer 241 may include glass, polymer, ceramic, silicon, quartz, or a combination thereof. In example embodiments, the lens layer 241 may include a plurality of unit lenses arranged in an array on the first surface 128 of the redistribution structure 120. For example, the plurality of unit lenses may be arranged in a two-dimensional array on the first surface 128 of the redistribution structure 120.

Referring to FIG. 18, both the first connection pad 212 and the second connection pad 213 of the first semiconductor chip 210a may be provided on the lower surface of the first semiconductor chip 210a. The second connection pad 213 may be electrically connected to the wiring pattern 121 of the redistribution structure 120 through the chip connection bump 150. Additionally, the molding layer 180 may be formed to further cover the top surface 219 of the first semiconductor chip 210a.

Referring to FIG. 19 , the redistribution structure 120a may include a hollow portion 127 . The hollow portion 127 is provided in the central region 120R1 of the redistribution structure 120a and extends from the first surface 128 to the second surface 129 of the redistribution structure 120a. ) may be in a form that penetrates. The hollow part 127 may be located on the path of light emitted from the light emitting part 215. Accordingly, the light emitted from the light emitting unit 215 may proceed to the lens structure 230 through the hollow portion 127 of the insulating layer 123 without passing through the interior of the insulating layer 123.

Referring to FIG. 20 , the semiconductor package 20e may further include a lens structure 230a and a transparent substrate 250 sequentially stacked on the second surface 129 of the redistribution structure 120a.

The redistribution structure 120a may be directly connected to the lens structure 230a. More specifically, the lens structure 230a has a generally flat shape, and has an outer edge corresponding to (or overlapping in the vertical direction (e.g., Z direction)) the outer region 120R2 of the redistribution structure 120a. It may have an area and a center area corresponding to (or overlapping in the vertical direction (eg, Z direction)) the hollow portion 127 formed in the center area 120R1 of the redistribution structure 120a. In the outer area of the lens structure 230a, the upper surface of the lens structure 230a is flat and may contact and support the second surface 129 of the redistribution structure 120a. A lens portion may be formed in the central area of the lens structure 230a. In example embodiments, the redistribution structure 120a may be formed by performing a redistribution process on an outer area of the lens structure 230a.

21 to 25 are cross-sectional views showing semiconductor packages 20g, 20h, 20i, 20j, and 20k, respectively, according to exemplary embodiments of the present invention. Hereinafter, descriptions that overlap with those described above will be omitted.

Referring to FIG. 21, in the semiconductor package 20g, the guide pattern 220 is omitted from the semiconductor package 20 of FIG. 14, and the lens structure 230 is attached to the second surface 129 of the redistribution structure 120. It may be substantially the same or similar to the one to which it is directly attached.

Referring to FIG. 22, in the semiconductor package 20h, the guide pattern 220 is omitted from the semiconductor package 20b of FIG. 17, and the lens structure 230 is attached to the second surface 129 of the redistribution structure 120. It may be substantially the same or similar to the one to which it is directly attached.

Referring to FIG. 23, the semiconductor package 20i may be substantially the same or similar to the semiconductor package 20a of FIG. 16 with the lens structure 230 omitted.

Referring to FIG. 24 , the semiconductor package 20j may be substantially the same as the semiconductor package 20b of FIG. 17 with the guide pattern 220 and the lens structure 230 omitted.

Referring to FIG. 25 , the semiconductor package 20k may include a first semiconductor chip 265, a second semiconductor chip 261, and a passive component 263 mounted on the redistribution structure 120. The first semiconductor chip 265, the second semiconductor chip 261, and the passive component 263 may be electrically connected to each other through the wiring pattern 121 of the redistribution structure 120. The first semiconductor chip 265, the second semiconductor chip 261, and the passive component 263 may be connected to the conductive connection terminal 140 through the wiring pattern 121 of the redistribution structure 120.

In example embodiments, the second semiconductor chip 261 may be a different type of chip than the first semiconductor chip 210. In example embodiments, the first semiconductor chip 210 is a light emitting chip, and the second semiconductor chip 261 is configured to drive a logic chip, a memory chip, and a time-of-flight (ToF) sensor. It may include a configured driver chip, a driver chip configured to drive a light emitting chip, a communication chip, a WIFI module chip, an RFFE (FR front end) chip, etc.

In example embodiments, the first semiconductor chip 265 may be a light emitting chip, and the second semiconductor chip 261 may be an image sensor chip. In example embodiments, the semiconductor package 20k is configured to drive and control the first semiconductor chip 265 and/or the second semiconductor chip 261 and includes a driver chip mounted on the redistribution structure 120. More may be included. The first semiconductor chip 265 and its surrounding components (e.g., redistribution structure 120, first side fill material layer 161, molding layer 180, guide pattern 220, and Any one of the semiconductor packages 20, 20a, 20b, 20c, 20d, 20e, 20g, 20h, 20i, 20j described with reference to FIGS. 14 to 24, together with at least one of the lens structures 230) Substantially the same or similar structures may be formed. The second semiconductor chip 261 and its surrounding components (e.g., redistribution structure 120, first side fill material layer 161, molding layer 180, guide pattern 220, and Any one of the semiconductor packages 10, 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i described with reference to FIGS. 1 to 13, together with at least one of the lens structures 230) Substantially the same or similar structures may be formed.

Figure 26 is a cross-sectional view showing a semiconductor package 30 according to exemplary embodiments of the present invention. Hereinafter, descriptions that overlap with those described above will be omitted.

Referring to FIG. 26 together with FIG. 1 , the semiconductor package 30 may be a semiconductor package in the form of a package on package in which an upper package 303 is mounted on a lower package 301.

The upper package 303 may include an image sensor chip. In FIG. 26 , the upper package 303 is illustrated as corresponding to the semiconductor package 10 described with reference to FIG. 1 . However, in example embodiments, the top package 303 is any one of the semiconductor packages 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, and 10i described with reference to FIGS. 3-13. It may apply to

The semiconductor package 30 may include a second sidefill material layer 410 extending along the perimeter of the redistribution structure 120 of the upper package 303. The second sidefill material layer 410 may have a ring shape continuously extending along the perimeter of the redistribution structure 120 when viewed from a plan view. The second side fill material layer 410 may cover at least a portion of the side surface of the redistribution structure 120 and at least a portion of the side surface of the transparent substrate 101 . The second sidefill material layer 410 may extend between the edge of the redistribution structure 120 and the upper surface of the lower package 301. The second sidefill material layer 410 extends continuously along the circumference of the redistribution structure 120 of the upper package 303 and is configured to seal the space between the redistribution structure 120 and the lower package 301. It can be. For example, the second sidefill material layer 410 may include epoxy.

For example, the lower package 301 may be a semiconductor package in the form of a fan out wafer level package (FOWLP). The lower package 301 may include a package substrate 310, a first lower semiconductor chip 321, a conductive post 325, and a lower molding layer 323.

The package substrate 310 may include an insulating layer 313 and a wiring pattern 311. For example, the package substrate 310 may be a redistribution substrate 131 formed through a redistribution process. For example, the insulating layer 313 may be formed of insulating polymer, epoxy, or a combination thereof. The wiring pattern 311 may be covered with an insulating layer 313.

The first lower semiconductor chip 321 may be mounted on the package substrate 310. For example, the first lower semiconductor chip 321 may be mounted on the package substrate 310 using a flip chip method. For example, the first lower semiconductor chip 321 may be electrically connected to the wiring pattern 311 of the package substrate 310 through the chip connection bump 329.

The first lower semiconductor chip 321 is electrically connected to the first semiconductor chip 130 included in the upper package 303 and may be configured to control the first semiconductor chip 130. For example, the first lower semiconductor chip 321 may include an image signal processor chip configured to control the image sensor chip or process signals generated from the image sensor chip.

In other example embodiments, the lower package 301 may further include an integrated circuit configured to implement Optical Image Stabilizer (OIS) and Auto Focus (AF) functions. Additionally, the lower package 301 may further include a ToF sensor, a ToF driver, etc. However, it is not limited to this, and the lower package 301 further includes logic chips such as a memory chip, a CPU (Central Processor Unit), an MPU (Micro Processor Unit), a GPU (Graphic Processor Unit), and an AP (Application Processor). You may.

The lower molding layer 323 may be provided on the package substrate 310 to cover at least a portion of the first lower semiconductor chip 321. For example, the lower molding layer 323 may cover the sidewall of the first lower semiconductor chip 321 and the upper surface of the first lower semiconductor chip 321. In some example embodiments, the lower molding layer 323 may cover the sidewall of the first lower semiconductor chip 321, but may not cover the top surface of the first lower semiconductor chip 321. Additionally, the lower molding layer 323 is filled between the first lower semiconductor chip 321 and the package substrate 310 and may surround the chip connection bump 329. Additionally, the lower molding layer 323 may surround the sidewall of the conductive post 325. The lower molding layer 323 may be formed of, for example, an epoxy molding compound, but is not limited thereto.

The conductive post 325 may be positioned laterally spaced apart from the sidewall of the first lower semiconductor chip 321 . The conductive post 325 may vertically penetrate the lower molding layer 323. The upper end of the conductive post 325 may be connected to the conductive connection terminal 140 of the upper package 303, and the lower end of the conductive post 325 may be connected to the wiring pattern 311 of the package substrate 310. The first lower semiconductor chip 321 is connected via the wiring pattern 311 of the package substrate 310, the conductive post 325, the conductive connection terminal 140, and the wiring pattern 121 of the redistribution structure 120. It may be electrically connected to the first semiconductor chip 130 through an electrical signal path. 27 to 30 are cross-sectional views showing semiconductor packages 30a, 30b, 30c, and 30d, respectively, according to exemplary embodiments of the present invention. Hereinafter, the semiconductor packages 30a, 30b, 30c, and 30d shown in FIGS. 27 to 30 will be described, focusing on differences from the semiconductor package 30 described with reference to FIG. 26.

Referring to FIG. 27 , the lower package 301 may further include a second lower semiconductor chip 322 mounted on the package substrate 310. The second lower semiconductor chip 322 may be electrically connected to the first semiconductor chip 130 through the wiring pattern 311 of the package substrate 310. The second lower semiconductor chip 322 may be a different type of chip than the first lower semiconductor chip 321. For example, the first lower semiconductor chip 321 may be an image sensor processor chip, and the second lower semiconductor chip 322 may be a logic chip, memory chip, communication chip, WIFI module chip, RFFE (FR front end) chip, etc. may include. Furthermore, in some embodiments, the lower package 301 may further include an antenna structure for wireless communication.

The first semiconductor chip 130 of the upper package 303 may be arranged to overlap the first lower semiconductor chip 321 of the lower package 301 in a plane. In this case, the electrical connection path between the first semiconductor chip 130 and the first lower semiconductor chip 321 becomes smaller, so high-speed signal processing can be implemented.

Additionally, the lower package 301 may further include an external conductive shielding layer 381. The external conductive shielding layer 381 may be configured to prevent electromagnetic interference to electronic components included in the lower package 301. For example, the external conductive shielding layer 381 may extend on the top and side surfaces of the lower molding layer 323 and on the side surfaces of the package substrate 310. The external conductive shielding layer 381 may include a conductive material such as copper (Cu), silver (Ag), or platinum (Pt). For example, the external conductive shielding layer 381 may be formed through a process such as physical vapor deposition, chemical vapor deposition, electroless plating, electrolytic plating, or spraying, but is not limited thereto.

In example embodiments, outer conductive shielding layer 381 may be electrically grounded. For example, a ground voltage may be applied to the external conductive shielding layer 381 through a portion of the wiring pattern 311 of the package substrate 310 that is electrically grounded.

In example embodiments, the lower package 301 may include a first region (R1) and a second region (R2) that are separated from each other in plan view. The first area (R1) is an area where the first semiconductor chip 130 is placed, and the second area (R2) is the remaining area other than the first area (R1) where the second semiconductor chip 261 may be placed. . The upper package 303 may be disposed on the first region R1 of the lower package 301. At this time, the external conductive shielding layer 381 covers the side and top surfaces of a portion of the lower molding layer 323 in the second region R2, and covers the side surface of the package substrate 310 in the second region R2. It can cover at least part of it. The external conductive shielding layer 381 can prevent electromagnetic interference to electronic components such as the second semiconductor chip 261 in the second region R2.

Referring to FIG. 28, the semiconductor package 30b is different from the semiconductor package 30a described with reference to FIG. 27 in that it generally further includes an internal conductive shielding layer 383. The internal conductive shielding layer 383 may be provided within the lower molding layer 323. The internal conductive shielding layer 383 extends in the vertical direction (eg, Z direction) within the lower molding layer 323 and may extend from the lower surface to the upper surface of the lower molding layer 323. In example embodiments, internal conductive shielding layer 383 may be electrically grounded. For example, a ground voltage may be applied to the internal conductive shielding layer 383 through a portion of the wiring pattern 311 of the package substrate 310 that is electrically grounded.

The internal conductive shielding layer 383 is provided at the boundary between the first region R1 and the second region R2 to partition or separate the first region R1 and the second region R2. For example, the internal conductive shielding layer 383 may be disposed between the first semiconductor chip 130 and the second semiconductor chip 261 in the first region R1.

The internal conductive shielding layer 383 may cooperate with the external conductive shielding layer 381 to form a shielding area for shielding electromagnetic interference. For example, the second semiconductor chips 261 in the second region R2 may be surrounded by the inner conductive shielding layer 383 and the outer conductive shielding layer 381 when viewed from a plan view.

Referring to FIG. 29, the semiconductor package 30c includes a lower package 301, a connection structure 350 provided on the lower package 301, an upper package 303 mounted on the connection structure 350, and an upper semiconductor chip. It may include (330). The connection structure 350 may be a build-up layer formed by performing a rewiring process on the lower molding layer 323 of the lower package 301. The connection structure 350 may include a wiring pattern 351 and an insulating layer 353 covering the upper surface of the lower molding layer 323. The wiring pattern 351 of the connection structure 350 may be electrically connected to the wiring pattern 311 of the package substrate 310 through a conductive post 325 . For example, the upper semiconductor chip 330 may include a memory chip, a MEMS gyroscope module, etc.

Referring to FIG. 30, the semiconductor package 30d differs from the semiconductor package 30c described with reference to FIG. 29 in that it further includes an internal ground layer 385. The internal ground layer 385 may extend in the horizontal direction (eg, X direction and/or Y direction) on the first lower semiconductor chip 321 and the second lower semiconductor chip 322. For example, the internal ground layer 385 may extend in a horizontal direction (e.g., in the X direction and/or Y direction) along the top surface of the lower molding layer 323 or within the lower molding layer 323. . For example, the internal ground layer 385 may have a planar shape extending along the upper surface of the lower molding layer 323. The internal ground layer 385 may be electrically grounded. For example, the internal ground layer 385 may be configured to receive a ground voltage through one of the conductive posts 325 provided in the lower molding layer 323. The internal ground layer 385 includes the first lower semiconductor chip 321 and the second lower semiconductor chip 322 included in the lower package 301, the first semiconductor chip 130 disposed on the lower package 301, and It may be configured to block residual wave interference between the upper semiconductor chips 330.

According to exemplary embodiments of the present invention, a semiconductor chip, for example, an image sensor chip or a light emitting chip, is mounted on the redistribution structure, thereby providing a miniaturized semiconductor package.

As above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached claims.

10: semiconductor package 120: rewiring structure
130: first semiconductor chip 140: connection terminal

Claims (16)

A redistribution structure including a wiring pattern and an insulating layer covering the wiring pattern;
a chip connection bump connected to the wiring pattern through a first opening of the insulating layer;
a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump;
a connection terminal connected to the wiring pattern through a second opening of the insulating layer;
package substrate;
at least one lower semiconductor chip on the package substrate;
a lower molding layer provided on the package substrate to cover the at least one lower semiconductor chip; and
a conductive post extending through the lower molding layer from the lower surface to the upper surface of the lower molding layer and electrically connected to wiring of the package substrate;
Including,
The vertical height of the connection terminal measured with respect to the first side of the redistribution structure is equal to or greater than the vertical height of the semiconductor chip measured with respect to the first side of the redistribution structure,
The first side of the redistribution structure faces the lower molding layer,
A semiconductor package wherein the connection terminal extends between the conductive post and the wiring pattern of the redistribution structure. According to claim 1,
A semiconductor package wherein the insulating layer includes polyimide, and the insulating layer has a light transmittance of 90% or more. According to claim 1,
The semiconductor chip is a semiconductor package that is a sensing chip including a sensing unit provided on one surface facing the first surface of the redistribution structure. According to claim 1,
A semiconductor package further comprising a sidefill material layer extending along a circumference of the semiconductor chip and sealing a space between the semiconductor chip and the first surface of the redistribution structure. According to claim 4,
Further comprising a dam structure disposed on the first side of the redistribution structure,
The dam structure is disposed at least one of between the sidefill material layer and the center of the lower surface of the semiconductor chip facing the first surface of the redistribution structure and between the sidefill material layer and the connection terminal. According to claim 1,
Further comprising a molding layer covering a side surface of the semiconductor chip and a side surface of the connection terminal,
The connection terminal is,
an upper surface on the same plane as the upper surface of the molding layer and exposed to the outside; and
a side wall having a profile extending convexly outward;
Including,
The connection terminal is a semiconductor package including solder. The method of claim 1 or 6,
A semiconductor package further comprising a transparent substrate disposed on a second side of the redistribution structure opposite to the first side. According to claim 7,
The transparent substrate includes an upper surface facing the redistribution structure and a lower surface opposing the upper surface,
A semiconductor package further comprising a lens layer disposed on the lower surface of the transparent substrate. According to claim 7,
A semiconductor package wherein the upper surface of the transparent substrate, the lower surface of the wiring pattern, and the lower surface of the insulating layer are on the same plane. A redistribution structure including a wiring pattern and an insulating layer covering the wiring pattern;
a chip connection bump connected to the wiring pattern through a first opening of the insulating layer;
a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump;
a connection terminal connected to the wiring pattern through a second opening of the insulating layer;
a molding layer covering a side surface of the semiconductor chip and a side surface of the connection terminal;
a guide pattern provided on a second side of the redistribution structure opposite to the first side; and
at least one of a lens structure supported on the guide pattern and a lens layer provided on the second surface of the redistribution structure;
Including,
The semiconductor chip is a light emitting chip configured to emit light to the first surface of the redistribution structure,
The semiconductor chip is,
a first connection pad provided on a lower surface of the semiconductor chip facing the first surface of the redistribution structure and electrically connected to the wiring pattern through the chip connection bump; and
a second connection pad provided on the upper surface of the semiconductor chip opposite to the lower surface of the semiconductor chip and exposed to the outside;
A semiconductor package containing a. According to claim 10,
The upper surface of the semiconductor chip is lower than the upper surface of the molding layer,
The molding layer is a semiconductor package including a step provided near an edge of the upper surface of the semiconductor chip. According to claim 1,
The redistribution structure is a semiconductor package including a hollow portion. A redistribution structure including a wiring pattern and an insulating layer covering the wiring pattern;
a chip connection bump connected to the wiring pattern through a first opening of the insulating layer;
a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump;
a connection terminal connected to the wiring pattern through a second opening of the insulating layer; and
a lens structure provided on a second side of the redistribution structure opposite the first side of the redistribution structure;
It includes, and the lens structure includes,
a central area provided with a lens unit; and
an outer area contacting and supporting the second surface of the redistribution structure;
A semiconductor package containing a. A redistribution structure including a wiring pattern and an insulating layer covering the wiring pattern;
a chip connection bump connected to the wiring pattern through a first opening of the insulating layer;
a semiconductor chip mounted on the first surface of the redistribution structure through the chip connection bump; and
a molding layer covering at least a portion of a side surface of the semiconductor chip and filled between the semiconductor chip and the first surface of the redistribution structure;
Including,
The semiconductor chip is,
a substrate including an inactive surface facing the redistribution structure and an active surface opposite the inactive surface;
a sensing unit on the active side of the substrate; and
Conductive vias penetrating the substrate and connected to each of the sensing unit and the chip connection bump;
A semiconductor package containing a. delete According to claim 1,
an external conductive shielding layer covering at least a portion of the surface of the lower molding layer; and
an internal conductive shielding layer extending within the lower molding layer;
A semiconductor package further comprising:

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