KR20110109027A - Flat panel display device and manufacturing method the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat panel display device and a method of manufacturing the flat panel display device capable of inspecting a pressing trace of a conductive ball electrically connected to a pad electrode. ; A conductive layer formed on an upper surface of the lower pad electrode; A protective layer formed to cover the conductive layer; A contact hole formed in a predetermined region of the protective layer; And an upper pad electrode formed in the contact hole to be electrically connected to the conductive layer and electrically connected to the lower pad electrode through the conductive layer.

Description

Flat panel display and manufacturing method thereof {FLAT PANEL DISPLAY DEVICE AND MANUFACTURING METHOD THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display device, and more particularly, to a flat panel display device and a method for manufacturing the same, which can enable inspection of a pressing trace of a conductive ball electrically connected to a pad electrode.

Recently, with the development of various portable electronic devices such as mobile communication terminals, notebook computers, and the like, there is an increasing demand for a flat panel display device that can be applied thereto. Such flat panel displays include liquid crystal display devices, plasma display panels, field emission display devices, and light emitting diode display devices. Although being studied, liquid crystal display devices are in the spotlight due to mass production technology, ease of driving means, and high quality.

Recently, in order to secure low cost, light weight, low power, and high reliability of a liquid crystal display device, a chip on glass type that bonds a plurality of gate driver integrated circuits and a plurality of data driver integrated circuits to a display panel has been developed. Liquid crystal display devices are being developed and mass produced.

1 is a diagram schematically illustrating a pad part of a typical chip on glass type liquid crystal display device.

Referring to FIG. 1, a pad part of a typical chip on glass type liquid crystal display device may include a gate pad part 20 and a data pad part 30 formed on a substrate 10, and a driving signal for driving a liquid crystal display device. The driving integrated circuit 40 generates and supplies the gate pad unit 20 and the data pad unit 30 to the gate pad unit 20.

The gate pad part 20 includes a lower gate pad electrode 21, an insulating layer 23, a protective layer 25, a gate contact hole 27, and an upper gate pad electrode 29.

The lower gate pad electrode 21 is electrically connected to a gate signal line (not shown) to which a gate signal is supplied. In this case, the lower gate pad electrode 21 is electrically connected to the gate signal line through a gate link line (not shown) formed in the substrate 10 to be electrically connected to the gate signal line.

The insulating layer 23 is formed to cover the lower gate pad electrode 21.

The protective layer 25 is formed to cover the insulating layer 23.

The gate contact hole 27 is formed by removing a portion of the protective layer 25, the insulating layer 23, and the lower gate pad electrode 21. In this case, the gate contact hole 27 is formed of the protective layer 25, the insulating layer 23, and the lower gate pad electrode 21 so that a predetermined region of the substrate 10 overlapping the lower gate pad electrode 21 is exposed. It is formed to pass through a predetermined area.

The upper gate pad electrode 29 is formed of a transparent material on the gate contact hole 27 and the protective layer 25 to be electrically connected to the lower gate pad electrode 21. In this case, the upper gate pad electrode 29 is formed on the upper surface of the protective layer 25 and the inner wall of the gate contact hole 27 to be electrically connected to the side surface of the lower gate pad electrode 21.

The data pad unit 20 includes a lower data pad electrode 31, a data contact hole 37, and an upper data pad electrode 39.

The lower data pad electrode 31 is formed on the substrate 10 with the same material as the lower gate pad electrode 21 and electrically connected to a data signal line (not shown) to which a data signal is supplied. In this case, the lower data pad electrode 31 is electrically connected to the data signal line through a gate link line (not shown) formed to be electrically connected to the gate signal line, and the gate link line connects one jumper (not shown). Is electrically connected to the data signal line.

The data contact hole 37 is formed by removing a portion of the protective layer 25, the insulating layer 23, and the lower data pad electrode 31. In this case, the data contact hole 37 of the protective layer 25, the insulating layer 23, and the lower data pad electrode 31 is exposed to expose a predetermined region of the substrate 10 overlapping the lower data pad electrode 31. It is formed to pass through a predetermined area.

The upper data pad electrode 39 is formed of a transparent material on the data contact hole 37 and the protective layer 25 to be electrically connected to the data pad lower electrode 31. In this case, the upper data pad electrode 39 is formed on the upper surface of the protective layer 25 and the inner wall of the data contact hole 37 to be electrically connected to the side surface of the lower data pad electrode 31.

The driving integrated circuit 40 generates a gate signal and supplies the gate signal to the gate signal line, and generates and supplies a data signal synchronized with the gate signal to the data signal line. To this end, the gate terminal (or bump) 42 and the data terminal 44 of the driving integrated circuit 40 may be gated through an anisotropic conductive film (ACF) 50 according to a tape automated bonding (TAB) method. It is electrically connected to each of the pad portion 20 and the data pad portion 30.

In this case, the upper gate pad electrode 29 of the gate pad part 20 is electrically connected to the gate terminal (or bump) 42 of the driving integrated circuit 40 through the conductive ball 52 of the ACF 50. .

In addition, the upper data pad electrode 39 of the data pad part 30 is also electrically connected to the data terminal (or bump) 44 of the driving integrated circuit 40 through the conductive ball 52 of the ACF 50. .

Such a liquid crystal display of a typical chip on glass type has gate and data signals from the driving integrated circuit 40 electrically connected to the pad portions 20 and 30 via the conductive balls 52 of the ACF 50. A predetermined image is displayed in accordance with the gate signal and the data signal supplied to the line.

In the structure of the general pad portion described above, the pad portions 20 and 30 and the terminals 42 and 44 depend on the connection state of the conductive balls 52 electrically connected between the pad electrodes 29 and 39 and the terminals 42 and 44. There is a problem that disconnection may occur in between. In order to check this problem, the connection state of the conductive ball 52 is checked by checking the pressing trace of the conductive ball 52 through a pad image according to the degree of light reflected from the pads 20 and 30 through light irradiation. Done.

However, the liquid crystal display of the conventional chip on glass type has the pad portion 20 described above by the contact holes 27 and 37 formed by removing predetermined regions of the lower gate pad electrode 21 and the lower data pad electrode 31. , 30), there is a problem that the trace of the pressing of the conductive ball 52 can not be confirmed because the pad image of 30) cannot be accurately obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is a technical object of the present invention to provide a flat panel display device and a method of manufacturing the same, which can enable inspection of a pressing trace of a conductive ball electrically connected to a pad electrode.

According to an aspect of the present invention, there is provided a flat panel display device including: a lower pad electrode connected to a signal line of a display panel; A conductive layer formed on an upper surface of the lower pad electrode; A protective layer formed to cover the conductive layer; A contact hole formed in a predetermined region of the protective layer; And an upper pad electrode formed in the contact hole to be electrically connected to the conductive layer and electrically connected to the lower pad electrode through the conductive layer.

According to an aspect of the present invention, there is provided a method of manufacturing a flat panel display, including: forming a signal line of a display panel and a lower pad electrode connected to the signal line; Forming a conductive layer on an upper surface of the lower pad electrode; Forming a protective layer to cover the conductive layer; Forming a contact hole by etching a predetermined region of the protective layer to expose a predetermined region of the conductive layer; And forming an upper pad electrode in the contact hole to be electrically connected to the lower pad electrode through the conductive layer.

As described above, the flat panel display and the manufacturing method thereof according to the present invention have the following effects.

First, a pad portion is formed to include a lower pad electrode made of a source / drain material, a conductive layer made of a transparent material, and an upper pad electrode, so that the conductive ball and the lower pad electrode are pressed by the conductive ball during bonding of the driving integrated circuit. Can be formed.

Second, through the pressing trace of the conductive ball formed on the lower pad electrode, it is possible to inspect the connection state of the conductive ball performed by the optical method after bonding of the driving integrated circuit to detect the defective connection by the conductive ball. You can do that.

1 is a diagram schematically illustrating a pad part of a typical chip on glass type liquid crystal display device.
2 is a diagram for schematically describing a flat panel display device according to a first exemplary embodiment of the present invention.
FIG. 3 is a diagram schematically illustrating an integrated circuit bonding unit according to an exemplary embodiment of the present invention illustrated in FIG. 2.
4 is a cross-sectional view illustrating a cross section of the AA line illustrated in FIG. 3.
FIG. 5 is a cross-sectional view illustrating a cross section of the BB line illustrated in FIG. 3.
6 is a diagram schematically illustrating a flat panel display device according to a second exemplary embodiment of the present invention.
7 is a diagram for schematically describing a flat panel display device according to a third exemplary embodiment of the present invention.
8A through 8H are steps of a manufacturing method of a flat panel display device according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram for schematically describing a flat panel display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 2, a flat panel display device according to a first embodiment of the present invention may include a display panel 100 and a driving integrated circuit 110; And a flexible printed circuit 120.

The display panel 100 includes a display area 102 for displaying an image and a non-display area 104 corresponding to the remaining areas except the display area 102.

The display area 102 includes a plurality of gate signal lines GL1 through GLm, a plurality of data signal lines DL1 through DLn, a plurality of gate signal lines GL1 through GLm, and a plurality of data signals formed at regular intervals so as to cross each other. It consists of the several pixel P formed for every area | region defined by the intersection of the lines DL1-DLn.

The pixel P includes a thin film transistor T connected to one gate signal line GL and one data signal line DL. The pixel P displays an image corresponding to a data signal supplied from the data signal line DL through the thin film transistor T. For example, the pixel P may be a liquid crystal cell displaying an image by adjusting the light transmittance of the liquid crystal according to a data signal supplied from the data signal line DL through the thin film transistor T. As another example, the pixel P may be a light emitting cell that emits light according to a current corresponding to a data signal supplied from the data signal line DL through the thin film transistor T to display an image.

The non-display area 104 bonds the driving integrated circuit 110 to supply a gate signal to the gate signal lines GL1 to GLm and to supply a data signal synchronized with the gate signal to the data signal lines DL1 to DLn. It is configured to include an integrated circuit bonding unit 120.

As illustrated in FIG. 3, the integrated circuit bonding unit 120 includes an output pad unit OPP and an input pad unit IPP.

The output pad part OPP includes first and second gate output pad parts GOP1 and GOP2 and a data output pad part DOP.

The first and second gate output pad parts GOP1 and GOP2 are formed with the data output pad part DOP interposed therebetween, and are provided with a plurality of gate pads GP electrically connected to the gate signal lines GL1 to GLm. It is comprised including the several gate connection part GCP.

Each of the plurality of gate pads GP may include a lower gate pad electrode DGPE, a gate conductive layer GCL, a protective layer 214, a plurality of gate contact holes GCH, and an upper portion thereof. And a gate pad electrode UGPE.

The lower gate pad electrode DGPE is formed on the insulating layer 212 formed on the substrate 210. In this case, the lower gate pad electrode DGPE is formed at the same time as the data signal lines DL1 to DLn and the source / drain electrodes of the thin film transistor T formed on the display panel 100. It is formed of / drain material.

The gate conductive layer GCL is formed on the lower gate pad electrode DGPE and is formed of a transparent material. In this case, the gate conductive layer GCL may include ZnO, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), ZTO (Zinc Tin Oxide) and ATO (Antimony Tin Oxide) may be formed of a transparent material.

The protective layer 214 is formed on the entire surface of the substrate 210 to cover the gate conductive layer GCL.

Each of the plurality of gate contact holes GCH is formed at regular intervals so that predetermined regions of the protective layer 214 are removed to expose predetermined regions of the gate conductive layer GCL. In this case, the gate conductive layer GCL serves as an etching stopper to prevent the lower gate pad electrode DGPE from being etched when the plurality of gate contact holes GCH are formed.

The upper gate pad electrode UGPE is formed on each of the plurality of gate contact holes GCH and the protection layer 214 and electrically connected to the gate conductive layer GCL through each of the plurality of gate contact holes GCH. The upper gate pad electrode UGPE may be formed of the same transparent material as the gate conductive layer GCL. The upper gate pad electrode UGPE is electrically connected to the lower gate pad electrode DGPE through the plurality of gate contact holes GCH and the gate conductive layer GCL.

Each of the plurality of gate connections GCP includes a gate link line GLL, a lower gate connection electrode DGCE, a gate via hole GVH, and an upper gate connection electrode UGCE, as shown in FIG. 4. It is configured by.

The gate link line GLL is formed simultaneously with the gate signal lines GL1 to GLm and the gate electrode of the thin film transistor T formed on the display panel 100, and is formed of the gate material of the thin film transistor T. The gate link line GLL is covered by the insulating layer 212.

The lower gate connection electrode DGCE extends from the lower gate pad electrode DGPE of the gate pad GP so as to overlap the gate link line GLL and is formed on the insulating layer 212.

The gate via hole GVH is formed so that predetermined regions of the passivation layer 214, the lower gate connection electrode DGCE, the insulating layer 212, and the gate link line GLL formed on the substrate 210 are removed. The predetermined region of 210 and the side surface of the gate link line GLL are exposed.

The upper gate connection electrode UGCE is formed on the gate via hole GVH and the protective layer 214 and is electrically connected to the gate link line GLL through the gate via hole GVH. The upper gate connection electrode UGCE may be formed of the same transparent material as the gate conductive layer GCL. The upper gate connection electrode UGCE electrically connects the lower gate connection electrode DGCE and the gate link line GLL through the gate via hole GVH so that the gate link line GLL is connected to the lower gate connection electrode DGCE. ) To be electrically connected to the lower gate pad electrode DGPE of the gate pad GP.

In FIG. 3, the data output pad part DOP includes a plurality of data pads DP electrically connected to the data signal lines DL1 to DLn.

As illustrated in FIG. 5, each of the plurality of data pads DP includes a lower data pad electrode DDPE, a data conductive layer DCL, a protective layer 214, a plurality of data contact holes DCH, and upper data. It comprises a pad electrode (UDPE).

The lower data pad electrode DDPE is formed on the insulating layer 212 formed on the substrate 210. In this case, the lower data pad electrode DDPE is formed at the same time as the data signal lines DL1 to DLn and the source / drain electrodes of the thin film transistor T formed on the display panel 100. It is formed of / drain material. The lower data pad electrode DDPE is electrically connected to the data signal lines DL1 to DLn of the display panel 100 through the data link line DLL illustrated in FIG. 3.

The data conductive layer DCL is formed on the lower data pad electrode DDPE and is formed of a transparent material. In this case, the data conductive layer DCL may be formed of any one of ZnO, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, ITO, IZO, ITZO, ZTO, and ATO.

The protective layer 214 is formed on the entire surface of the substrate 210 to cover the data conductive layer DCL.

Each of the plurality of data contact holes DCH is formed at regular intervals so that predetermined regions of the protective layer 214 are removed to expose predetermined regions of the data conductive layer DCL. In this case, the data conductive layer DCL serves as an etching stopper to prevent the lower data pad electrode DDPE from being etched when the plurality of data contact holes DCH are formed.

The upper data pad electrode UDPE is formed on each of the plurality of data contact holes DCH and the protection layer 214 and electrically connected to the data conducting layer DCL through each of the plurality of data contact holes DCH. The upper data pad electrode UDPE may be formed of the same transparent material as the data conductive layer DCL. The upper data pad electrode UDPE is electrically connected to the lower data pad electrode DDPE through the plurality of data contact holes DCH and the data conductive layer DCL.

Meanwhile, the lower data pad electrode UDPE is electrically connected to the data signal lines DL1 to DLn through the data link line DLL in the data output pad part DOP, but is not limited thereto. It may be electrically connected to the data signal lines DL1 to DLn through a data link line (not shown) and two data connections (not shown) formed of a gate material simultaneously with the gate link line GLL. Here, the two data connection portions may be formed to have the same structure as the above-described gate connection portion GCP.

On the other hand, in the above-described output pad unit OPP, the lower gate pad electrode DGPE and the lower data pad electrode DDPE are simultaneously formed of the same material by the same process, and the gate output pad units GOP1 and GOP2 are simultaneously formed. And the data output pad unit DOP are divided and described with separate reference numerals, and the lower gate pad electrode DGPE and the lower data pad electrode DDPE may be defined as lower pad electrodes.

Similarly, the gate conductive layer GCL and the data conductive layer DCL may also be defined as conductive layers, and the plurality of gate contact holes GCH and data contact holes DCH may also be defined as contact holes. The gate pad electrode UGPE and the upper data pad electrode UDPE may also be defined as the upper pad electrode.

In FIG. 3, the input pad unit IPP is electrically connected to the flexible printed circuit 130 bonded to the display panel 100 through the input link line ILL to drive driving power from the flexible printed circuit 130. And a plurality of input pads IP to which a timing synchronization signal and image data are supplied.

Each of the plurality of input pads IP is formed to have the same structure as the above-described data pad DP, and a detailed description thereof will be replaced with the above description of the data pad DP.

In FIG. 2, the driving integrated circuit 110 is integrated circuit bonding of the display panel 100 by an anisotropic conductive film (ACF) 140 (see FIGS. 4 and 5) according to a tape automated bonding (TAB) method. Bonding to 120 allows electrical connection to the input pad portion IPP and the output pad portion OPP.

To this end, the driving integrated circuit 100 may include a plurality of gate output terminals (or bumps) 112 (see FIG. 4), a plurality of data output terminals 114 (see FIG. 5), and a plurality of input terminals (not shown). It is configured to include.

Each of the plurality of gate output terminals 112 may be electrically connected to the upper gate pad electrodes UGPE of the plurality of gate pads GP through the conductive balls 142 of the ACF 140 as illustrated in FIG. 4. Is connected. At this time, the conductive ball 142 of the ACF 140 is dispersed in the gate contact hole GCH and the upper gate pad electrode UGPE by thermal pressure according to the TAB method so that the gate output terminal 112 and the upper gate pad electrode ( UGPE) are electrically connected to each other. Accordingly, the conductive balls 142 are pressed by the thermal pressure on the upper gate pad electrode UGPE, the gate conductive layer GCL, and the lower gate pad electrode DGPE formed on each of the plurality of gate pads GP. Traces PM are formed. The pressing trace PM of the conductive ball 142 formed on the lower gate pad electrode DGPE is performed by the optical method after bonding of the driving integrated circuit 110 through the optical ball and the lower gate pad. It is possible to check the connection state between the electrodes DGPE.

Each of the plurality of data output terminals 114 is electrically connected to the upper data pad electrodes UDPE of the plurality of data pads DP through the conductive balls 142 of the ACF 140 as illustrated in FIG. 5. Is connected. At this time, the conductive ball 142 of the ACF 140 is dispersed in the data contact hole (DCH) and the upper data pad electrode (UDPE) by the thermal pressure according to the TAB method so that the data output terminal 114 and the upper data pad electrode ( UDPE) are electrically connected to each other. Accordingly, the conductive balls 142 are pressed by the thermal pressure on the upper data pad electrode UDPE, the data conductive layer DCL, and the lower data pad electrode DDPE formed on each of the plurality of data pads DP. Traces PM are formed. The pressing trace PM of the conductive ball 142 formed on the lower data pad electrode DDPE is performed by an optical method after bonding of the driving integrated circuit 110 through the optical ball and the lower data pad. It is possible to check the connection state between the electrodes DDPE.

Each of the plurality of input terminals is electrically connected to the plurality of input pads IP via the conductive balls 142 of the ACF 140. In this case, the conductive ball 142 of the ACF 140 electrically connecting the plurality of input terminals and the plurality of input pads IP may have a lower pad electrode (not shown) in the same manner as the gate and data pads GP and DP described above. By forming the pressing trace PM on the C), it is possible to inspect the connection state of the conductive ball 142 which is performed through the optical method after the bonding of the driving integrated circuit 110.

The driving integrated circuit 100 may display the display panel 100 based on driving power, timing synchronization signals, and image data input from the flexible printed circuit 130 to the plurality of input terminals through the plurality of input pads IP. Generate a gate signal and a data signal for displaying an image. In addition, the driving integrated circuit 100 sequentially supplies the gate signals generated through the plurality of gate output terminals 112 to the plurality of gate pads GP so that the gate signal lines GL1 to GLm of the display panel 100 are provided. In addition, the data signal generated for each horizontal section is simultaneously supplied to the plurality of data pads DP through the plurality of data output terminals 114 so as to be synchronized with the gate signal.

Meanwhile, in the flat panel display according to the first exemplary embodiment of the present invention, the printed circuit bonding pad 132 formed on the display panel 100 to bond the flexible printed circuit 130 to the above-described data pad DP may also be used. It is formed to have the same structure.

The flat panel display according to the first exemplary embodiment of the present invention includes the lower pad electrodes DGPE and DDPE made of a source / drain material, the conductive layers GCL and DCL made of a transparent material, and the upper pad electrodes UGPE and UDPE. By forming each of the input pad unit IPP and the output pad unit OPP to include a, the upper pad electrodes UGPE and UDPE when bonding the driving integrated circuit 110, as shown in FIGS. 4 and 5, The traces PM by pressing the conductive balls 142 are formed on the conductive layers GCL and DCL and the lower pad electrodes DGPE and DDPE.

Therefore, the flat panel display device according to the first exemplary embodiment of the present invention after the bonding of the driving integrated circuit 110 through the pressing traces PM of the conductive balls 142 formed on the lower pad electrodes DGPE and DDPE. Inspection of the connection state of the conductive ball 142 performed by the optical method may be enabled to detect the connection failure by the conductive ball 142.

6 is a diagram schematically illustrating a flat panel display device according to a second exemplary embodiment of the present invention.

Referring to FIG. 6, a flat panel display device according to a second embodiment of the present invention may include a display panel 300, at least one gate driver integrated circuit 310, a plurality of data driver integrated circuits 320, and flexible printing. And a circuit 330.

The display panel 300 includes a display area 302 for displaying an image and a non-display area 304 corresponding to the remaining areas except for the display area 302.

The display area 302 crosses a plurality of gate signal lines GL, a plurality of data signal lines DL, a plurality of gate signal lines GL, and a plurality of data signal lines DL formed at regular intervals so as to cross each other. It is comprised including the some pixel P formed for every area | region defined by.

As illustrated in FIG. 2, the pixel P includes a thin film transistor T connected to one gate signal line GL and one data signal line DL.

In the non-display area 304, at least one gate driving integrated circuit 310 for supplying a gate signal to the gate signal line GL is bonded, and a data signal synchronized with the gate signal is supplied to the data signal line DL. A plurality of data driver integrated circuits 320 are bonded to each other.

The at least one gate driving integrated circuit 310 is bonded to one side non-display area 304 of the display panel 300 corresponding to one side of the gate signal line GL to sequentially gate the signal to the gate signal line GL. Supply. To this end, at least one gate integrated circuit bonding unit (not shown) is provided in one side of the non-display area 304 of the display panel 300, and the at least one gate integrated circuit bonding unit includes a gate input pad unit (not shown), And a gate output pad part (not shown).

A plurality of gate input pads (not shown) electrically connected to the flexible printed circuit 330 through gate signal input lines (not shown) formed in one side non-display area 304 of the display panel 300. It is configured to include.

The gate output pad part includes a plurality of gate output pads (not shown) electrically connected to the gate signal line GL.

Since the gate input pad and the gate output pad are formed to have the same structure as the input pad IP and the gate pad GP shown in FIGS. 3 and 4, a detailed description thereof will be replaced with the above description.

Each of the at least one gate integrated circuit bonding unit is bonded to terminals of the gate driving integrated circuit 310 by a conductive ball of an ACF (not shown) according to the TAB method.

The plurality of data driving integrated circuits 320 are bonded to the upper non-display area 304 of the display panel 300 corresponding to one side of the data signal line DL to supply the data signal to the data signal line DL. To this end, a plurality of data integrated circuit bonding units (not shown) are provided in one side of the non-display area 304 of the display panel 300, and each of the plurality of data integrated circuit bonding units may include a data input pad unit (not shown), And a data output pad unit (not shown).

A plurality of data input pads (not shown) electrically connected to the flexible printed circuit 330 through data signal input lines (not shown) formed in the upper non-display area 304 of the display panel 300. It is configured to include.

The data output pad part includes a plurality of data output pads (not shown) electrically connected to the data signal line DL.

Since the data input pad and the data output pad are formed to have the same structure as the input pad IP and the data pad DP shown in FIGS. 3 and 5, a detailed description thereof will be replaced with the above description.

The terminals of the data driving integrated circuit 320 are bonded to each of the plurality of data integrated circuit bonding units by conductive balls of the ACF according to the TAB method.

The flexible printed circuit 330 is bonded to a plurality of printed circuit bonding pads (not shown) provided in the upper non-display area 304 of the display panel 300 by the conductive ball of the ACF according to the TAB method.

The plurality of printed circuit bonding pads are electrically connected to the data input pads of the plurality of data integrated circuit bonding units through data signal input lines (not shown) formed in the upper non-display area 304 of the display panel 300. It is also electrically connected to the gate signal input line. In this case, each of the plurality of printed circuit bonding pads is formed to have the same structure as that of the data pad DP shown in FIGS. 3 and 5.

The flat panel display device according to the second embodiment of the present invention described above is performed by the optical method after bonding the driving integrated circuits 310 and 320 through the pressing trace of the conductive ball in the same manner as the first embodiment of the present invention. Inspection of the connection state of the conductive balls to be made possible can be made possible to detect the connection failure by the conductive balls.

7 is a diagram for schematically describing a flat panel display device according to a third exemplary embodiment of the present invention.

Referring to FIG. 7, a flat panel display device according to a third embodiment of the present invention may include a display panel 300, at least one gate circuit film 410 on which a gate driving integrated circuit 310 is mounted, and a data driving integrated circuit. And a plurality of data circuit films 420 on which the 320 is mounted, a printed circuit board 500, and a timing controller 510.

The display panel 300 includes a display area 302 for displaying an image and a non-display area 304 corresponding to the remaining areas except for the display area 302.

The display area 302 crosses a plurality of gate signal lines GL, a plurality of data signal lines DL, a plurality of gate signal lines GL, and a plurality of data signal lines DL formed at regular intervals so as to cross each other. It is comprised including the some pixel P formed for every area | region defined by.

As illustrated in FIG. 2, the pixel P includes a thin film transistor T connected to one gate signal line GL and one data signal line DL.

In the non-display area 304, at least one gate driving integrated circuit 310 for supplying a gate signal to the gate signal line GL is bonded, and a data signal synchronized with the gate signal is supplied to the data signal line DL. A plurality of data driver integrated circuits 320 are bonded to each other.

The gate driving integrated circuit 310 is mounted on the gate circuit film 410 to generate and output a gate signal for driving the gate signal line GL under the control of the timing controller 510.

The at least one gate circuit film 410 is bonded to a gate pad part (not shown) formed in one non-display area 304 of the display panel 300 corresponding to one side of the gate signal line GL, thereby driving a gate driving integrated circuit. The gate signal output from the 310 is supplied to the gate signal line GL. In this case, at least one terminal of the gate circuit film 410 is bonded to the gate pad part by the conductive ball of the ACF according to the TAB method. Here, the gate circuit film 410 may be a tape carrier package (TCP) or a chip on film (COF).

The gate pad part includes a plurality of gate pads (not shown) formed to have the same structure as the gate pad GP shown in FIGS. 3 and 4 and electrically connected to the gate signal line GL.

The data driving integrated circuit 320 is mounted on the data circuit film 420 to generate and output a data signal for driving the data signal line DL under the control of the timing controller 510.

Each of the plurality of data circuit films 420 is bonded to a data pad part (not shown) formed in one non-display area 304 of the display panel 300 corresponding to one side of the data signal line DL, thereby driving the data driving integrated circuit. The data signal output from 320 is supplied to the data signal line GL. At this time, the terminals of each of the plurality of data circuit films 410 are bonded to the data pad part by the conductive balls of the ACF according to the TAB method. Here, the data circuit film 420 may be TCP or COF.

The data pad part includes a plurality of data pads (not shown) formed to have the same structure as the data pad DP shown in FIGS. 3 and 5 and electrically connected to the data signal line DL.

The printed circuit board 500 is electrically connected to the plurality of data circuit films 420 by conductive balls of ACF according to the TAB method.

The timing controller 510 is mounted on the printed circuit board 500 to generate image data corresponding to an input image supplied from the outside, and generates the image data through the printed circuit board 500 and the data circuit film 420. The data driving integrated circuit 320 is supplied to the data driving integrated circuit 320.

In addition, the timing controller 510 controls the driving of the gate driver integrated circuit 310 and the data driver integrated circuit 320 based on a timing synchronization signal supplied from the outside.

The flat panel display device according to the third embodiment of the present invention described above is performed by an optical method after bonding the circuit films 410 and 420 through the pressing trace of the conductive ball in the same manner as the first embodiment of the present invention. Inspection of the connection state of the conductive balls can be made possible so that a defective connection can be detected by the conductive balls.

8A through 8H are steps of a manufacturing method of a flat panel display device according to an exemplary embodiment of the present invention.

Referring to FIGS. 8A to 8H, a method of manufacturing a flat panel display device according to an exemplary embodiment of the present invention will be described below.

First, as shown in FIG. 8A, a gate link line GLL made of a gate material is formed in a non-display area of the substrate 210. At the same time, a gate signal line (not shown) made of a gate material and a gate electrode (not shown) protruding from the gate signal line are formed in each pixel in the display area of the substrate 210.

Next, as shown in FIG. 8B, an insulating layer 212 is formed on the entire surface of the substrate 210.

Next, as shown in FIG. 8C, after the source / drain material is formed on the entire surface of the insulating layer 212, the source / drain material formed on the non-display area of the substrate 210 is selectively removed to connect the lower gate. A lower pad electrode divided into an electrode DGCE, a lower gate pad electrode DGPE, and a lower data pad electrode DDPE is formed. The lower gate connection electrode DGCE extends from the lower gate pad electrode DGPE so as to overlap the gate link line GLL. At the same time, the source / drain material formed on the display area of the substrate 210 may be selectively removed to protrude data signal lines (not shown), data link lines (not shown), and source electrodes protruding from the data signal lines for each pixel. And a drain electrode spaced apart from the source electrode by a predetermined distance.

Meanwhile, a semiconductor layer (not shown) is formed between the insulating layer 212 formed on the substrate 210 and the source / drain material. As a result, a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode is formed in each pixel.

Then, as shown in FIG. 8D, after forming a transparent material conductive material on the source / drain material, the conductive material formed on the source / drain material is selectively removed to remove the lower gate pad electrode DGPE and the lower part. A gate conductive layer GCL and a data conductive layer DCL are electrically connected to each of the data pad electrodes DDPE.

Next, as shown in FIG. 8E, a protective layer 214 is formed on the entire surface of the substrate 210.

Then, as shown in FIG. 8F, the protective layer 214, the lower gate connection electrode DGCE, and predetermined regions of the gate link line GLL are etched to form the gate via hole GVH, and at the same time, the protection is performed. A plurality of gate contact holes GCH for exposing a predetermined region of the gate conductive layer GCL by etching a predetermined region of the layer 214 and a plurality of data contact holes for exposing predetermined regions of the data conductive layer DCL. (DCH) is formed. Here, the gate conductive layer GCL serves as an etching stopper to prevent the etching of the lower gate pad electrode DGPE during etching, and the data conductive layer DCL performs etching of the lower data pad electrode DDPE during etching. Serves as an etching stopper to prevent. At the same time, a pixel contact hole (not shown) is formed in the display area to expose a predetermined area of the source / drain electrodes of each thin film transistor.

Then, as shown in FIG. 8G, a conductive material made of a transparent material is formed on the protective layer 214 including the gate via hole GCH, the gate, and the data contact holes GCH and DCH. The material may be selectively etched to electrically connect to the gate conduction layer GCL through the gate contact hole GCH and the upper gate connection electrode UGCE electrically connected to the gate link line GLL through the gate via hole GCH. The gate connection part GCP and the gate pad GP are formed by forming the upper gate pad electrode UGPE to be connected and the upper data pad electrode UDPE electrically connected to the data conductive layer DCL through the data contact hole DCH. ) And a data pad DP. At the same time, a pixel electrode (not shown) electrically connected to the source / drain electrodes of each thin film transistor is formed in the display area through the pixel contact hole (not shown).

Then, as illustrated in FIG. 8H, the TAB method of attaching the ACF 140 having the conductive balls 142 dispersed thereon onto the upper gate connection electrode UGCE and the upper data pad electrode UDPE, and then thermally compressing the same. Accordingly, the gate and data terminals of the driving integrated circuit 100 are electrically connected to the upper gate pad electrode UGPE and the upper data pad electrode UDPE, respectively. Accordingly, the gate terminal of the driving integrated circuit 100 may include the upper gate pad electrode UGPE, the gate conductive layer GCL, the lower gate pad electrode DGPE, the lower gate connection electrode DGCE, and the upper gate connection electrode UGCE. And a gate signal line through the gate link line GLL. In addition, the data terminal of the driving integrated circuit 100 may be electrically connected to the data signal line through an upper data pad electrode UDPE, a data conductive layer DCL, a lower data pad electrode DDPE, and a data link line (not shown). Is connected.

The manufacturing method of the flat panel display device according to the embodiment of the present invention described above includes lower pad electrodes DGPE and DDPE made of a source / drain material, conductive layers GCL and DCL made of a transparent material, and upper pad electrodes UGPE and UDPE. Each of the gate and data pads GP and DP is formed to include the upper pad electrodes UGPE and UDPE during bonding of the driving integrated circuit 110 via the ACF 140, as shown in FIG. 8H. ), The traces PM by pressing the conductive balls 142 are formed on the conductive layers GCL and DCL and the lower pad electrodes DGPE and DDPE.

Accordingly, in the method of manufacturing the flat panel display device according to the embodiment of the present invention, the conductive ball 142 is connected through the optical method after bonding of the driving integrated circuit 110 through the pressing trace of the conductive ball 142. Inspection of the state can be made possible so that a connection failure can be detected by the conductive ball.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100 and 300: display panel 110: driving integrated circuit
120: integrated circuit bonding unit 140: ACF
142: conductive ball 210: substrate
212: insulating layer 214: protective layer

Claims (14)

A lower pad electrode connected to the signal line of the display panel;
A conductive layer formed on an upper surface of the lower pad electrode;
A protective layer formed to cover the conductive layer;
A contact hole formed in a predetermined region of the protective layer; And
And an upper pad electrode formed in the contact hole to be electrically connected to the conductive layer and electrically connected to the lower pad electrode through the conductive layer. The method of claim 1,
The upper pad electrode is formed on any one of a flexible printed circuit, an integrated circuit, and a circuit film mounted with the integrated circuit for supplying a predetermined signal to the signal line by an adhesive member including a plurality of conductive balls. A flat panel display, which is electrically connected to a terminal. The method of claim 2,
And a trace formed by pressing the plurality of conductive balls on each of the upper pad electrode, the conductive layer, and the lower pad electrode. The method of claim 1,
And the conductive layer and the upper pad electrode are made of a transparent material. The method of claim 1,
The signal line is formed on the display panel and is electrically connected to at least one of a data signal line to which a data signal is supplied and a gate signal line to which the gate signal is supplied so as to intersect the data signal line. Flat panel display device. The method of claim 5, wherein
And the lower pad electrode is formed of the same material as the data signal line. The method of claim 5, wherein
A gate link line formed on the substrate to be electrically connected to the gate signal line;
A lower gate connection electrode formed on an insulating layer formed to cover the gate link line and extending from the lower pad electrode to overlap the gate link line;
A via hole formed in a predetermined region of the protective layer, the lower gate connection electrode, the insulating layer, and the gate link line; And
And an upper gate connection electrode formed in the via hole to electrically connect the lower gate connection electrode to the gate link line. Forming a signal line of a display panel and a lower pad electrode connected to the signal line;
Forming a conductive layer on an upper surface of the lower pad electrode;
Forming a protective layer to cover the conductive layer;
Forming a contact hole by etching a predetermined region of the protective layer to expose a predetermined region of the conductive layer; And
And forming an upper pad electrode in the contact hole to be electrically connected to the lower pad electrode through the conductive layer. The method of claim 8,
Bonding any one of a flexible printed circuit, an integrated circuit, and a circuit film on which the integrated circuit is mounted to supply the predetermined voltage to the signal line by using an adhesive member including a plurality of conductive balls. A method of manufacturing a flat panel display, characterized in that it further comprises the step of. The method of claim 8,
The conductive layer and the upper pad electrode are ZnO, ZnO: B, ZnO: Al, SnO ₂ , SnO ₂ : F, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Tin Zinc Oxide (ITZO), ZTO (Zinc Tin Oxide) and ATO (Antimony Tin Oxide), the method of manufacturing a flat panel display device characterized in that formed of a material. The method of claim 8,
And the signal line is at least one of a data signal line formed on the display panel to supply a data signal and a gate signal line formed on the display panel so as to intersect the data signal line and supplied with a gate signal. Method of manufacturing the device. The method of claim 11,
And the lower pad electrode is formed of the same material as the data signal line. The method of claim 11,
Before forming the lower pad electrode, forming a gate link line electrically connected to the gate signal line on a substrate, and then forming an insulating layer to cover the gate link line;
Forming a lower gate connection electrode extending from the lower pad electrode on the insulating layer overlapping the gate link line at the same time as the lower pad electrode is formed;
Simultaneously forming the via hole by etching a predetermined region of the passivation layer, the lower gate connection electrode, the insulating layer, and the gate link line; And
And forming an upper gate connection electrode in the via hole such that the lower gate connection electrode and the gate link line are electrically connected to each other at the same time as the upper pad electrode is formed. Manufacturing method. The method of claim 8,
And wherein the conductive layer prevents etching of the lower pad electrode when the contact hole is formed.

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