KR20110078258A - Method for removing dimple defect using wafer backside cleaning - Google Patents

Abstract

PURPOSE: A method for removing dimple defects using wafer backside cleaning is provided to increase production yield by removing a source preventing the STI gap fill of a high tech semiconductor product group to be less than 130um. CONSTITUTION: In a method for removing dimple defects using wafer backside cleaning, B / S wet etch is performed between an SI RIE(Reactive Ion Etch) process and an AA(Active Area) SI RIE process. The TEOS of the wafer backside is removed and STI dimple is removed. B / S wet etch is removed by using an oxide etchant. The wafer backside is cleaned firstly before etching oxide etchant and the particles of FEOL is removed.

Description

Dimple Defect Removal through Wafer Backside Cleaning {METHOD FOR REMOVING DIMPLE DEFECT USING WAFER BACKSIDE CLEANING}

The present invention relates to a method for removing dimple defects through wafer backside cleaning. More specifically, the present invention relates to a wafer backside cleaning method for improving the yield of a product by removing a source that obstructs the STI gap fill of a high-tech semiconductor product of 130 μm or less. It relates to a method for removing dimple defects.

In general, after the Reactive Ion Etch (RIE) process in the semiconductor process, By-product (Polymer) is generated. Such By-Product affects not only the product but also subsequent materials. do.

In the active area (hereinafter referred to as 'AA') formation of the semiconductor manufacturing process as shown in Table 1, AA RIE, AA SPA RIE, and AA SI RIE 3 processes are performed. After each RIE step, the wafer backside is processed. As shown in FIG. 1, there are a number of defects that serve as sources of contamination.

These defects that adhere to the wafer backside are removed along with the oxide film and transferred to the wafer front during the SH Clean & Pre Clean process, which is carried out after the RIE, and during the wet process to prevent this phenomenon. The front surface of the wafer and its surface can be opposed to proceed to minimize the defect adsorption.

The defects adsorbed in this way interfere with the isolation between active and active wafers during the AA HDP Fill process. The defects caused by these defects are called STI dimples. .

However, these STI dimples are occurring in all semiconductor products as killing defects, especially in the dense line of flash products of 130 nm or less, which seriously degrades the yield of flash products. Is in a situation.

SUMMARY OF THE INVENTION The present invention was created in view of the above-described problems in the prior art, and improves the yield of a product by removing a source that obstructs the STI gap fill of a high-tech semiconductor product of 130 μm or less through wafer backside cleaning. A major challenge is to provide a method for removing dimple defects through wafer backside cleaning.

According to an aspect of the present invention, there is provided a method for removing an STI dimple defect when performing an active area (AA) formation during a semiconductor manufacturing process; The wafer backside cleaning may be performed by removing the PAD TEOS of the wafer backside by performing a B / S WET ETCH between the SI RIE process and the POST AA SI RIE process. It provides a method for removing dimple defects.

At this time, the B / S WET ETCH is also characterized by removing using an oxide etchant (Oxide Etchant).

In addition, the wafer backside is first cleaned before etching with the oxide etchant to remove particles of FEOL.

In addition, the B / S WET ETCH is also characterized in that it is applied to the high-tech semiconductor product line 130㎛ or less.

According to the present invention, by removing the particles causing the defect through the wafer backside cleaning, it is possible to prevent the STI gap fill interference, to prevent particle reduction occurring during the AA formation, and to increase the yield. .

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment according to the present invention.

Figure 2 is a structural diagram showing a film stack laminated on the wafer backside for explaining the present invention, Figure 3 is a schematic diagram showing a film stack of the wafer backside treated by the method according to the invention, Figure 4 is in accordance with the present invention It is a graph which shows the yield at the time of a process compared with the process without a process.

As described above, in the case of particles falling on the active line during the formation of the STI, the majority of the particles originating from the wafer backside were found to be caused by the transition to the front.

Thus, when checking the stack of the film laminated on the wafer backside, it can be seen that a plurality of particles 100 are attached as shown in FIG. 3.

This may simply prevent particle adsorption by the wafer backside by etching the Pad TEOS containing the particle source after the Wet process to remove the defect source.

In view of the foregoing, the present invention performs the B / S WET ETCH between the AA SI RIE process and the POST AA SI RIE process, as shown in Table 2 and FIG. 3 below. 110) to effectively remove the STI dimples.

At this time, the B / S WET ETCH is preferably removed using an oxide etchant.

In this case, particles of FEOL can also be removed by cleaning the wafer backside prior to etching with oxide etchant.

More specifically, as shown in Table 2, the process of proceeding RIE in AA formation is AA RIE, AA SPA RIE, AA SI RIE, AA RIE, AA SPA RIE is AA AA etching the silicon by oxide etching (Etching) Polymer generation is less than SI RIE, and the subsequent cleaning process also does not oxidize oxides by SH cleaning and COM (SC-2) cleaning. Defect transition is relatively low.

Accordingly, the STI dimple may be effectively removed by removing the PAD TEOS 110 after the AA SI RIE process in which the polymer generation is large and the oxide is etched into dHF in a subsequent process.

In order to confirm this, as a result of the experiment by adding the B / S Wet Etch (PAD TEOS removal process) to the actual 130nm flash product, as shown in Figure 4 was able to obtain a yield improvement effect of more than 1.4% compared to the conventional yield

Therefore, by adding the B / S Wet Etch process in AA Formation, it was possible to remove a large number of particles caused by the wafer backside (Wafer Backside), thereby obtaining a yield improvement effect.

Based on this result, it is expected that significant yield improvement can be expected by adding wet process for PAD TEOS stripping to all products during active formation.

1 is a view showing a state in which the front surface after loading the wafer according to the conventional method backside,

2 is a structural diagram showing a film stack laminated on a wafer backside for explaining the present invention;

3 is a schematic diagram showing a film stack of a wafer backside treated by the method according to the present invention;

Figure 4 is a graph showing the yield at the time of treatment with the method according to the present invention compared to the time without treatment.

♧ description of the symbols for the main parts of the drawing ♧

100: Particle 110: PAD TEOS

Claims (3)

A method for removing STI dimple defects when performing active area (AA) formation during a semiconductor manufacturing process; The wafer backside cleaning may be performed by removing the PAD TEOS of the wafer backside by performing a B / S WET ETCH between the SI RIE process and the POST AA SI RIE process. How to remove dimple defects through The method according to claim 1; The B / S WET ETCH is removed using a oxide etchant (Oxide Etchant), characterized in that the dimple defect removal method through the wafer backside cleaning. The method according to claim 2; A method for removing dimple defects through wafer backside cleaning, wherein the wafer backside is first cleaned prior to etching with the oxide etchant to remove particles of FEOL.

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