KR100611008B1 - Wafer cleaning method in the semiconductor processing - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wet cleaning method in a semiconductor process, and in particular, foreign matters generated during a wafer cleaning process by not depositing HF in a pre-furnace cleaning step after a high voltage ion implantation (HV NWELL & HV PWELL Implant). Wafer cleaning in the semiconductor process that can improve the yield and reliability of the semiconductor by preventing the transition to the form of silicon pits by reacting with the silicon (Si) interface in the subsequent high temperature process (Well Anneal) It is about a method.

Wafer Cleaning, Standard Cleaning 1 (SC-1), Standard Cleaning 2 (SC-2), Silicon (Si), Pit

Description

Wafer cleaning method in the semiconductor processing

1 is a view showing a process of a cleaning method in a conventional semiconductor process.

2 is a view schematically showing generation of silicon pits by a cleaning method in a conventional semiconductor process.

Figure 3 (a) is a view showing the process of one embodiment of a wafer cleaning method in a semiconductor process according to the present invention.

Figure 3 (b) is a view showing a process of another embodiment of the wafer cleaning method in the semiconductor process according to the present invention.

4 is a view showing a silicon pit prevented by a wafer cleaning method in a semiconductor process according to the present invention.

<Explanation of symbols for the main parts of the drawings>

110: zero oxide

112: Remain Pad Oxide

120: high voltage N well ion implantation (HV NWELL Implant)

130: high voltage P well ion implantation (HV PWELL Implant)

140: silicon substrate 150: contaminants

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wet cleaning method in a semiconductor process, and in particular, foreign matters generated during a pre-furnace cleaning process after high voltage ion implantation (HV NWELL & HV PWELL Implant) are well annealed (Well Anneal). The present invention relates to a wafer cleaning method in a semiconductor process capable of preventing a reaction with a silicon (Si) interface and transitioning into a silicon pit, thereby improving semiconductor yield and reliability.

Generally, the cleaning method used in the semiconductor process is largely divided into dry cleaning and wet cleaning, and the wet cleaning method includes Sulfuric PerOxide Mixture (SPM) cleaning, Dilute Hydrofluoric Acid (DHF) cleaning, and RCA cleaning. Method and the like.

However, the RCA cleaning method was proposed by W. Kern of RCA, USA in the 1970s as a synonym for a wet cleaning method, and is widely used as a semiconductor manufacturing process. RCA cleaning method commonly uses hydrogen peroxide (H ₂ O ₂ ) as a basis, and there are two main methods, SC-1 (Standard Clean-1) and SC-2 (Standard Clean-2). Hereinafter, a cleaning method in a conventional semiconductor process will be described in detail with reference to the accompanying drawings.

1 is a view showing an RCA cleaning method in a conventional semiconductor process.

According to the cleaning method of the conventional semiconductor process, the wafer subjected to high voltage ion implantation (HNWELL & HPWELL Implant) is subjected to pre-furnace cleaning, and the well-annealed wafer is subjected to wafer cleaning (pre-furnace cleaning).

First, pre-furnace cleaning of a wafer subjected to high voltage ion implantation (HNWELL & HPWELL Implant) will be described. This includes a cleaning process that proceeds to SC-1 (Standard Clean-1), HF deposition, and Dry.

SC-1 is a mixture of ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) in a ratio of about 1: 1: 5. It is a cleaning method for removing contaminants such as organic contaminants. Next, fluorine (HF) deposition is performed at room temperature for about 1800 seconds. HF is used in a diluted state (1% HF-H ₂ O). Fluoride (HF) deposition is a typical method of etching silicon oxide (SiO ₂ ). The wafer is spin dried after silicon oxide etching by fluorine (HF) deposition.

Next, the wafer annealed wafer (WELL Annealed) will be described in the wafer (Pre Furnace Cleaning). The cleaning process is performed in the order of SC-1 (Standard Clean-1), HF deposition, SC-2 (Standard Clean-2), and drying step.

Performing SC-1 (Standard Clean-1), HF deposition and drying step is the same as described above.

SC-2 (Standard Clean-2) is a solution of hydrochloric acid (HCl), hydrogen peroxide and water in a ratio of about 1: 1: 6 to remove transition metal contaminants at room temperature.

However, in the case of using dilute HF (1% HF-HO ₂ ) in the conventional semiconductor cleaning method, the silicon wafer, which was a hydrophilic surface, becomes hydrophobic as the oxide film is removed by HF deposition. However, since the hydrophobic surface is activated, there is a problem that foreign substances are generated by being contaminated with particles or organic substances from chemicals or process environments.

In addition, during the dilution HF deposition process, a metal having a smaller ionization tendency than Si, such as Cu, was deposited on the surface of the silicon wafer, thereby causing foreign matter.

Particularly problematic is that the foreign matter generated during the pre-furnace cleaning after high voltage ion implantation (HV NWELL & HV PWELL Implant) reacts with the silicon (Si) wafer interface in a high temperature process which is subsequent well annealing. This results in the transfer of silicon pit into the form of a problem that lowers the yield and reliability of the semiconductor.

That is, according to the cleaning method according to the prior art, the equipment at the time of pre-furnace cleaning performed before the well annealing after the high voltage ion injection in the high voltage device. If there is a problem with the part or if there is a chemical problem, a foreign substance is generated and it reacts with the silicon (Si) during a long time high temperature process called annealing, which is a subsequent process. Will create a.

Hereinafter, such a problem will be described in detail with reference to FIG. 2.

2 is a view schematically showing generation of silicon pits by a cleaning method in a conventional semiconductor process.

FIG. 2A illustrates a wafer in a state in which a high voltage NWELL & PWELL implant is performed in a high voltage device, and a zero oxide 10 is formed on a silicon substrate 40. After the formation, the high voltage N well ion implantation (HV NWELL Implant) 20 and the high voltage P well ion implantation (HV PWELL Implant) 30 are shown.

FIG. 2 (b) shows that there is a problem in the equipment part or a chemical problem when the wafers subjected to high voltage ion implantation (HNWELL & HPWELL Implant) 20 and 30 are subjected to wafer cleaning (Pre Furnace Cleaning). In this case, the foreign material 50 is generated on the surface of the silicon wafer.

FIG. 2 (c) illustrates a defect in the form of silicon pits 60 when the wafer of FIG. 2 (b) is subjected to a high temperature process such as annealing. The silicon pits 60 refer to the fact that the pits are created on the silicon wafer.

That is, according to the cleaning method in the conventional semiconductor process, foreign matters generated during the pre-furnace cleaning after the high voltage ion implantation (HV NWELL & HV PWELL Implant) are silicon in the high temperature process of subsequent well annealing. There was a problem of reacting with the Si) interface to transfer into a silicon pit to reduce the yield and reliability of the semiconductor.

Therefore, the present invention minimizes the generation of foreign matters in the pre-furnace cleaning process after the HV NWELL & HV PWELL Implant, and furthermore, the foreign matters generated are silicon in the high temperature process of the subsequent well annealing. The purpose of the present invention is to contribute to improving the yield and reliability of semiconductor products by preventing the occurrence of pits in advance by improving the cleaning process.

In order to achieve the above object, a wafer cleaning method in a semiconductor process according to the present invention includes: pre-furnace cleaning a wafer of high voltage ion implanted (HNWELL & HPWELL Implant) so that a pad oxide layer remains; And pad an oxide pre-furnace cleaning after well-annealing the cleaned wafer. Characterized in that it comprises a.

In addition, the wafer cleaning (Pre Furnace Cleaning) step is SC-1 (Standard Clean-1) cleaning step at 75 ~ 85 ℃; And drying the wafer, wherein the wafer is pre-furnace cleaned.

In addition, the pad oxide layer cleaning (Pad Oxideide Pre Furnace Cleaning) step may be a step of SC-1 cleaning the wafer at 75 ~ 85 ℃; Depositing fluorine (HF) at room temperature on the SC-1 cleaned wafer; SC-2 (Standard Clean-2) at room temperature on the HF deposited wafer; And drying the SC-2 wafer.

In addition, the HF deposition step may be performed at room temperature 1800 ~ 2200 seconds.

The method may further include buffer oxide etching after the pad oxide layer cleaning.

According to the present invention, foreign matters are prevented from occurring during the pre-furnace cleaning after the high voltage ion implantation (HV NWELL & HV PWELL Implant), and foreign matter present in the equipment part or the chemical is subsequently well annealed ( In the high temperature process, which is a well anneal, it effectively prevents the transition to the form of silicon pits by reacting with the silicon (Si) interface, thereby significantly improving the yield and reliability of the semiconductor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A is a view illustrating a cleaning process of a wafer cleaning method in a semiconductor process according to the present invention.

According to a preferred embodiment of the present invention, the cleaning process is performed in the order of pre-furnace cleaning of the wafers subjected to high voltage ion implantation (HNWELL & HPWELL Implant), followed by well-annealed pad oxide oxide cleaning. This is going on.

First, a step of pre-furnace cleaning of a wafer subjected to high voltage ion implantation (HNWELL & HPWELL Implant) will be described. This is done in the order of SC-1 (Standard Clean-1) cleaning step and Drying step (Dry). This will be described in detail below.

SC-1 (Standard Clean-1) cleaning step according to the present invention is a ratio of ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and water (H ₂ O) 100: 90 ~ 110: 450 ~ 550, respectively Refers to a cleaning method for removing contaminants such as particles and organic contaminants using the prepared mixed solution. Preferably, ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and water (H ₂ O) are more preferably in a ratio of 100: 100: 500.

On the other hand, the temperature of the SC-1 cleaning according to the present invention proceeds at a rather high temperature of 75-85 ° C., preferably about 80 ° C., which prevents the cleaning solution from being sufficiently activated and rapidly decomposing hydrogen peroxide at low temperatures. To do this.

Next, when the drying step (Dry) is described, the drying step (Dry) may use conventional spin drying, and in the present invention, it is more preferable to use IPA (Isopropyl Alcohol, isopropyl alcohol). Do.

The well annealed Pad Oxide Furnace Cleaning step will now be described. This is a cleaning process in the order of SC-1 cleaning step at 75 ~ 85 ℃, HF deposition step at room temperature, SC-2 cleaning step and drying step (Dry) at room temperature.

SC-1 cleaning step is the same as the step of pre-furnace cleaning (HNWELL & HPWELL Implant) wafer.

HF deposition according to the present invention is preferably carried out at room temperature for 1800 ~ 2000 seconds. This is the biggest difference from the HF deposition about 1800 seconds in the pre-furnace cleaning step of the high voltage ion implanted (HNWELL & HPWELL Implant) in the cleaning method according to the prior art. That is, the HF deposition according to the present invention is not performed in the pre-furnace cleaning step of the high voltage ion implanted (HNWELL & HPWELL Implant) step, but proceeds only in the pad oxide layer cleaning step, preferably 1800 to 2200 seconds at room temperature, preferably It takes about 2000 seconds. This is because the remaining pad oxide layer (Pad Oxide) is further grown, it is preferable to slightly over-etch for etching.

Next, SC-2 cleaning is demonstrated. SC-2 (Standard Clean-2) according to the present invention is a mixture of hydrochloric acid (HCl), hydrogen peroxide and water in a ratio of about 100: 90 ~ 110: 550 ~ 650, preferably in a ratio of 100: 100; 600 It is a cleaning method that removes transitional metal contaminants at room temperature with a solution. SC-2 rinsing is collectively called the Hydrochloric PerOxide Mixture (HPM).

Next, the drying step (Dry) may use a conventional spin dry, it is more preferable to use IPA (Isopropyl Alcohol, isopropyl alcohol).

Typically, the cleaning is finished by drying (Dry), and then a pad oxide layer is formed to protect the silicon wafer in the semiconductor process.

FIG. 3B is a view showing another embodiment of the wafer cleaning method in the semiconductor process according to the present invention.

The embodiment of FIG. 3 (b) is further characterized by further performing a buffer oxide etching process after pad oxide burn cleaning of FIG. 3 (a).

Usually, HF is effective for etching oxide film (SiO ₂ ). However, since pure HF etches the oxide layer (SiO ₂ ) too quickly, it is difficult to control the etching time. On the other hand, when HF is diluted with water, the etching rate is slowed down, but hydrogen ions are generated to change the etching rate, which makes it difficult to control the etching rate. In order to solve this problem, mixing NH ₄ F (ammonium fluoride) with HF buffers the etching reaction between HF and the oxide layer, thereby controlling the etching rate. This etching is called Buffer Oxide Etch (BOE). The ratio of HF and NH ₄ F according to the present invention is preferably 35 to 45: 0.3 to 2.0, preferably 39.1: 0.49.

4 is a view schematically showing how silicon pits are prevented by a wafer cleaning method in a semiconductor process according to the present invention.

FIG. 4A is a diagram illustrating a wafer in a state in which a high voltage NWELL & PWELL implant is performed in a high voltage device. In detail, after forming a zero oxide 110 on the silicon substrate 140, the high voltage N well implant 120 and the high voltage P well implant 130 are formed. It is a figure which shows the state which performed.

FIG. 4 (b) is a view showing a state when a wafer subjected to high voltage ion implantation (HNWELL & HPWELL Implant) is subjected to wafer cleaning according to the present invention. Pre-furnace cleaning refers to a step of performing SC-1 (Standard Clean-1) and a drying step. At this time, since the wafer cleaning (Pre Furnace Cleaning) does not go through the HF deposition step, the oxide film 112 remains. Therefore, even if the foreign matter 150 occurs due to a problem in the equipment part or a chemical problem, it is present on the oxide film 112 and does not directly contact the silicon substrate 140.

FIG. 4 (c) illustrates a defect in the form of a silicon cone pit even when the wafer of FIG. 4 b is subjected to a high temperature process such as annealing.

That is, according to the wafer cleaning method in the semiconductor process according to the present invention, foreign matter generated during wafer cleaning (Pre Furnace Cleaning) reacts with the silicon interface in a high temperature process of subsequent well annealing to form a silicon pit. In order to prevent the transition, the HF is not used in the pre-furnace cleaning process to leave a thin oxide layer and use the oxide layer to prevent the foreign matter and the silicon interface from reacting. In addition, the remaining oxide layer is then removed by pad oxide pre-furnace cleaning or buffer oxide etching.

The wafer cleaning method in the semiconductor process according to the present invention can be used in a conventional cleaning apparatus, but is most preferably applied in a total cleaning apparatus, especially a continuous multi-tank total cleaning apparatus. The total cleaning device refers to a cleaning device for batch processing a sequence. Continuous multimodality refers to a batch process that processes multiple wafers simultaneously.

As described above, according to the wafer cleaning method in the semiconductor process according to the present invention, the residual oxide film (Remain Oxide) is not carried out by performing HF deposition in the pre-furnace cleaning step after the high voltage ion implantation (HV NWELL & HV PWELL Implant). ) So that the surface of the wafer does not become a hydrophobic environment, thereby preventing the generation of foreign matters.

In addition, according to the present invention, by not performing HF deposition in the wafer cleaning process after the high voltage ion implantation, residual oxide film is retained so that foreign matters are separated from the silicon (Si) wafer interface in the high temperature process of subsequent well annealing. This prevents the reaction from transitioning to the form of silicon pits, which ultimately improves the yield and reliability of the semiconductor.

Claims (5)

Pre-furnace cleaning the HNWELL & HPWELL Implanted wafer so that a pad oxide layer remains; And And cleaning the pad oxide layer after well annealing the cleaned wafer (WELL Anneal). The method of claim 1, The wafer cleaning (Pre Furnace Cleaning) step SC-1 (Standard Clean-1) washing step at 75 ~ 85 ℃; And Drying the wafer (Pre Furnace Cleaning) the wafer (Dry); Wafer cleaning method in a semiconductor process comprising a. The method according to claim 1 or 2, The Pad Oxdeideide Pre Furnace Cleaning step SC-1 cleaning the wafer at 75-85 ° C .; Depositing fluorine (HF) at room temperature on the SC-1 cleaned wafer;  SC-2 (Standard Clean-2) at room temperature on the HF deposited wafer; And Drying the SC-2 cleaned wafer (Dry); Wafer cleaning method in a semiconductor process comprising a. The method of claim 3, wherein The HF deposition step is a wafer cleaning method in a semiconductor process, characterized in that 1800 ~ 2200 seconds at room temperature. The method of claim 3, wherein After the pad oxide layer cleaning, HF and NH ₄ F mixed in a predetermined ratio buffer oxide film (Buffer Oxide Etch); Wafer cleaning method further comprising a semiconductor process.

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