KR20110040102A - Semiconductor package - Google Patents

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KR20110040102A
KR20110040102A KR1020090097243A KR20090097243A KR20110040102A KR 20110040102 A KR20110040102 A KR 20110040102A KR 1020090097243 A KR1020090097243 A KR 1020090097243A KR 20090097243 A KR20090097243 A KR 20090097243A KR 20110040102 A KR20110040102 A KR 20110040102A
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South Korea
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semiconductor
semiconductor chip
semiconductor package
shielding layer
groove portion
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KR1020090097243A
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Korean (ko)
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조범상
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주식회사 하이닉스반도체
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Priority to KR1020090097243A priority Critical patent/KR20110040102A/en
Publication of KR20110040102A publication Critical patent/KR20110040102A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package is provided to efficiently shield electromagnetic noise by processing a shielding layer inserted into a substrate without the increase of the height of a semiconductor package. CONSTITUTION: A substrate(102) comprises a body(110), a first bond finger(122), a second bond finger(124), and a ball land(142). A first semiconductor chip(150a) is inserted within the second groove portion in the upper side of a substrate. A shielding layer(130) is inserted within the first groove portion on the substrate body including the first semiconductor chip. A second semiconductor chip(150b) is attached on the shielding layer. First and second connection members are connected to the ground terminal and the shielding layer and the second bond finger and the second semiconductor chip respectively.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor Package {SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 반도체 칩의 동작시 발생하는 전자기적 노이즈에 따른 성능 저하 문제를 개선한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that improves a performance degradation problem caused by electromagnetic noise generated during operation of a semiconductor chip.

반도체 산업에서 집적회로에 대한 패키징 기술은 소형화에 대한 요구 및 실장 신뢰성을 만족시키기 위해 지속적으로 발전하여 왔다. 예컨대, 소형화에 대한 요구는 칩 크기에 근접한 패키지에 대한 기술 개발을 가속화시키고 있으며, 실장 신뢰성에 대한 요구는 실장 작업의 효율성 및 실장 후의 기계적·전기적 신뢰성을 향상시킬 수 있는 패키징 기술에 대한 중요성을 부각시키고 있다.Packaging technology for integrated circuits in the semiconductor industry has been continuously developed to meet the demand for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technologies for packages that are close to chip size, and the demand for mounting reliability highlights the importance of packaging technologies that can improve the efficiency of mounting operations and mechanical and electrical reliability after mounting. I'm making it.

또한, 전기·전자 제품의 소형화와 더불어 고 성능화가 요구됨에 따라, 고용량의 반도체 패키지를 제공하기 위한 다양한 기술들이 연구 개발되고 있다. 고용량의 반도체 패키지를 제공하기 위한 방법으로서는 메모리 칩의 고집적화를 들 수 있으며, 이러한 고집적화는 한정된 반도체 칩의 공간 내에 보다 많은 수의 셀을 집적해 넣는 것에 의해 실현될 수 있다.In addition, as miniaturization of electric and electronic products and high performance are required, various technologies for providing a high capacity semiconductor package have been researched and developed. As a method for providing a high capacity semiconductor package, there is a high integration of the memory chip, which can be realized by integrating a larger number of cells in a limited space of the semiconductor chip.

그러나, 이러한 고집적화를 구현하기 위해 반도체 회로가 소형화 및 밀집화 되는 환경에서는 전자기적 노이즈 방해(elecromagnetic interference)에 의해 반도체 패키지의 동작 성능이 저하되는 문제가 발생하고 있다.However, in order to realize such high integration, an operation of a semiconductor package may be degraded due to electromagnetic interference in an environment in which semiconductor circuits are miniaturized and compact.

이러한 전자기적 노이즈 방해에 따른 반도체 패키지의 성능 저하를 방지하기 위해 반도체 패키지의 상면에 금속판을 부착하는 방법이 이용되고 있다. 메모리 반도체의 경우 반도체 패키지의 높이가 통상 1mm 내외이나, 전술한 구조로 반도체 패키지를 설계하다 보면, 반도체 패키지의 높이가 2배 이상으로 높아지는 문제가 있다.In order to prevent performance degradation of the semiconductor package due to the electromagnetic noise interference, a method of attaching a metal plate to the upper surface of the semiconductor package is used. In the case of a memory semiconductor, the height of the semiconductor package is usually about 1 mm, but when the semiconductor package is designed with the above-described structure, the height of the semiconductor package is twice or more.

일반적으로, 반도체 패키지의 구동시, 반도체 칩에서 방출되는 전자기적 노이즈가 금속판에 충돌했을 때 발생하는 현상으로는 1. 반사, 2. 투과, 3. 전류로 변환, 4. 열에너지로 변환되는 4가지로 요약될 수 있다.In general, four kinds of phenomena which occur when electromagnetic noise emitted from a semiconductor chip collides with a metal plate during driving of a semiconductor package are 1. reflection, 2. transmission, 3. conversion to current, and 4. conversion to thermal energy. It can be summarized as

이때, 반도체 칩에서 방출된 전자기적 노이즈가 전류로 변환되었을 때, 이를 외부로 접지시키지 않으면 차징(charging) 현상에 의해 전자기적 노이즈의 차폐 효과가 급격히 저하되나, 반도체 패키지의 상면에 금속판을 부착하는 구조에서는 외부에 접지시킬 방법이 없는 관계로 이를 해결하는 것이 무엇보다 시급한 상황이다.At this time, when the electromagnetic noise emitted from the semiconductor chip is converted into a current, the shielding effect of the electromagnetic noise is drastically lowered by the charging phenomenon unless the ground is externally grounded, but the metal plate is attached to the upper surface of the semiconductor package. In the structure, there is no way to ground the outside, so it is urgent to solve this problem.

본 발명은 반도체 패키지의 높이 증가 없이 전자기적 노이즈 방해에 따른 성능 저하 문제를 개선할 수 있는 반도체 패키지를 제공한다.The present invention provides a semiconductor package that can improve the performance degradation problem caused by electromagnetic noise interference without increasing the height of the semiconductor package.

또한, 본 발명은 이종 칩을 스택한 멀티 칩 패키지에 있어서, 이종 칩과 기판 간의 열팽창 계수 차이에 기인한 크랙 불량을 방지할 수 있는 반도체 패키지를 제공한다.In addition, the present invention provides a semiconductor package capable of preventing crack failure due to a difference in thermal expansion coefficient between a heterogeneous chip and a substrate in a multi-chip package in which heterogeneous chips are stacked.

본 발명의 실시예에 따른 반도체 패키지는 상면 및 하면과 상기 상면에 제1 크기를 갖는 제1 홈부 및 상기 제1 홈부 내측에 상기 제1 크기보다 작은 제2 크기를 갖는 제2 홈부를 구비한 몸체와, 상기 몸체의 제2 홈부 저면에 형성된 제1 본드핑거, 상기 제1 홈부 외측 주변에 형성된 제2 본드핑거와 접지단자, 및 상기 하면에 형성된 볼랜드를 포함한 회로패턴을 갖는 기판; 상기 기판 몸체 상면의 제2 홈부 내에 삽입된 제1 반도체 칩; 상기 제1 반도체 칩을 포함한 기판 몸체 상의 상기 제1 홈부 내에 삽입된 차폐층; 상기 차폐층 상에 부착된 적어도 하나 이상의 제2 반도체 칩; 및 상기 접지단자와 차폐층 사이, 및 상기 제2 본드핑거와 제2 반도체 칩 사이를 각각 연결하는 제1 연결부재 및 제2 연결부재를 포함하는 것을 특징으로 한다.A semiconductor package according to an embodiment of the present invention includes a body having a top surface and a bottom surface, a first groove portion having a first size on the top surface, and a second groove portion having a second size smaller than the first size inside the first groove portion. And a circuit pattern including a first bond finger formed on a bottom surface of the second groove portion of the body, a second bond finger formed on an outer periphery of the first groove portion, a ground terminal, and a ball land formed on the bottom surface thereof. A first semiconductor chip inserted in a second groove of the upper surface of the substrate body; A shielding layer inserted in the first groove on the substrate body including the first semiconductor chip; At least one second semiconductor chip attached to the shielding layer; And a first connection member and a second connection member connecting the ground terminal and the shielding layer and between the second bond finger and the second semiconductor chip, respectively.

상기 제1 및 제2 반도체 칩은 동종 칩인 것을 특징으로 한다.The first and second semiconductor chips may be of the same type.

상기 제1 및 제2 반도체 칩은 이종 칩인 것을 특징으로 한다.The first and second semiconductor chips may be heterogeneous chips.

상기 제1 홈부의 높이와 상기 차폐층의 두께는 대응하는 크기를 갖는 것을 특징으로 한다.The height of the first groove portion and the thickness of the shielding layer has a corresponding size.

상기 차폐층은 금, 은, 동, 철, 니켈, 크롬 및 이들 각각의 합금 중 어느 하나로 이루어진 것을 특징으로 한다.The shielding layer is characterized by consisting of any one of gold, silver, copper, iron, nickel, chromium and their respective alloys.

상기 기판과 제1 반도체 칩은 범프를 매개로 전기적으로 연결된 것을 특징으로 한다.The substrate and the first semiconductor chip may be electrically connected to each other via a bump.

상기 제1 및 제2 연결부재는 금속 와이어를 포함하는 것을 특징으로 한다.The first and second connection members may include metal wires.

상기 차폐층, 제2 반도체 칩, 제1 및 제2 연결부재를 포함한 기판 몸체의 상면을 밀봉하도록 형성된 봉지제를 더 포함하는 것을 특징으로 한다.And an encapsulant formed to seal an upper surface of the substrate body including the shielding layer, the second semiconductor chip, and the first and second connection members.

상기 제2 반도체 칩 상에 부착된 적어도 하나 이상의 제3 반도체 칩을 더 포함하는 것을 특징으로 한다.And at least one third semiconductor chip attached to the second semiconductor chip.

상기 제2 반도체 칩과 상기 제2 반도체 상에 부착된 상기 제3 반도체 칩들은 관통전극을 매개로 상호 간이 전기적으로 연결된 것을 특징으로 한다.The second semiconductor chip and the third semiconductor chips attached to the second semiconductor may be electrically connected to each other through a through electrode.

본 발명은 반도체 패키지의 높이 증가 없이, 기판 내에 삽입된 차폐층을 그라운드 처리하여 전자기적 노이즈를 효과적으로 차폐할 수 있다.The present invention can effectively shield electromagnetic noise by grounding the shielding layer inserted in the substrate without increasing the height of the semiconductor package.

또한, 본 발명은 이종 칩들을 스택함에 있어서, 오버행(overhang) 구조가 발생하더라도, 이종 칩들 사이에 배치된 차폐층을 지지 수단으로 활용하는 것을 통해 이종 칩들에 크랙이나 휨이 발생하는 것을 방지할 수 있다.In addition, in the stacking of heterogeneous chips, even if an overhang structure occurs, the use of a shielding layer disposed between the heterogeneous chips as a support means may prevent cracks or warpage of the heterogeneous chips. have.

(실시예)(Example)

이하, 본 발명의 바람직한 실시예에 따른 반도체 패키지에 대해 설명하도록 한다.Hereinafter, a semiconductor package according to an exemplary embodiment of the present invention will be described.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다. 도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 나타낸 단면도이다.1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention. 2 is a cross-sectional view illustrating a semiconductor package in accordance with another embodiment of the present invention.

도 1에 도시한 바와 같이, 제1 홈부(H1) 및 제2 홈부(H2)를 구비한 기 판(102)의 제2 홈부(H2) 내에 제1 반도체 칩(150a)이 삽입된다. 기판(102)은 상면(110a) 및 하면(110b)을 가지며, 상기 상면(110a)에 제1 크기를 갖는 제1 홈부(H1) 및 상기 제1 홈부(H1) 내측에 상기 제1 크기보다 작은 제2 크기를 갖는 제2 홈부(H2)를 포함한 몸체(110)를 구비한다.As illustrated in FIG. 1, the first semiconductor chip 150a is inserted into the second groove portion H2 of the substrate 102 having the first groove portion H1 and the second groove portion H2. The substrate 102 has an upper surface 110a and a lower surface 110b and is smaller than the first size inside the first groove portion H1 and the first groove portion H1 having a first size on the upper surface 110a. A body 110 including a second groove portion H2 having a second size is provided.

이에 더불어, 기판(102)은 몸체(110)의 제2 홈부(H2) 저면에 형성된 제1 본드핑거(122), 상기 제1 홈부(H2) 외측 주변에 형성된 제2 본드핑거(124)와 접지단자(126), 및 상기 하면(110b)에 형성된 볼랜드(142)를 포함한 회로패턴(도시안함)을 구비한다. 제1 반도체 칩(150a)은 기판 몸체(110)의 제2 홈부(H2) 저면 상에 플립 칩 본딩하는 것이 바람직하다.In addition, the substrate 102 may be grounded with a first bond finger 122 formed on the bottom surface of the second groove portion H2 of the body 110, and a second bond finger 124 formed around the outer side of the first groove portion H2. A circuit pattern (not shown) including a terminal 126 and a ball land 142 formed on the lower surface 110b is provided. The first semiconductor chip 150a may be flip chip bonded on the bottom surface of the second groove portion H2 of the substrate body 110.

즉, 제1 반도체 칩(150a)의 본딩패드(112)와 기판 몸체(110)의 제1 본드핑거(122) 간의 맞닿는 사이에 개재된 충진제(132) 및 접속부재(134)를 매개로 물리적 및 전기적으로 연결될 수 있다.That is, the filler 132 and the connection member 134 interposed between the bonding pad 112 of the first semiconductor chip 150a and the first bond finger 122 of the substrate body 110 may be physically connected to each other. Can be electrically connected.

충진제(132)는 일 예로 이방성 도전성 페이스트(anisotropy conductive paste: NCP)와 이방성 도전성 필름(anisotropy conductive film: NCF)을 포함할 수 있다. 접속부재(134)는 일 예로 범프를 포함할 수 있다.The filler 132 may include, for example, an anisotropy conductive paste (NCP) and an anisotropy conductive film (NCF). The connection member 134 may include bumps as an example.

또한, 제1 반도체 칩(150a)을 포함한 기판 몸체(110) 상의 제1 홈부(H1) 내에 차폐층(130)이 삽입된다. 제1 홈부(H1)의 높이와 차폐층(130)의 두께는 대응하는 크기를 가질 수 있다. 이와 다르게, 제1 홈부(H1)의 높이는 차폐층(130)의 두께보다 크거나, 또는 작은 크기를 가질 수 있다.In addition, the shielding layer 130 is inserted into the first groove H1 on the substrate body 110 including the first semiconductor chip 150a. The height of the first groove portion H1 and the thickness of the shielding layer 130 may have a corresponding size. Alternatively, the height of the first groove H1 may be greater than or smaller than the thickness of the shielding layer 130.

본 실시예에서는, 차폐층(130)과 제1 반도체 칩(150a)이 기판 몸체(110)의 제1 및 제2 홈부(H1, H2) 내에 각각 삽입되므로, 기판 몸체(110)의 두께에서 차폐층(130)과 제1 반도체 칩(150a)의 두께를 배제할 수 있다.In the present embodiment, since the shielding layer 130 and the first semiconductor chip 150a are inserted into the first and second grooves H1 and H2 of the substrate body 110, the shielding layer 130 and the first semiconductor chip 150a are shielded at the thickness of the substrate body 110. The thickness of the layer 130 and the first semiconductor chip 150a may be excluded.

한편, 차폐층(130) 상에는 적어도 하나 이상의 제2 반도체 칩(150b)이 부착된다. 도면으로 제시하지는 않았지만, 제1 반도체 칩(150a), 차폐층(130) 및 제2 반도체 칩(150b)은 각각의 맞닿는 사이 공간에 개재된 접착제(도시안함)를 매개로 물리적으로 각각 부착될 수 있다.Meanwhile, at least one second semiconductor chip 150b is attached to the shielding layer 130. Although not shown in the drawings, the first semiconductor chip 150a, the shielding layer 130, and the second semiconductor chip 150b may be physically attached to each other through an adhesive (not shown) interposed between the abutting spaces. have.

상기 차폐층(130)은 금(Au), 은(Ag), 구리(Cu), 철(Fe), 니켈(Ni), 크롬(Cr) 및 이들 각각의 합금 중 어느 하나로 이루어질 수 있다. 특히, 차폐층(130)은 전착이 쉬운 저탄소강 또는 니켈-철 합금으로 형성하는 것이 바람직하다.The shielding layer 130 may be made of any one of gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), chromium (Cr), and their respective alloys. In particular, the shielding layer 130 is preferably formed of a low carbon steel or nickel-iron alloy that is easy to electrodeposit.

상기 차폐층(130)은 기판 몸체(110)의 제1 홈부(H1) 내에 삽입하는 것이 바람직하다. 이와 다르게, 도면으로 제시하지는 않았지만, 차폐층(130)은 기판 몸체(110)의 상면(110a) 상에 부착될 수 있다.The shielding layer 130 is preferably inserted into the first groove portion H1 of the substrate body 110. Alternatively, although not shown in the drawings, the shielding layer 130 may be attached on the top surface 110a of the substrate body 110.

접지단자(126)와 차폐층(130)은 각각의 사이에 배치된 제1 연결부재(116)를 매개로 전기적으로 연결된다. 또한, 기판 몸체(110)의 제2 본드핑거(124)와 제2 반도체 칩(150b)의 본딩패드(112)는 각각의 사이에 배치된 제2 연결부재(118)를 매개로 전기적으로 연결된다. 제1 연결부재(116) 및 제2 연결부재(118)는 일 예로 금속 와이어를 포함할 수 있다.The ground terminal 126 and the shielding layer 130 are electrically connected to each other through the first connection member 116 disposed therebetween. In addition, the second bond fingers 124 of the substrate body 110 and the bonding pads 112 of the second semiconductor chip 150b are electrically connected to each other via second connection members 118 disposed therebetween. . The first connection member 116 and the second connection member 118 may include, for example, metal wires.

제1 반도체 칩(150a)과 제2 반도체 칩(150b)은 상이한 크기를 가질 수 있다. 이때, 상기 제1 반도체 칩(150a)은 제2 반도체 칩(150b)보다 작은 크기를 가질 수 있다. 또한, 상기 제1 반도체 칩(150a)과 제2 반도체 칩(150b)은 동종 칩일 수 있 다. 이와 다르게, 제1 반도체 칩(150a)과 제2 반도체 칩(150b)은 이종 칩일 수 있다.The first semiconductor chip 150a and the second semiconductor chip 150b may have different sizes. In this case, the first semiconductor chip 150a may have a smaller size than the second semiconductor chip 150b. In addition, the first semiconductor chip 150a and the second semiconductor chip 150b may be the same type of chip. Alternatively, the first semiconductor chip 150a and the second semiconductor chip 150b may be heterogeneous chips.

한편, 상기 차폐층(130), 제2 반도체 칩(150b), 제1 및 제2 연결부재(116, 118)를 포함한 기판 몸체(110)의 상면(110a)을 밀봉하도록 형성된 봉지제(170)를 더 포함할 수 있다. 봉지제(170)는 일 예로 EMC(Epoxy Molding Compound)를 포함할 수 있다.Meanwhile, the encapsulant 170 formed to seal the top surface 110a of the substrate body 110 including the shielding layer 130, the second semiconductor chip 150b, and the first and second connection members 116 and 118. It may further include. The encapsulant 170 may include, for example, an epoxy molding compound (EMC).

또한, 기판 몸체(110) 하면(110b)의 볼랜드(142)에 부착된 외부접속단자(144)를 더 포함할 수 있다. 외부접속단자(144)는 일 예로 솔더볼을 포함할 수 있다. 이때, 외부접속단자(144)들 중 적어도 하나 이상의 외부접속단자(144)는 접지단자(126)에 접지 처리된다.In addition, the substrate body 110 may further include an external connection terminal 144 attached to the ball land 142 of the lower surface (110b). The external connection terminal 144 may include solder balls as an example. In this case, at least one or more external connection terminals 144 of the external connection terminals 144 are grounded to the ground terminal 126.

전술한 구성은 제1 반도체 칩(150a) 및 차폐층(130)이 기판 몸체(110) 내에 삽입되어 있어 반도체 패키지(105)의 두께 증가 없이 고용량의 반도체 패키지(105)를 제작할 수 있다.In the above-described configuration, since the first semiconductor chip 150a and the shielding layer 130 are inserted into the substrate body 110, the semiconductor package 105 having a high capacity may be manufactured without increasing the thickness of the semiconductor package 105.

또한, 반도체 패키지(105)의 동작시, 제1 및 제2 반도체 칩(150a, 150b)에서 방출된 전자기적 노이즈가 전류 및 열 에너지로 변환되더라도, 그라운드 처리된 차폐층(130)을 통해 반도체 패키지(105)의 외부로 손쉽게 방출시킬 수 있는 장점이 있다.In addition, during operation of the semiconductor package 105, even if the electromagnetic noise emitted from the first and second semiconductor chips 150a and 150b is converted into current and thermal energy, the semiconductor package is provided through the grounded shielding layer 130. There is an advantage that can be easily released to the outside of (105).

한편, 차폐층(130)은 반도체 패키지(105) 내의 기판 몸체(110)와 봉지제(170) 간의 열팽창 계수 차이가 발생하는 것을 완충하는 역할을 한다. 따라서, 차폐층(130)은 기판 몸체(110)와 봉지제(170) 간의 열팽창 계수 차이를 줄이는 완 충제의 기능을 하는바, 피로 균열의 발생을 막아 제1 및 제2 반도체 칩(150a, 150b)에 휨이 발생하는 것을 최소화할 수 있다.On the other hand, the shielding layer 130 serves to buffer the occurrence of the difference in thermal expansion coefficient between the substrate body 110 and the encapsulant 170 in the semiconductor package 105. Accordingly, the shielding layer 130 functions as a buffer to reduce the difference in thermal expansion coefficient between the substrate body 110 and the encapsulant 170. The shielding layer 130 prevents the occurrence of fatigue cracks, thereby preventing the occurrence of the first and second semiconductor chips 150a and 150b. The warpage can be minimized.

나아가, 이종 칩으로 이루어진 제1 및 제2 반도체 칩(150a, 150b)들을 스택함에 있어서, 제1 반도체 칩(150a)의 크기가 제2 반도체 칩(150b)의 크기 보다 작은 오버행(overhang) 구조로 이루어지더라도, 제1 반도체 칩(150a)과 제2 반도체 칩(150b) 사이에 배치된 차폐층(130)을 지지 수단으로 사용할 수 있어 제2 반도체 칩(150b)에 크랙이 발생하는 것을 방지할 수 있다.Furthermore, in stacking the first and second semiconductor chips 150a and 150b made of heterogeneous chips, the size of the first semiconductor chip 150a is smaller than that of the second semiconductor chip 150b. Even if it is made, the shielding layer 130 disposed between the first semiconductor chip 150a and the second semiconductor chip 150b can be used as a support means to prevent cracks in the second semiconductor chip 150b. Can be.

한편, 도 2에 도시한 본 발명의 다른 실시예에 따른 반도체 패키지와 같이, 제2 반도체 칩(150b) 상에 적어도 하나 이상의 제3 반도체 칩(150c)을 더 부착할 수 있다.On the other hand, like the semiconductor package according to another embodiment of the present invention shown in FIG. 2, at least one third semiconductor chip 150c may be further attached on the second semiconductor chip 150b.

제2 반도체 칩(150b)과 상기 제2 반도체 칩(150b) 상에 부착된 제3 반도체 칩들은 관통전극(154)과 솔더(154)를 매개로 상호 간이 전기적으로 연결될 수 있다. 이와 다르게, 제3 반도체 칩(150c)들은 전도성 연결부재(도시안함)를 매개로 전기적으로 연결할 수도 있다. 전도성 연결부재는 범프 또는 금속 와이어일 수 있다.The second semiconductor chip 150b and the third semiconductor chips attached to the second semiconductor chip 150b may be electrically connected to each other through the through electrode 154 and the solder 154. Alternatively, the third semiconductor chips 150c may be electrically connected through a conductive connection member (not shown). The conductive connecting member may be a bump or a metal wire.

따라서, 본 발명의 다른 실시예에 따른 반도체 패키지는 제2 반도체 칩과 제2 반도체 칩들 상에 스택된 제3 반도체 칩들 상호 간을 관통전극 및 범프를 매개로 전기적으로 연결하는 것을 통해 전기적 연결 경로가 짧아져 고속 동작을 구현하는 데 적극적으로 대응할 수 있다.Therefore, the semiconductor package according to another embodiment of the present invention has an electrical connection path through the electrical connection between the second semiconductor chip and the third semiconductor chips stacked on the second semiconductor chips through the through electrode and the bump. It is shortened to actively respond to high speed operation.

이상, 전술한 본 발명의 실시예에서는 특정 실시예에 관련하여 도시하고 설 명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiment of the present invention, although shown and described with respect to a specific embodiment, the present invention is not limited thereto, and the scope of the claims below do not depart from the spirit and field of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도.1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 나타낸 단면도.2 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention.

Claims (10)

상면 및 하면과 상기 상면에 제1 크기를 갖는 제1 홈부 및 상기 제1 홈부 내측에 상기 제1 크기보다 작은 제2 크기를 갖는 제2 홈부를 구비한 몸체와, 상기 몸체의 제2 홈부 저면에 형성된 제1 본드핑거, 상기 제1 홈부 외측 주변에 형성된 제2 본드핑거와 접지단자, 및 상기 하면에 형성된 볼랜드를 포함한 회로패턴을 갖는 기판;A body having an upper surface and a lower surface and a first groove portion having a first size on the upper surface and a second groove portion having a second size smaller than the first size inside the first groove portion, and on a bottom surface of the second groove portion of the body. A substrate having a circuit pattern including a first bond finger formed, a second bond finger formed around the outer side of the first groove and a ground terminal, and a ball land formed on the bottom surface; 상기 기판 몸체 상면의 제2 홈부 내에 삽입된 제1 반도체 칩;A first semiconductor chip inserted in a second groove of the upper surface of the substrate body; 상기 제1 반도체 칩을 포함한 기판 몸체 상의 상기 제1 홈부 내에 삽입된 차폐층;A shielding layer inserted in the first groove on the substrate body including the first semiconductor chip; 상기 차폐층 상에 부착된 적어도 하나 이상의 제2 반도체 칩; 및At least one second semiconductor chip attached to the shielding layer; And 상기 접지단자와 차폐층 사이, 및 상기 제2 본드핑거와 제2 반도체 칩 사이를 각각 연결하는 제1 연결부재 및 제2 연결부재;First and second connection members connecting the ground terminal and the shielding layer and between the second bond finger and the second semiconductor chip, respectively; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서, 상기 제1 및 제2 반도체 칩은 동종 칩인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the first and second semiconductor chips are homogeneous chips. 제 1 항에 있어서, 상기 제1 및 제2 반도체 칩은 이종 칩인 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the first and second semiconductor chips are heterogeneous chips. 제 1 항에 있어서, 상기 제1 홈부의 높이와 상기 차폐층의 두께는 대응하는 크기를 갖는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein a height of the first groove and a thickness of the shielding layer have a corresponding size. 제 1 항에 있어서, 상기 차폐층은 금, 은, 동, 철, 니켈, 크롬 및 이들 각각의 합금 중 어느 하나로 이루어진 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the shielding layer is made of gold, silver, copper, iron, nickel, chromium, or an alloy thereof. 제 1 항에 있어서, 상기 기판과 제1 반도체 칩은 범프를 매개로 전기적으로 연결된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the substrate and the first semiconductor chip are electrically connected to each other via a bump. 제 1 항에 있어서, 상기 제1 및 제2 연결부재는 금속 와이어를 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, wherein the first and second connection members comprise metal wires. 제 1 항에 있어서, 상기 차폐층, 제2 반도체 칩, 제1 및 제2 연결부재를 포함한 기판 몸체의 상면을 밀봉하도록 형성된 봉지제를 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, further comprising an encapsulant formed to seal an upper surface of the substrate body including the shielding layer, the second semiconductor chip, and the first and second connection members. 제 1 항에 있어서, 상기 제2 반도체 칩 상에 부착된 적어도 하나 이상의 제3 반도체 칩을 더 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 1, further comprising at least one third semiconductor chip attached to the second semiconductor chip. 제 9 항에 있어서, 상기 제2 반도체 칩과 상기 제2 반도체 상에 부착된 상기 제3 반도체 칩들은 관통전극을 매개로 상호 간이 전기적으로 연결된 것을 특징으로 하는 반도체 패키지.The semiconductor package of claim 9, wherein the second semiconductor chip and the third semiconductor chips attached to the second semiconductor are electrically connected to each other through a through electrode.
KR1020090097243A 2009-10-13 2009-10-13 Semiconductor package KR20110040102A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9390992B2 (en) 2013-07-11 2016-07-12 Samsung Electronics Co., Ltd. Semiconductor packages including a metal layer between first and second semiconductor chips
CN110610925A (en) * 2019-09-17 2019-12-24 苏州日月新半导体有限公司 Integrated circuit package and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9390992B2 (en) 2013-07-11 2016-07-12 Samsung Electronics Co., Ltd. Semiconductor packages including a metal layer between first and second semiconductor chips
CN110610925A (en) * 2019-09-17 2019-12-24 苏州日月新半导体有限公司 Integrated circuit package and method of manufacturing the same

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