CN110610925A - Integrated circuit package and method of manufacturing the same - Google Patents
Integrated circuit package and method of manufacturing the same Download PDFInfo
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- CN110610925A CN110610925A CN201910875910.7A CN201910875910A CN110610925A CN 110610925 A CN110610925 A CN 110610925A CN 201910875910 A CN201910875910 A CN 201910875910A CN 110610925 A CN110610925 A CN 110610925A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000853 adhesive Substances 0.000 claims description 31
- 230000001070 adhesive effect Effects 0.000 claims description 31
- 239000003292 glue Substances 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 21
- 239000000463 material Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 239000012790 adhesive layer Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Embodiments of the present disclosure relate to integrated circuit packages and methods of fabricating the same. An integrated circuit package according to an embodiment includes a package substrate and a first chip module. The package substrate is provided with: the circuit board comprises a first group of pins and at least one grounding metal unit positioned on the periphery of the first group of pins. The first chip module is arranged on the packaging substrate and comprises: a first chip configured to electrically connect with a first set of pins; and an electromagnetic shield covering the first chip and configured to be connected with the grounding metal unit. The integrated circuit package and the manufacturing method thereof provided by the embodiment of the application can avoid electromagnetic interference among chips in a system-in-package structure by simple processes and technologies.
Description
Technical Field
Embodiments of the present disclosure relate to the field of semiconductor packaging, and more particularly, to an integrated circuit package and a method for manufacturing the same.
Background
In order to meet the demand for miniaturization of electronic products, System In a Package (SIP) technology is increasingly used. In a system-in-package, a plurality of chips having different functions need to be integrated in one package. A more common example is that more and more wireless communication devices have been highly integrated into a handset with a limited volume, such that different functional chips originally packaged separately are integrated into the same package. The chips integrated in a package may have the same or different operating frequencies, and harmonic signal interference may occur between the chips having the same or different operating frequencies, thereby affecting the performance of the chips, particularly chips sensitive to electromagnetic interference therein.
There are still a lot of technical problems to be solved in the industry for avoiding the generation of electromagnetic interference between chips in the system-in-package.
Disclosure of Invention
It is an object of the present invention to provide an integrated circuit package and a method for manufacturing the same, which can avoid electromagnetic interference between chips in a system-in-package structure with simple processes.
An embodiment of the present application provides an integrated circuit package including a package substrate and a first chip module. The package substrate is provided with: the circuit board comprises a first group of pins and at least one grounding metal unit positioned on the periphery of the first group of pins. The first chip module is arranged on the packaging substrate and comprises: a first chip configured to electrically connect with a first set of pins; and an electromagnetic shield covering the first chip and configured to be connected with the grounding metal unit.
In another embodiment of the present application, a groove is disposed on an upper surface of the package substrate, and the first group of leads and the first chip module are disposed in the groove. In another embodiment of the present application, the integrated circuit package further includes at least one first conductive element disposed around the first group of leads and surrounding at least two opposite sides of the first chip; the electromagnetic shielding element is arranged on the at least one first conductive element and is configured to be electrically connected with the at least one metal grounding unit through the at least one first conductive element. In another embodiment of the present application, the first conductive elements are metal bumps, and a distance between adjacent metal bumps is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation. In a further embodiment of the present application, the first conductive element is a metal strip having a length smaller than a wavelength of an electromagnetic wave generated by the first chip in operation. In another embodiment of the present application, the first conductive element is a surface mount element. The distance between adjacent surface mounting elements is smaller than the wavelength of the electromagnetic wave generated by the first chip during operation, or the length of the surface mounting element is smaller than the wavelength of the electromagnetic wave generated by the first chip during operation. In yet another embodiment of the present application, the height of the first conductive element is configured such that the electromagnetic shield contacts the top surface of the first chip when the electromagnetic shield is placed on the first conductive element. In another embodiment of the present application, the electromagnetic shield is a conductive film layer or a conductive glue layer. In another embodiment of the present application, the electromagnetic shield is a second chip or a metal cover plate, and a conductive adhesive is disposed between the second chip and the top surface of the first chip and the metal cover plate. In another embodiment of the present application, the first chip is disposed on the upper surface of the package substrate, the first chip is a flip chip, and a conductive adhesive is disposed between the electromagnetic shielding element and the top surface of the first chip.
Another embodiment of the present application provides a method of manufacturing an integrated circuit package, comprising: providing a package substrate and disposing a first chip module on the package substrate. The package substrate is provided with: the first group of pins and at least one grounding metal unit positioned on the periphery of the first group of pins. The first chip module includes: a first chip configured to electrically connect with a first set of pins; and an electromagnetic shield covering the first chip and configured to be connected with the grounding metal unit.
The integrated circuit package and the manufacturing method thereof provided by the embodiment of the application can form a good grounding shielding effect around the chip in the integrated circuit package, especially around the chip sensitive to electromagnetism, and prevent the electromagnetic interference generated between the chips in the integrated circuit package and the electromagnetic interference outside the integrated circuit package. In addition, the integrated circuit package and the manufacturing method thereof provided by the embodiment of the application have the advantages of simple manufacturing process, high production efficiency and the like.
Drawings
FIG. 1 is a schematic diagram of a longitudinal cross-section of an integrated circuit package according to an embodiment of the present application
FIGS. 2a-2e are schematic flow diagrams illustrating a process for fabricating an integrated circuit package according to an embodiment of the present application, which can fabricate the integrated circuit package shown in FIG. 1
FIG. 3 is a schematic diagram of a longitudinal cross-section of an integrated circuit package according to another embodiment of the present application
FIG. 4 is a schematic diagram of a longitudinal cross-section of an integrated circuit package according to yet another embodiment of the present application
FIGS. 5a-5c are schematic flow diagrams illustrating the fabrication of an integrated circuit package according to another embodiment of the present application, which can fabricate the integrated circuit package of FIG. 4
FIG. 6 is a schematic diagram of a longitudinal cross-section of an integrated circuit package according to another embodiment of the present application
Detailed Description
In order to better understand the spirit of the embodiments of the present application, the following further description is given in conjunction with some preferred embodiments of the present application.
Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the embodiments of the present application be constructed or operated in a particular orientation.
As used herein, the terms "about," "substantially," and "approximately" are used to describe and illustrate minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the stated numerical value, such as less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%. For example, two numerical values are "substantially" identical and "similar" if the difference between the two numerical values is less than or equal to ± 10% (e.g., less than or equal to ± 5%, less than or equal to ± 4%, less than or equal to ± 3%, less than or equal to ± 2%, less than or equal to ± 1%, less than or equal to ± 0.5%, less than or equal to ± 0.1%, or less than or equal to ± 0.05%) of the mean of the values.
Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.
In the embodiments of the present application, unless otherwise specified or limited, the terms "disposed," "connected," "coupled," "fixed," and the like are used broadly, and those skilled in the art can understand that the terms may be, for example, fixed, detachable, or integrated according to specific situations; it may also be mechanically or electrically connected; it may also be a direct link or an indirect link through an intermediary structure; or may be an internal communication of the two components.
Fig. 1 is a schematic longitudinal cross-sectional view of an integrated circuit package 100 according to an embodiment of the present application.
As shown in fig. 1, an integrated circuit package 100 according to an embodiment of the present application may include: package substrate 10, first chip module 12 and insulating housing 14.
The package substrate 10 has an upper surface 101 and a lower surface 103 opposite the upper surface 101. The upper surface 101 is provided with a first set of leads 105 and a second set of leads 107. The first set of pins 105 may include signal pins and/or ground pins. According to some embodiments of the present disclosure, the first group of leads 105 may be disposed in a recess 109 of the package substrate 10, and the recess 109 is recessed from the upper surface 101 toward the lower surface 103 by a certain depth. The depth of the recess 109 and the number of leads 105 of the first group may depend on the actual conditions of the first chip module 12. The lower surface 103 may be provided with one or more leads (not shown) as desired. The package substrate 10 may also be provided with a grounding metal unit 111 located at the periphery of the first group of leads 105. The grounding metal unit 111 is disposed on the upper surface 101 of the package substrate 10 around the edge of the recess 109. The material of the grounding metal unit 111 is any suitable conductive material.
The first chip module 12 is disposed on the package substrate 10. The first chip module 12 may include a first chip 121 and an electromagnetic shield 123. The first chip 121 is disposed in the groove 109 of the upper surface 101 of the package substrate 10. According to some embodiments of the present application, the first chip 121 may be a flip chip configured to be electrically connected with the first set of leads 105 through the metal balls 121a thereon by a flip chip process. The electromagnetic shield 123 covers the first chip 121 and is configured to be connected with the grounding metal unit 111. According to some embodiments of the present application, the electromagnetic shield 123 is a second chip. A conductive adhesive 125 may be disposed between the electromagnetic shield 123 and the top surface 121b of the first chip 121, so that the second chip may be electrically connected to the grounding metal unit 111 through the conductive adhesive 125. The thickness of the conductive adhesive 125 can be set according to actual needs, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, about 100 microns, etc. The electromagnetic shield 123 is connected to the second set of leads 107 by leads 16.
The first chip 121 according to the embodiment of the present application may be any type of chip, such as, but not limited to, a sensitive element such as a low noise amplifier. The electromagnetic shield 123 may also be any type of chip such as, but not limited to, a power amplifier chip or a chip with transmit and receive functions.
The insulating case 14 covers at least the upper surface 101 of the package substrate 10, the first chip module 12, and the leads 16. The material of the insulating housing 14 is a material of an insulating housing commonly known in the art.
In some embodiments of the present application, the integrated circuit package 100 may further include a shielding metal layer (not shown) shielding at least the upper surface 141a and at least a portion of the sidewall 141b of the insulating housing 14 or a shielding metal layer using other technical structures to better shield external electromagnetic interference.
Some embodiments of the present application illustrated in fig. 1 shield the first chip 121 in the integrated circuit package 100 by disposing the conductive adhesive 125 between the electromagnetic shield 123 and the top surface 121b of the first chip 121, such that the electromagnetic shield 123 is electrically connected to the grounding metal unit 111 via the conductive adhesive 125, thereby preventing the first chip 121 from being interfered by external signals.
Fig. 2a-2e are schematic flow diagrams illustrating the fabrication of an integrated circuit package 100 according to an embodiment of the present application, which can fabricate the integrated circuit package 100 shown in fig. 1.
As shown in fig. 2a, a package substrate 10 is provided, the package substrate 10 having an upper surface 101 and a lower surface 103 opposite to the upper surface 101. The upper surface 101 is provided with a first set of leads 105 and a second set of leads 107. The first set of pins 105 may include signal pins and/or ground pins. According to some embodiments of the present disclosure, the first group of leads 105 may be disposed in a recess 109 of the package substrate 10, and the recess 109 is recessed from the upper surface 101 toward the lower surface 103 by a certain depth. The depth of the recess 109 and the number of leads 105 of the first group may depend on the actual conditions of the first chip module 12. The lower surface 103 may be provided with one or more leads (not shown) as desired. The package substrate 10 may also be provided with a grounding metal unit 111 located at the periphery of the first group of leads 105. The grounding metal unit 111 is disposed on the upper surface 101 of the package substrate 10 around the edge of the recess 109. The material of the grounding metal unit 111 is any suitable conductive material.
As shown in fig. 2b to 2d, the first chip module 12 is disposed on the package substrate 10. The first chip module 12 may include a first chip 121 and an electromagnetic shield 123.
The first chip 121 is disposed in the recess 109 of the upper surface 101 of the package substrate 10. According to some embodiments of the present disclosure, the first chip 121 may be a flip chip, and the first chip 121 may be electrically connected to the first group of leads 105 through the metal balls 121a thereon by using a flip chip process.
Next, the electromagnetic shield 123 is disposed to cover the first chip 121 and configured to be connected with the grounding metal unit 111. According to some embodiments of the present application, the electromagnetic shield 123 is a second chip, and a conductive adhesive 125 (not shown in fig. 2b to 2 d) may be disposed between the second chip and the top surface 121b of the first chip 121, so that the second chip is electrically connected to the grounding metal unit 111 through the conductive adhesive 125. The conductive adhesive 125 may be previously coated on the top surface 121b of the first chip 121, or the conductive adhesive 125 may be coated on the lower surface 123a of the electromagnetic shield 123. The thickness of the conductive adhesive 125 can be set according to actual needs, and can be, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, or about 100 microns. According to the embodiment of the present application, the first chip 121 may be any type of chip, such as, but not limited to, a sensitive element such as a low noise amplifier. According to embodiments of the application, the second chip may be any type of chip, such as, but not limited to, a power amplifier chip or a chip with transmit and receive functionality.
As shown in fig. 2e, the second chip is electrically connected to the second set of leads 107 through leads 16 by a conventional wire bonding process.
The insulative housing 14 is then formed by conventional injection molding to cover at least the top surface 101 of the package substrate 10, the first chip module 12 and the leads 16. The material of the insulating housing 14 is a material of an insulating housing commonly known in the art.
In some embodiments of the present application, a shielding metal layer (not shown) or a shielding metal layer using other technical structures may be further disposed to shield at least the upper surface 141a and at least a portion of the sidewall 141b of the insulating housing 14 for better shielding external electromagnetic interference.
Some embodiments of the present application illustrated in fig. 2a-2e are provided with the conductive adhesive 125 between the electromagnetic shield 123 and the top surface 121b of the first chip 121, so that the electromagnetic shield 123 is electrically connected to the grounding metal unit 111 through the conductive adhesive 125 to shield the first chip 121 in the integrated circuit package 100, thereby preventing the first chip 121 from being interfered by external signals, and having advantages of simple manufacturing process, low manufacturing cost, high production efficiency, and the like.
Fig. 3 is a schematic longitudinal cross-sectional view of an integrated circuit package 200 according to another embodiment of the present application. As shown in fig. 3, the integrated circuit package 200 shown in fig. 3 differs from the integrated circuit package 100 shown in fig. 1 in that: the electromagnetic shield 223 of the integrated circuit package 200 is a metal cover plate, and the insulating housing 14 at least shields the upper surface 101 of the package substrate 10 and the first chip module 12.
According to some embodiments of the present application, the electromagnetic shield 223 may be a conductive film layer or a conductive adhesive layer. After the first chip 121 is disposed on the package substrate 10, a conductive film layer or a conductive adhesive layer is disposed on the top surface 121b of the first chip 121. The thickness of the conductive film layer or the conductive glue layer can be set according to actual needs, and can be, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, about 100 microns, or the like.
Some embodiments of the present application illustrated in fig. 3 electrically connect the metal cover to the grounding metal unit 111 through the conductive adhesive 125 by disposing the conductive adhesive 125 between the electromagnetic shield 223 and the top surface 121b of the first chip 121, or electrically connect the metal cover to the grounding metal unit 111 through a conductive film layer or a conductive adhesive layer, so as to shield the first chip 121 in the integrated circuit package 100, thereby preventing the first chip 121 from being interfered by external signals.
Fig. 4 is a schematic diagram of a longitudinal cross-section of an integrated circuit package 300 according to yet another embodiment of the present application. As shown in fig. 4, an integrated circuit package 300 according to yet another embodiment of the present application includes: a package substrate 30, a first chip module 32 and an insulating housing 34.
The package substrate 30 has an upper surface 301 and a lower surface 303 opposite the upper surface 301. The upper surface 301 is provided with a first set of leads 305 and a second set of leads 307. The first set of pins 305 may include signal pins and/or ground pins. The lower surface 303 may be provided with one or more leads (not shown) as desired. The package substrate 30 may also be provided with a grounding metal unit 309 located at the periphery of the first group of pins 305. The material of the grounded metal unit 309 is any suitable conductive material.
The first chip module 32 is disposed on the package substrate 30. The first chip module 32 may include a first chip 321 and an electromagnetic shield 323. The first chip 321 is disposed on the upper surface 301 of the package substrate 30. According to some embodiments of the present application, the first chip 321 is a flip chip configured to be electrically connected to the first set of leads 305 through the metal balls 321a thereon by a flip chip process. The electromagnetic shield 323 covers the first chip 321 and is configured to be connected with the grounding metal unit 309. According to some embodiments of the present application, the electromagnetic shield 323 is a second chip, a conductive adhesive 325 may be disposed between the electromagnetic shield 123 and the top surface 321b of the first chip 321, and the electromagnetic shield 123 may be configured to be electrically connected to the ground metal unit 309 through the conductive adhesive 325. The thickness of the conductive paste 325 can be set as desired, and can be, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, or about 100 microns. The second chip may be connected to the second set of pins 307 by wires 36.
The first chip 321 according to the embodiment of the present application may be any type of chip, such as, but not limited to, a sensitive element such as a low noise amplifier. The electromagnetic shield 323 may also be any type of chip such as, but not limited to, a power amplifier chip or a chip with transmit and receive capabilities.
The integrated circuit package 300 further includes a first conductive element 327 disposed around the first group of leads 305 and surrounding two opposite sides of the first chip 321. According to some embodiments of the present application, the first conductive element 327 surrounds three or four sides of the first chip 321. The electromagnetic shield 323 can be disposed on the first conductive element 327 through the conductive adhesive 325, and is configured to be electrically connected to the ground metal unit 309 through the conductive adhesive 325 and the first conductive element 327. According to some embodiments of the present disclosure, the first conductive element 327 is a metal bump, and a distance between adjacent metal bumps is smaller than a wavelength of an electromagnetic wave generated by the first chip 321 during operation so as to shield a signal that may interfere with the first chip 321. According to some embodiments of the present application, the first conductive element 327 is a metal strip, and the length of the metal strip is smaller than the wavelength of the electromagnetic wave generated by the first chip 321 during operation so as to shield the signal that may interfere with the first chip 321. According to some embodiments of the present application, the first conductive element 327 is a surface mount element. According to some embodiments of the present application, a distance between adjacent surface mount components is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation. According to some embodiments of the present application, the length of the surface mount component is smaller than the wavelength of the electromagnetic wave generated by the first chip during operation. For example, when a surface mount device is disposed on one side of the first chip 321, the length of the surface mount device is smaller than the wavelength of the electromagnetic wave generated by the first chip 321 during operation, so as to shield signals that may interfere with the first chip 321. When two or more surface mount devices are disposed on one side of the first chip 321, the distance between adjacent surface mount devices is smaller than the wavelength of electromagnetic waves generated by the first chip 321 during operation so as to shield signals that may interfere with the first chip 321. The height of the first conductive element 327 is configured such that when the electromagnetic shield 323 is placed on the first conductive element 321, the electromagnetic shield 323 contacts the top surface 321a of the first chip 321, such that the electromagnetic shield 323 is electrically connected with the metal ground unit 309 via the at least one first conductive element 327.
The insulating case 34 covers at least the upper surface 301 of the package substrate 30, the first chip module 32, and the leads 36. The material of the insulating housing 34 is common in the art.
According to some embodiments of the present disclosure, the integrated circuit package 300 may further include a shielding metal layer (not shown) shielding at least the upper surface 341a and at least a portion of the sidewall 341b of the insulating housing 34 or a shielding metal layer using other technical structures to better shield external electromagnetic interference.
Some embodiments of the present application, as illustrated in fig. 4, shield the first chip 321 in the integrated circuit package 300 by disposing the conductive adhesive 325 between the electromagnetic shield 323 and the top surface 121b of the first chip 121, and electrically connecting the electromagnetic shield 323 with the ground metal unit 309 via the conductive adhesive 325 and the first conductive element 327, so as to prevent the first chip 321 from being interfered by external signals.
Fig. 5a-5c are schematic flow diagrams illustrating the fabrication of an integrated circuit package 300 according to yet another embodiment of the present application, which can fabricate the integrated circuit package 300 shown in fig. 4.
As shown in fig. 5a, a package substrate 30 is provided. The package substrate 30 has an upper surface 301 and a lower surface 303 opposite the upper surface 301. The upper surface 301 is provided with a first set of leads 305 and a second set of leads 307. The first set of pins 305 may include signal pins and/or ground pins. The lower surface 303 may be provided with one or more leads (not shown) as desired. The package substrate 30 may also be provided with a grounding metal unit 309 located at the periphery of the first group of pins 305. The material of the grounded metal unit 309 is any suitable conductive material.
Next, a first conductive element 327 may be disposed around the first group of leads 305 and around two opposite sides of the first chip 321 by using a surface mount process or any other suitable process. According to some embodiments of the present application, the first conductive element 327 may be disposed to surround three or four sides of the first chip 321. According to some embodiments of the present disclosure, the first conductive element 327 is a metal bump, and a distance between adjacent metal bumps is smaller than a wavelength of an electromagnetic wave generated by the first chip 321 during operation so as to shield a signal that may interfere with the first chip 321. According to some embodiments of the present application, the first conductive element 327 is a metal strip, and the length of the metal strip is smaller than the wavelength of the electromagnetic wave generated by the first chip 321 during operation so as to shield the signal that may interfere with the first chip 321. According to some embodiments of the present application, the first conductive element 327 is a surface mount element. According to some embodiments of the present application, a distance between adjacent surface mount components is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation. According to some embodiments of the present application, the length of the surface mount component is smaller than the wavelength of the electromagnetic wave generated by the first chip during operation. For example, when a surface mount device is disposed on one side of the first chip 321, the length of the surface mount device is smaller than the wavelength of the electromagnetic wave generated by the first chip 321 during operation, so as to shield signals that may interfere with the first chip 321. When two or more surface mount devices are disposed on one side of the first chip 321, the distance between adjacent surface mount devices is smaller than the wavelength of electromagnetic waves generated by the first chip 321 during operation so as to shield signals that may interfere with the first chip 321. According to some embodiments of the present application, the first conductive element 327 is any suitable conductive material. The height of the first conductive element 327 is configured such that when the electromagnetic shield 323 is placed on the first conductive element 321, the electromagnetic shield 323 contacts the top surface 321a of the first chip 321, such that the electromagnetic shield 323 is electrically connected with the metal ground unit 309 via the at least one first conductive element 327.
As shown in fig. 5b, the first chip module 32 is disposed on the package substrate 30. The first chip module 32 may include a first chip 321 and an electromagnetic shield 323.
The first chip 321 is disposed on the upper surface 301 of the package substrate 30. According to some embodiments of the present application, the first chip 321 is a flip chip, and the first chip 321 is electrically connected to the first group of leads 305 through the metal balls 321a thereon by using a flip chip process.
Next, an electromagnetic shield 323 is disposed to cover the first chip 321 and configured to be connected with the grounding metal unit 309. According to some embodiments of the present application, the electromagnetic shield 323 is a second chip, and a conductive adhesive 325 (not shown in fig. 5b and 5 c) may be disposed between the second chip and the top surface 321b of the first chip 321, so that the electromagnetic shield 323 is electrically connected to the ground metal unit 309 through the conductive adhesive 325. The conductive paste 325 may be previously coated on the top surface 321b of the first chip 321, or the conductive paste 325 may be coated on the lower surface 323a of the electromagnetic shield 323. The thickness of the conductive paste 325 can be set as desired, and can be, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, or about 100 microns. The second chip is connected to a second set of leads 307 by leads 36.
The first chip 321 according to the embodiment of the present application may be any type of chip, such as, but not limited to, a sensitive element such as a low noise amplifier. The electromagnetic shield 323 may also be any type of chip such as, but not limited to, a power amplifier chip or a chip with transmit and receive capabilities.
As shown in fig. 5c, the second chip is electrically connected to the second set of leads 307 through wires 36 by a conventional wire bonding process.
Next, the insulating housing 34 is formed by conventional injection molding to cover at least the upper surface 301 of the package substrate 30, the first chip module 32 and the leads 36. The material of the insulating housing 34 is common in the art.
According to some embodiments of the present disclosure, a shielding metal layer (not shown) or a shielding metal layer using other technical structures may be further disposed to shield at least the upper surface 341a and at least a portion of the sidewall 341b of the insulating housing 34 for better shielding external electromagnetic interference.
Some embodiments of the present application illustrated in fig. 5a-5c are provided with the first conductive element 327, such that the electromagnetic shielding element 323 is electrically connected to the grounding metal unit 309 through the conductive adhesive 325 between the electromagnetic shielding element 323 and the top surface 321b of the chip 321, so as to shield the first chip 321 in the integrated circuit package 300 by a simple process, thereby preventing the first chip 321 from being interfered by external signals, and having advantages of simple manufacturing process, low manufacturing cost, high production efficiency, and the like.
Fig. 6 is a schematic longitudinal cross-sectional view of an integrated circuit package 400 according to yet another embodiment of the application. As shown in fig. 6, the integrated circuit package 400 shown in fig. 6 differs from the integrated circuit package 300 shown in fig. 4 in that: the electromagnetic shield 423 of the integrated circuit package 400 is a metal cover plate, and the insulating housing 34 at least shields the upper surface 301 of the package substrate 30 and the first chip module 32.
According to some embodiments of the present application, the electromagnetic shield 423 may be a conductive film layer or a conductive glue layer. After the first chip 321 is disposed on the package substrate 30, a conductive film layer or a conductive adhesive layer is disposed on the top surface 321b of the first chip 321. The thickness of the conductive film layer or the conductive glue layer can be set according to actual needs, and can be, for example, about 10 microns, about 20 microns, about 50 microns, about 75 microns, about 100 microns, or the like.
Some embodiments of the present application illustrated in fig. 6 electrically connect the metal cover to the grounding metal unit 309 through the conductive adhesive 325 by disposing the conductive adhesive 325 between the electromagnetic shielding member 423 and the top surface 321b of the first chip 321, or electrically connect the metal cover to the grounding metal unit 309 through the conductive film layer or the conductive adhesive layer, so as to shield the first chip 321 in the integrated circuit package 400, thereby preventing the first chip 321 from being interfered by external signals.
While the embodiments of the present application have been described in detail, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the embodiments of the present application. Therefore, the scope of the embodiments of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the embodiments of the present application, which are encompassed by the claims of the present application.
Claims (20)
1. An integrated circuit package, comprising:
a package substrate provided with:
a first group of pins; and
at least one grounding metal unit located at the periphery of the first group of pins; and
a first chip module disposed on the package substrate; the first chip module includes:
a first chip configured to electrically connect with the first set of pins; and
an electromagnetic shield covering the first chip and configured to be connected with the grounding metal unit.
2. The integrated circuit package of claim 1, wherein a recess is disposed on an upper surface of the package substrate, the first group of leads and the first chip module being disposed in the recess.
3. The integrated circuit package of claim 1, further comprising:
at least one first conductive element disposed around the first group of leads and surrounding at least two opposite sides of the first chip; the electromagnetic shield is disposed on the at least one first conductive element and is configured to be electrically connected with the at least one metal grounding unit through the at least one first conductive element.
4. The integrated circuit package of claim 3, wherein the first conductive elements are metal bumps, and a pitch between adjacent metal bumps is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation.
5. The integrated circuit package of claim 3, wherein the first conductive element is a metal strip having a length less than a wavelength of an electromagnetic wave generated by the first chip during operation.
6. The integrated circuit package as claimed in claim 3, wherein the first conductive elements are surface mount elements, wherein a distance between adjacent ones of the surface mount elements is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation, or a length of the surface mount elements is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation.
7. The integrated circuit package of claim 3, wherein a height of the first conductive element is configured such that the electromagnetic shield contacts a top surface of the first chip when the electromagnetic shield is placed on the first conductive element.
8. The integrated circuit package of claim 2 or 3, wherein the electromagnetic shield is a conductive film layer or a conductive glue layer.
9. The integrated circuit package of claim 2 or 3, wherein the electromagnetic shield is a second chip or a metal cover plate, and a conductive adhesive is disposed between the top surfaces of the first chip and the second chip and the metal cover plate.
10. The integrated circuit package of claim 1, wherein the first chip is disposed on the upper surface of the package substrate, the first chip is a flip chip, and a conductive adhesive is disposed between the electromagnetic shield and the top surface of the first chip.
11. A method of manufacturing an integrated circuit package, comprising:
providing a package substrate, the package substrate provided with:
a first group of pins; and
at least one grounding metal unit located at the periphery of the first group of pins; and
disposing the first chip module on the package substrate; the first chip module includes:
a first chip configured to electrically connect with the first set of pins; and
an electromagnetic shield covering the first chip and configured to be connected with the grounding metal unit.
12. The method as claimed in claim 11, wherein a recess is formed on the upper surface of the package substrate, the first group of leads and the first chip module are disposed in the recess, and the at least one grounding metal unit is disposed around the recess.
13. The method of manufacturing an integrated circuit package of claim 11, further comprising:
arranging at least one first conductive element on the periphery of the first group of pins and at least surrounding two opposite side edges of the first chip; and arranging the electromagnetic shielding piece on the at least one first conductive element so as to electrically connect the at least one first conductive element with the at least one metal grounding unit.
14. The method as claimed in claim 13, wherein the first conductive elements are metal bumps, and a distance between adjacent metal bumps is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation.
15. The method of claim 13, wherein the first conductive element is a metal strip having a length less than a wavelength of an electromagnetic wave generated by the first chip during operation.
16. The method as claimed in claim 13, wherein the first conductive elements are surface mount elements, and wherein a distance between adjacent surface mount elements is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation, or a length of the surface mount elements is smaller than a wavelength of an electromagnetic wave generated by the first chip during operation.
17. The method of manufacturing an integrated circuit package of claim 13, wherein a height of the first conductive element is configured such that the electromagnetic shield contacts a top surface of the first chip when the electromagnetic shield is placed on the first conductive element.
18. The method of manufacturing an integrated circuit package of claim 12 or 13, wherein the electromagnetic shield is a conductive film layer or a conductive glue layer.
19. The method of manufacturing an integrated circuit package according to claim 12 or 13, wherein the electromagnetic shield is a second chip or a metal cover plate, and a conductive adhesive is disposed between the top surfaces of the first chip and the second chip and the metal cover plate.
20. The method of claim 11, wherein the first chip is disposed on the top surface of the package substrate, the first chip is a flip chip, and a conductive adhesive is disposed between the electromagnetic shield and the top surface of the first chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910875910.7A CN110610925A (en) | 2019-09-17 | 2019-09-17 | Integrated circuit package and method of manufacturing the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910875910.7A CN110610925A (en) | 2019-09-17 | 2019-09-17 | Integrated circuit package and method of manufacturing the same |
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| CN110610925A true CN110610925A (en) | 2019-12-24 |
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Address after: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province Applicant after: Riyuexin semiconductor (Suzhou) Co.,Ltd. Address before: No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou, Jiangsu Province Applicant before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd. |