KR20110001693A - Mask for forming contact hole of semiconductor device and method for forming contact hole of semiconductor device - Google Patents

Mask for forming contact hole of semiconductor device and method for forming contact hole of semiconductor device Download PDF

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Publication number
KR20110001693A
KR20110001693A KR1020090059353A KR20090059353A KR20110001693A KR 20110001693 A KR20110001693 A KR 20110001693A KR 1020090059353 A KR1020090059353 A KR 1020090059353A KR 20090059353 A KR20090059353 A KR 20090059353A KR 20110001693 A KR20110001693 A KR 20110001693A
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KR
South Korea
Prior art keywords
pattern
contact hole
forming
photoresist
photoresist pattern
Prior art date
Application number
KR1020090059353A
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Korean (ko)
Inventor
복철규
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090059353A priority Critical patent/KR20110001693A/en
Publication of KR20110001693A publication Critical patent/KR20110001693A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70216—Mask projection systems
    • G03F7/70341—Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor

Abstract

The present invention relates to a mask for forming a contact hole and a method for forming a contact hole in a semiconductor device. In particular, by forming a contact hole pattern by crossing a plurality of line and space patterns, both the diameter and the pitch of the contact hole pattern can be reduced. In addition, the present invention relates to a mask for forming a contact hole and a method for forming a contact hole of a semiconductor device capable of improving the yield of the semiconductor device by improving the uniformity of the size of the contact hole pattern.

A method of forming a contact hole in a semiconductor device according to the present invention may include forming a first photosensitive film pattern of a line and space type; Forming a line and space type second photoresist pattern in a direction perpendicular to the first photoresist pattern; Forming a line and space type third photoresist pattern in parallel with the first photoresist pattern and positioned in a space between the first photoresist pattern; And forming a fourth photoresist pattern of a line-and-space type parallel to the first photoresist pattern and positioned in a space between the first photoresist pattern.

Description

Mask for forming contact hole and method for forming contact hole of semiconductor device {MASK FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING CONTACT HOLE OF SEMICONDUCTOR DEVICE}

The present invention relates to a mask for forming a contact hole and a method for forming a contact hole in a semiconductor device. More particularly, the present invention relates to a mask for forming a contact hole of a semiconductor device and a method for forming a contact hole for forming a contact hole in an etched layer in a semiconductor device.

The pitch of the minimum contact hole that can be formed by the conventional 1.35 NA ArF immersion lithography technique is about 100 nm, and is about 50 nm on the half-pitch basis.

In order to reduce the pitch of the contact hole, a resist flow process or a resolution enhancement resolution (RELACS) process has been conventionally applied.

1 and 2 are perspective views illustrating a conventional method for forming a semiconductor device contact hole. Referring to FIG. 1, a photosensitive film pattern 20 is formed on an etched layer 10 of a semiconductor device. The photoresist pattern 20 is used to form contact holes, and contact hole patterns 25 are formed at predetermined intervals so that the contact holes can be etched in the etched layer 10. In FIG. 1 the pitch of the minimum contact hole is represented by 'a', which is about 10 nm in ArF immersion lithography technique.

Thereafter, in order to reduce the diameter of the contact hole pattern 25, 1) a resist flow process is performed. Specifically, when the photoresist pattern 20 is baked at or above the glass transition temperature, the photoresist pattern 20 swells as if it is a steamed bread, as shown in FIG. The diameter of 25 decreases.

Or ② to perform a relaxation process, after the formation of the photosensitive film pattern 20 is coated with a relaxation material on the top of the photosensitive film pattern 20. When the photosensitive film pattern 20 coated with the relaxed material is baked, a new film is formed as the photoresist material and the relaxed material react as if a yellowed paper is formed, and the diameter of the contact hole pattern 25 as shown in FIG. 2. This decreases.

However, even when the resist flow process or the relaxation process is applied as described above, only the diameter of the contact hole pattern 25 can be reduced as shown in FIG. 2, and the pitch a between the contact hole patterns 25 can be reduced. It was difficult to reduce the overall size of the semiconductor chip.

The present invention is to solve the conventional problems as described above, by forming a contact hole pattern by crossing a plurality of line-and-space patterns other than the conventional photoresist pattern for forming a contact hole, the diameter and pitch of the contact hole pattern An object of the present invention is to provide a mask for forming a contact hole and a method for forming a contact hole of a semiconductor device, which can be reduced in all and improve the yield of the semiconductor device by improving the uniformity of the contact hole pattern size.

In order to achieve the above object, the present invention comprises the steps of forming a first photosensitive film pattern of the line and space type, forming a second photosensitive film pattern of the line and space type in a direction perpendicular to the first photosensitive film pattern, Forming a line and space type third photoresist pattern parallel to the first photoresist pattern and positioned in a space between the first photoresist pattern, and parallel to the first photoresist pattern, and in a space between the first photoresist pattern Forming a fourth photoresist pattern of a line-and-space type to be positioned, thereby reducing both the diameter and the pitch of the contact hole pattern, and improving the yield of the semiconductor device by improving the uniformity of the size of the contact hole pattern. It is characterized by being.

Further, the line-and-space type first to fourth photoresist pattern may have a width of three times the width of the photoresist pattern and finally increase the resolution twice.

In addition, the line-and-space type first to fourth photoresist pattern may have a width of seven times the width of the photoresist pattern, thereby improving the resolution four times.

The method may further include freezing the first to fourth photoresist patterns, respectively, to protect the first photoresist pattern from being developed when each photoresist pattern is formed.

Further, the freezing of the first to fourth photoresist patterns may include coating a freezing agent on a surface of the first to fourth photoresist patterns and removing the coated freezing agent. It may include.

Alternatively, freezing the first to fourth photoresist patterns, respectively, may include baking the first to fourth photoresist patterns at 100 ° C. to 200 ° C. It is also preferable to include the step of irradiating light of the wavelength of 100 nm to 200 nm to the fourth photoresist pattern.

On the other hand, the contact hole forming mask of the semiconductor device according to the present invention is a line-and-space type first photosensitive film pattern, a line and space type second photosensitive film pattern formed in a direction perpendicular to the first photosensitive film pattern, the second A line-and-space-type third photosensitive film pattern parallel to the first photosensitive film pattern and positioned in a space between the first photosensitive film patterns, and a line-and-parallel parallel to the second photosensitive film pattern and parallel to the second photosensitive film pattern. Including the space-type fourth photoresist pattern, the diameter and pitch of the contact hole pattern can be similarly reduced, and the yield of the semiconductor device can be improved by improving the uniformity of the size of the contact hole pattern.

The contact hole forming mask and the contact hole forming method of the semiconductor device of the present invention can reduce both the diameter and pitch of the contact hole pattern, and improve the yield of the semiconductor device by improving the uniformity of the size of the contact hole pattern. To provide.

Hereinafter, an embodiment of a contact hole forming mask and a contact hole forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

3 to 9 are plan views illustrating a method for forming contact holes in a semiconductor device according to the present invention.

First, referring to FIG. 3, a first photoresist layer pattern 30 is formed in a vertical direction on an etched layer (not shown). The first photoresist pattern 30 is formed in a line and space pattern, and the width of the first photoresist pattern 30 is 20 nm, and the space width between the first photoresist pattern 30 is 60 nm. It is desirable to. This is because the resolution limit of the ArF immersion lithography process of 1.35 NA is 80 nm pitch, and the line width or the space line width of the first photoresist pattern 30 may vary according to the lithography technique. That is, it is advantageous to form a contact hole having a uniform pitch, as will be described later, so that the width of the space has three times the width of the photosensitive film pattern.

Subsequently, as illustrated in FIG. 4, the first photoresist pattern 30 is freezed to form a frozen first photoresist pattern 35. 'Freezing' is to prevent development even when the photoresist pattern is exposed. After freezing agent is coated on the surface of the first photoresist pattern 30, TMAH (tetramethyl ammonium) is applied. It is preferable to use a method of washing and removing the freezing agent with hydroxide). At this time, ZEEM 'SOF004' (trade name) or R & H's 'XO081296A (trade name)' can be used as freezing zero.

In addition to using a freezing agent as a method of freezing the first photoresist pattern 30, the first photoresist pattern 30 may be baked at 100 ° C. to 200 ° C., or may have a wavelength of 100 nm to 200 nm. You can also use light irradiation.

Next, referring to FIG. 5, a second photoresist layer pattern 40 is formed on the frozen line-and-space type first photoresist layer pattern 35 in a direction perpendicular thereto (a horizontal direction in FIG. 5). The second photoresist film pattern 40 is also formed in a line-and-space pattern similarly to the first photoresist film pattern 30, and the second photoresist film pattern 40 is formed such that the width of the second photoresist film pattern 40 is 20 nm and the width of the space is 60 nm. It is preferable. At this time, since the frozen first photoresist pattern 35 positioned below the second photoresist pattern 40 is frozen, the second photoresist pattern 40 is not developed even when the second photoresist pattern 40 is exposed and developed.

Thereafter, as shown in FIG. 6, the second photoresist layer pattern 40 is also frozen to form a frozen second photoresist layer pattern 45. The method of freezing the second photoresist film pattern 40 is the same as the method of freezing the first photoresist film pattern 30 described above, that is, a method of using a freezing agent, a method of baking, a method of irradiating light, and the like. May be used, and the same may be applied to other photoresist patterns described later.

Next, referring to FIG. 7, a space between the first photoresist pattern 35 in a direction parallel to the first photoresist pattern 35 on the first and second photoresist patterns 35 and 45. A third photosensitive film pattern 50 positioned in the space). The third photoresist pattern also has a width of 20 nm and a space of 60 nm, and the spacing with the first photoresist pattern 35 is constant, so that the line width of 20 nm and 20 nm together with the first photoresist pattern 35 are obtained. A line and space pattern with spaces is formed.

Thereafter, as shown in FIG. 8, the third photoresist pattern 50 is also frozen in the same manner as the first and second photoresist patterns 30 and 40, thereby forming the frozen third photoresist pattern 55.

9, a space between the second photoresist pattern 45 in a direction parallel to the second photoresist pattern 45 on the first to third photoresist patterns 35, 45, and 45. The fourth photoresist pattern positioned at is formed and then frozen in the same manner as the other photoresist patterns 35, 45, and 55, thereby forming the frozen fourth photoresist pattern 65. The fourth photoresist pattern also has a width of 20 nm and a space of 60 nm, and a distance between the second photoresist pattern 45 is constant, so that the line width of 20 nm and 20 nm together with the third photoresist pattern 45 are obtained. A line and space pattern with spaces is formed.

By this process, line and space patterns 35, 45, 55, and 65 in the vertical and horizontal directions are formed on the etched layer (not shown) of the semiconductor device. The line width is 20 nm and the pitch is 40 between the patterns. A contact hole pattern b of nm is naturally formed at uniform intervals in the horizontal and vertical directions.

Since the line-and-space pattern has less optical proximity effect than the conventional contact-hole pattern, when the contact-hole pattern is formed using the line-and-space pattern as in the present invention, the line width and pitch uniformity of the contact hole pattern are compared with the conventional one. It is possible to increase the yield of the semiconductor device.

In addition, the method described so far uses four masks to form four photoresist patterns 30, 40, 50, and 60; a line width of 20 nm and a space line width of 60 nm to form a contact hole pattern having a line width of 20 nm. The embodiment formed is described. In the same way, if you use a mask with a photoresist pattern line width of 10 nm and a space line width of 70 nm (that is, letting the space line width be seven times the photoresist pattern line width), the number of masks and the number of photoresist patterns will increase, resulting in a line width. This makes it possible to form a contact hole pattern of 10 nm and pitch of 20 nm.

The present invention can be applied not only to ArF lithography described above but also to other lithography such as KrF lithography or EUV lithography.

The present invention is not limited to the described embodiments, and various modifications and changes can be made to those skilled in the art without departing from the spirit and scope of the present invention. It belongs to the claims of the.

1 and 2 are perspective views showing a conventional method for forming a semiconductor device contact hole; And,

3 to 9 are plan views illustrating a method for forming contact holes in a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: etching layer 20: photoresist pattern

25 contact hole pattern 30 first photosensitive film pattern

40: second photosensitive film pattern 50: third photosensitive film pattern

60: fourth photosensitive film pattern

Claims (10)

Forming a first photoresist pattern of line and space type; Forming a line and space type second photoresist pattern in a direction perpendicular to the first photoresist pattern; Forming a line and space type third photoresist pattern in parallel with the first photoresist pattern and positioned in a space between the first photoresist pattern; And Forming a fourth photoresist pattern of a line-and-space type parallel to the first photoresist pattern and positioned in a space between the first photoresist pattern Contact hole forming method of a semiconductor device comprising a. The method according to claim 1, The first to fourth photosensitive film patterns of the line and space type, A method of forming a contact hole in a semiconductor device, characterized in that the width of the space has three times the line width of the photosensitive film pattern width. The method according to claim 1, The first to fourth photosensitive film patterns of the line and space type, A method of forming a contact hole in a semiconductor device, characterized in that the width of the space has a line width seven times the width of the photoresist pattern. The method according to claim 1, And freezing the first to fourth photoresist patterns, respectively. The method according to claim 4, Freezing the first to fourth photoresist patterns, respectively, Coating a freezing agent on a surface of the first to fourth photoresist patterns; And Removing the coated freezing agent. The method according to claim 4, Freezing the first to fourth photoresist patterns, respectively, And baking the first to fourth photoresist patterns at 100 ° C to 200 ° C. The method according to claim 4, Freezing the first to fourth photoresist patterns, respectively, And irradiating light having a wavelength of 100 nm to 200 nm to the first to fourth photoresist patterns. A first photosensitive film pattern of line and space type; A second photosensitive film pattern of line and space type formed in a direction perpendicular to the first photosensitive film pattern; A third photoresist pattern of a line-and-space type parallel to the first photoresist pattern and positioned in a space between the first photoresist pattern; And A fourth photoresist pattern of a line-and-space type parallel to the second photoresist pattern and positioned in a space between the second photoresist pattern A contact hole forming mask of a semiconductor device comprising a. The method according to claim 8, The first to fourth photosensitive film patterns of the line and space type, A mask for forming a contact hole in a semiconductor device, wherein the space has a line width three times the width of the photosensitive film pattern. The method according to claim 8, The first to fourth photosensitive film patterns of the line and space type, A mask for forming a contact hole in a semiconductor device, characterized in that the width of the space has a line width seven times the width of the photosensitive film pattern.
KR1020090059353A 2009-06-30 2009-06-30 Mask for forming contact hole of semiconductor device and method for forming contact hole of semiconductor device KR20110001693A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130109829A (en) * 2012-03-28 2013-10-08 삼성전자주식회사 Method for forming fine patterns of semiconductor device
US8652968B2 (en) 2012-01-11 2014-02-18 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
US8785319B2 (en) 2012-03-28 2014-07-22 Samsung Electronics Co., Ltd. Methods for forming fine patterns of a semiconductor device
US9431324B2 (en) 2014-04-14 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor device having contact structures

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8652968B2 (en) 2012-01-11 2014-02-18 Samsung Electronics Co., Ltd. Method of manufacturing a semiconductor device
KR20130109829A (en) * 2012-03-28 2013-10-08 삼성전자주식회사 Method for forming fine patterns of semiconductor device
US8785319B2 (en) 2012-03-28 2014-07-22 Samsung Electronics Co., Ltd. Methods for forming fine patterns of a semiconductor device
US9431324B2 (en) 2014-04-14 2016-08-30 Samsung Electronics Co., Ltd. Semiconductor device having contact structures
US9761593B2 (en) 2014-04-14 2017-09-12 Samsung Electronics Co., Ltd. Semiconductor device

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