KR20100123582A - Array substrate and method of fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate and method of fabricating the same are provided to prevent the deterioration of a thin film transistor without exposing an active layer to outside through dry etching. CONSTITUTION: A buffer layer(103), comprised of an inorganic insulating material, is formed on a substrate in which a pixel region and a switch region is defined. An inter-layer insulating film(122) exposes an active layer by depositing and patterning the inorganic insulating material over the active layer to have an active contact hole. A barrier pattern(125) of intrinsic amorphous silicon is contacted with the active layer through the active layer on the inter-layer insulating film. A first protective layer(140) has a gate contact hole exposing a gate electrode.

Description

Array substrate and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate, and more particularly, to a thin film transistor array substrate having an active layer having excellent mobility characteristics and suppressing surface damage generation of the active layer by dry etching.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling the voltage on / off of each pixel, realizes resolution and video. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which is essentially a switching element, is provided to remove each pixel area on / off.

FIG. 1 is a cross-sectional view of a pixel area including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting display device.

As illustrated, the gate electrode 15 is disposed in the switching region TrA in the plurality of pixel regions P defined by the plurality of gate lines (not shown) and the data lines 33 intersecting on the array substrate 11. Is formed, and a gate insulating film 18 is formed on the entire surface of the gate electrode 15. The active layer 22 of pure amorphous silicon and the ohmic contact layer 26 of impurity amorphous silicon are sequentially formed thereon. The configured semiconductor layer 28 is formed. The source electrode 36 and the drain electrode 38 are spaced apart from each other on the ohmic contact layer 26 to correspond to the gate electrode 15. In this case, the gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, and the source and drain electrodes 36 and 38 sequentially formed in the switching region TrA form a thin film transistor Tr.

In addition, a protective layer 42 including a drain contact hole 45 exposing the drain electrode 38 is formed over the source and drain electrodes 36 and 38 and the exposed active layer 22. The pixel electrode 50 is formed on the passivation layer 42 independently of each pixel region P and contacts the drain electrode 38 through the drain contact hole 45. In this case, a semiconductor pattern 29 having a double layer structure of a first pattern 27 and a second pattern 23 made of the same material forming the ohmic contact layer 26 and the active layer 22 below the data line 33. ) Is formed.

Referring to the semiconductor layer 28 of the thin film transistor Tr formed in the switching region TrA in the conventional array substrate 11 having the above-described structure, the active layers 22 of pure amorphous silicon are disposed on top of each other. It can be seen that the first thickness t1 of the portion where the spaced ohmic contact layer 26 is formed and the second thickness t2 of the exposed portion are removed by removing the ohmic contact layer 26. The thickness difference (t1 ≠ t2) of the active layer 22 is due to the manufacturing method, and the characteristic difference of the thin film transistor (Tr) occurs due to the thickness difference (t1 ≠ t2) of the active layer 22. have.

2A through 2E are cross-sectional views illustrating a process of forming a semiconductor layer, a source, and a drain electrode during a manufacturing process of a conventional array substrate. In the drawings, the gate electrode and the gate insulating film are omitted for convenience of description.

First, as shown in FIG. 2A, the pure amorphous silicon layer 20 is formed on the substrate 11, and the impurity amorphous silicon layer 24 and the metal layer 30 are sequentially formed thereon. Thereafter, a photoresist is formed on the metal layer 30 to form a photoresist layer (not shown), and the photoresist is exposed using an exposure mask, and subsequently developed to correspond to a portion where the source and drain electrodes are to be formed. A first photoresist pattern 91 having a thickness is formed, and at the same time, a second photoresist pattern 92 having a fourth thickness that is thinner than the third thickness is formed to correspond to the spaced area between the source and drain electrodes. .

Next, as shown in FIG. 2B, the metal layer (30 of FIG. 2A) exposed to the outside of the first and second photoresist patterns 91 and 92, an impurity and a pure amorphous silicon layer below it (of FIG. 2A) 24 and 20 are etched and removed to form a source drain pattern 31 as a metal material on the top, and an impurity amorphous silicon pattern 25 and an active layer 22 below.

Next, as shown in FIG. 2C, the second photoresist pattern 92 of FIG. 2B having the fourth thickness is removed by ashing. In this case, the first photoresist pattern (91 in FIG. 2B) having the third thickness forms the third photoresist pattern 93 while the thickness thereof is reduced, and remains on the source drain pattern 31.

Next, as illustrated in FIG. 2D, the source and drain electrodes 36 and 38 spaced apart from each other by etching by removing the source drain pattern 31 of FIG. 2C exposed to the outside of the third photoresist pattern 93. To form. In this case, the impurity amorphous silicon pattern 25 is exposed between the source and drain electrodes 36 and 398.

Next, as shown in FIG. 2E, the source and drain electrodes are dry-etched on the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the separation region between the source and drain electrodes 36 and 38. (36, 38) An ohmic contact layer 26 spaced apart from each other is formed under the source and drain electrodes 36 and 38 by removing the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside.

In this case, the dry etching is continued for a long time to completely remove the impurity amorphous silicon pattern (25 of FIG. 2D) exposed to the outside of the source and drain electrodes (36, 38), in this process the impurity amorphous silicon pattern (Fig. Even a portion of the active layer 22 disposed below 25) of 2d may have a predetermined thickness etched at a portion where the impurity amorphous silicon pattern (25 of FIG. 2d) is removed. Therefore, a difference (t1 ≠ t2) occurs in the portion where the ohmic contact layer 26 is formed on the active layer 22 and the exposed portion. If the dry etching is not performed for a long time, the impurity amorphous silicon pattern (25 of FIG. 2D) to be removed in the spaced region between the source and drain electrodes 36 and 38 remains on the active layer 22. This is to prevent this.

Therefore, in the above-described method of manufacturing the array substrate 11, the thickness difference of the active layer 22 is inevitably generated, which causes a decrease in the characteristics of the thin film transistor (Tr in FIG. 1).

In addition, the pure amorphous silicon layer (20 in FIG. 2A) forming the active layer 22 is sufficiently thick in consideration of the thickness of the active layer 22 that is etched and removed during the dry etching process for forming the ohmic contact layer 26. It must be deposited thick enough, resulting in increased deposition time and reduced productivity.

On the other hand, the most important component of the array substrate is formed for each pixel region, and is connected to the gate wiring, the data wiring and the pixel electrode at the same time to selectively and periodically apply a signal voltage to the pixel electrode thin film transistor Can be mentioned.

However, in the case of a thin film transistor generally constructed in a conventional array substrate, it can be seen that the active layer uses amorphous silicon. When the active layer is formed using the amorphous silicon, the amorphous silicon is changed to a quasi-stable state when irradiated with light or an electric field because the atomic arrangement is disordered, which causes a problem in stability when used as a thin film transistor element. The mobility of the carrier is low at 0.1 cm 2 / V · s to 1.0 cm 2 / V · s, which makes it difficult to use it as a driving circuit element.

In order to solve this problem, a method of manufacturing a thin film transistor using polysilicon as an active layer has been proposed by crystallizing a semiconductor layer of amorphous silicon into a semiconductor layer of polysilicon by a crystallization process using a laser device.

However, referring to FIG. 3, which is a cross-sectional view of one pixel region including the thin film transistor in an array substrate having a thin film transistor including a polysilicon semiconductor layer, the polysilicon may be formed using a semiconductor layer ( In the manufacturing of the array substrate 51 including the thin film transistor (Tr) used as a 55) of the n + region 55b or the p + region (not shown) containing a high concentration of impurities in the polysilicon semiconductor layer 55 Requires formation. Therefore, a doping process for forming these n + regions 55b or p + is required, and ion implantation equipment is additionally required for the doping process. In this case, the manufacturing cost is increased, and a problem arises in that a manufacturing line must be newly configured to manufacture the array substrate 51 by adding new equipment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object thereof is to provide a method of manufacturing an array substrate in which the active layer is not exposed to dry etching and thus no damage occurs on the surface thereof, thereby improving the quality of the thin film transistor. .

Furthermore, another object of the present invention is to provide a method of manufacturing an array substrate having a thin film transistor capable of improving a mobility property while forming a semiconductor layer using polysilicon, without requiring a doping process.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate, the method including: forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate insulating layer and an active layer of pure polysilicon sequentially stacked on the switching layer, exposing a gate electrode of impurity polysilicon and an edge of the gate electrode in an island form in the switching region; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on the front surface over the data line and the source and drain electrodes; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

In this case, the step of forming a gate insulating layer of the impurity polysilicon and the edge of the gate electrode in an island form over the buffer layer and the active layer of the pure insulating layer and the pure insulating layer of the polyimide layer is sequentially formed, the buffer layer Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed outside the first photoresist pattern and the inorganic insulating pattern thereunder; Removing the first photoresist pattern.

According to still another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate electrode and a gate insulating film of impurity polysilicon sequentially stacked in an island shape in the switching region over the buffer layer and an active layer of pure polysilicon exposing an edge portion of the gate insulating film over the gate insulating film; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer over the data line and the source and drain electrodes, the first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on a front surface thereof; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

Forming an active layer of pure polysilicon exposing a gate electrode and a gate insulating film of impurity polysilicon sequentially stacked in an island shape in the switching region over the buffer layer and an edge portion of the gate insulating film over the gate insulating film; Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate insulating layer by removing the pure polysilicon pattern exposed outside the first photoresist pattern; Removing the first photoresist pattern.

The solid crystallization process may be crystallization through heat treatment or alternating magnetic field crystallization using an alternating magnetic field crystallization (AMFC) device, wherein the barrier pattern, the ohmic contact layer, the source and drain electrodes are the same mask. Patterned and formed at the same time through the process is characterized by having a form that is sequentially stacked in the same shape and the same size.

The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, and the forming of the gate line may include one end of the gate line. And forming a connected gate pad electrode, wherein forming the second protective layer having the drain contact hole comprises: a data pad contact exposing the gate pad contact hole and the data pad electrode exposing the gate pad electrode; And forming a hole, wherein forming the pixel electrode contacts a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole, and contacting the data pad electrode through the data pad contact hole. Forming a data auxiliary pad electrode.

The gate electrode of the impurity polysilicon has a thickness of about 500 kPa to 1000 kPa, and the active layer of the pure polysilicon is formed to have a thickness of about 400 kPa to 600 kPa.

An array substrate according to the present invention includes a gate electrode of impurity polysilicon formed in an island shape in the switching region on a substrate in which a pixel region and a switching region are defined; A gate insulating film formed on the gate electrode; An active layer of pure polysilicon formed on the gate insulating layer to expose an edge of the gate electrode or the gate insulating layer; An interlayer insulating film formed on an entire surface of the active layer, the active contact hole exposing the active layer and spaced apart from each other; A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing an edge portion of the gate electrode outside the active layer over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; And a pixel electrode formed in the pixel area in contact with the drain electrode through the drain contact hole on the second passivation layer.

The gate insulating film has the same area and shape as that of the gate electrode formed below and is formed to completely overlap, or is formed to have the same area and shape and completely overlaps with the active layer formed thereon.

The impurity polysilicon gate electrode has a thickness of 500 kPa to 1000 kPa, the active layer of the pure polysilicon has a thickness of 400 kPa to 600 kPa, and the barrier pattern has a thickness of 50 kPa to 300 kPa.

The gate pad electrode may include a gate pad electrode connected to an end of the gate line, a data pad electrode connected to an end of the data line, and the second protective layer may include a gate pad contact hole exposing the gate pad electrode, and the data pad. A gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer, the data pad contact hole exposing the electrode; And a data auxiliary pad electrode contacting the data pad electrode through a pad contact hole.

According to still another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate insulating layer and an active layer of pure polysilicon sequentially stacked on the switching layer by exposing a gate electrode having a specific thickness as a specific metal material and an edge of the gate electrode in an island shape in the switching region; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on the front surface over the data line and the source and drain electrodes; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

In this case, the step of forming a gate insulating layer and an active layer of pure polysilicon sequentially stacked while exposing a gate electrode having a specific thickness as a specific metal material and an edge portion of the gate electrode in an island shape in the switching region over the buffer layer. Depositing the specific metal material on the buffer layer to have the specific thickness to form a gate metal layer; Sequentially stacking a first inorganic insulating layer and a pure amorphous silicon layer on the gate metal layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The specific metal material gate is sequentially stacked on the switching region by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer and the gate metal layer thereunder. Forming an electrode, an inorganic insulating pattern, and a pure polysilicon pattern; Exposing the edge portion of the pure polysilicon pattern to the outside of the first photoresist pattern by performing ashing to remove the second photoresist pattern; Exposing an edge portion of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed outside the first photoresist pattern and the inorganic insulating pattern thereunder; Removing the first photoresist pattern.

According to still another aspect of the present invention, there is provided a method of manufacturing an array substrate, the method including: forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate electrode having a specific thickness and an active layer of pure polysilicon exposing the edge portion of the gate insulating layer with a specific metal material sequentially stacked in an island form in the switching region over the buffer layer; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer; A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer over the data line and the source and drain electrodes, the first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on a front surface thereof; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area.

The forming of the gate electrode and the gate insulating layer having a specific thickness and an active layer of pure polysilicon exposing the edge portion of the gate insulating layer with a specific metal material sequentially stacked in the switching region in the form of an island on the switching layer may include: Depositing the specific metal material on the buffer layer to have the specific thickness to form a gate metal layer; Sequentially stacking a first inorganic insulating layer and a pure amorphous silicon layer on the gate metal layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate insulating layer by removing the pure polysilicon pattern exposed outside the first photoresist pattern; Removing the first photoresist pattern.

The solid phase crystallization process is characterized in that the crystallization through heat treatment or alternating magnetic field crystallization using an alternating magnetic field crystallization (AMFC) device.

In addition, the specific metal material is any one or two or more materials of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu), the specific thickness is characterized in that 100 ~ 1000Å.

The barrier pattern, the ohmic contact layer, the source and the drain electrode may be patterned and formed at the same time by performing the same mask process.

The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line, and the forming of the gate line may include a gate connected to one end of the gate line. Forming a pad electrode, wherein forming the second protective layer having the drain contact hole comprises forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode; And forming the pixel electrode, a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole, and data contacting the data pad electrode through the data pad contact hole. Forming an auxiliary pad electrode.

In addition, the active layer of the pure polysilicon is characterized in that it is formed to have a thickness of about 400 kPa to 600 kPa.

According to still another aspect of the present invention, an array substrate includes: a gate electrode formed of a specific metal material and having a first thickness in an island shape in the switching region on a substrate in which a pixel region and a switching region are defined; A gate insulating film formed on the gate electrode; An active layer of pure polysilicon formed on the gate insulating layer to expose an edge of the gate electrode or the gate insulating layer; An interlayer insulating film formed on an entire surface of the active layer, the active contact hole exposing the active layer and spaced apart from each other; A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing an edge portion of the gate electrode outside the active layer over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; And a pixel electrode formed in the pixel area in contact with the drain electrode through the drain contact hole on the second passivation layer.

In this case, the gate insulating film has the same area and shape as the gate electrode formed under the gate electrode, and is formed so as to completely overlap, or is formed to have the same area and shape as the active layer formed on the top and completely overlap.

In addition, the specific metal material may be any one or two or more materials of molybdenum (Mo), molybdenum alloy (MoTi) and copper (Cu) including the same, and the first thickness is 100 kPa to 1000 kPa, and active of the pure polysilicon The layer has a thickness of 400 kPa to 600 kPa and the barrier pattern is 50 kPa to 300 kPa.

The gate pad electrode may include a gate pad electrode connected to an end of the gate line, a data pad electrode connected to an end of the data line, and the second protective layer may include a gate pad contact hole exposing the gate pad electrode, and the data pad. A gate auxiliary pad electrode having a data pad contact hole exposing an electrode and contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer, and the data pad contact And a data auxiliary pad electrode contacting the data pad electrode through a hole.

By the method of manufacturing the array substrate according to the present invention, since the active layer is not exposed to dry etching, surface damage does not occur and thus the thin film transistor characteristics are prevented from deteriorating.

Since the active layer is not affected by dry etching, it is not necessary to consider the thickness lost by etching, thereby reducing the thickness of the active layer, thereby reducing the deposition time, thereby improving productivity.

The array substrate manufactured by the manufacturing method according to the present invention comprises a thin film transistor including a semiconductor layer of an amorphous silicon layer by crystallizing an amorphous silicon layer into a polysilicon layer by a crystallization process and forming a thin film transistor using the semiconductor layer as a semiconductor layer. There is an effect of improving the mobility characteristics by several tens to several hundred times compared to one array substrate.

Since the active layer of polysilicon is used as the semiconductor layer of the thin film transistor, doping of impurities is not necessary, and thus, the initial investment cost can be reduced because new equipment investment for the doping process is not required.

In addition, in the first embodiment, the gate electrode is formed of polysilicon containing impurities, and the gate electrode and the semiconductor layer are deformed or the gate electrode is generated during the crystallization process of the conventional array substrate in which the gate electrode of the metal material is formed. It is effective to solve problems such as shorts at source.

In addition, in the second embodiment, a gate electrode having a specific thickness is formed by using a metal material that satisfies a specific condition, thereby forming a low-resistance metal material used in the manufacture of a conventional array substrate as a gate electrode. The problem of deformation of the substrate and the formation of voids in the gate electrode is solved, and the contact resistance between the gate lines is reduced, thereby reducing the driving voltage of the thin film transistor.

In addition, the gate electrode, the gate insulating film, and the edge of the active layer that are sequentially stacked in the switching region are formed to have an upward step shape so that the insulating layer formed thereon is formed well without interruption, and further, the undercut is prevented by preventing undercut. There is an effect of improving the yield by preventing defects due to foreign matter in the forming portion.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>

4A to 4M are cross-sectional views illustrating manufacturing processes of one pixel area including a thin film transistor of an array substrate according to a first embodiment of the present invention, and FIGS. 5A to 5M illustrate an array substrate according to an embodiment of the present invention. 6 is a cross-sectional view illustrating manufacturing steps of the gate pad part, and FIGS. 6A to 6M are cross-sectional manufacturing steps of the data pad part of the array substrate according to the exemplary embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr, which is connected to the gate and the data line in each pixel region P, is to be formed is defined as a switching region TrA.

First, as shown in FIGS. 4A, 5A, and 6A, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the transparent substrate 101 to have a thickness of about 2000 Pa to 3000 Pa. The buffer layer 103 is formed. Due to the characteristics of the present invention, a solid phase crystallization step is performed in a later step, and a high temperature atmosphere of 600 ° C to 700 ° C is required for this solid phase crystallization step. In this case, when the substrate is exposed to a high temperature atmosphere, alkali ions may be eluted from the surface of the substrate to deteriorate the characteristics of the component made of polysilicon, thereby forming the buffer layer 103 to prevent such a problem.

Next, the impurity amorphous silicon is deposited on the buffer layer 103 to form a first impurity amorphous silicon layer 105 having a thickness of about 500 GPa to 1000 GPa. Subsequently, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) is deposited on the first impurity amorphous silicon layer 105 in succession to form a first inorganic insulating layer 108 having a thickness of about 500 to 4000 Å. By depositing pure amorphous silicon on top, a pure amorphous silicon layer 111 having a thickness of about 400 kPa to 600 kPa is formed.

In this case, the formation of the buffer layer 103, the first impurity amorphous silicon layer 105, the first inorganic insulating layer 108, and the pure amorphous silicon layer 111 may be performed by chemical vapor deposition (CVD). ) Through equipment (not shown). Thus, these four layers 103, 105, 108, 110 are characterized in that they are formed continuously by changing only the reaction gas injected into the chamber (not shown) of the chemical vapor deposition (CVD) equipment (not shown). In this case, the pure amorphous silicon layer 111 is formed in a thickness of about 800 kPa to about 1000 kPa in consideration of the conventional etching to expose the dry etching to remove some thickness from the surface. However, in the exemplary embodiment of the present invention, the active layer of polysilicon (115 of FIG. 4m) finally implemented through the pure amorphous silicon layer 111 is not exposed to dry etching, and thus its thickness is thin by dry etching. There is no problem such as losing. Therefore, the pure amorphous silicon layer 111 may be formed to have a thickness of 400 kPa to 600 kPa, which may serve as an active layer. In this case, the material cost and unit process time may be reduced.

Next, as shown in FIGS. 4B, 5B, and 6B, a solid phase crystallization (SPC) process is performed to improve mobility characteristics of the pure amorphous silicon layer (111 of FIGS. 4A, 5A, and 6A). As a result, the pure amorphous silicon layer (111 of FIGS. 4A, 5A, and 6A) is crystallized to form the pure polysilicon layer 112. At this time, the solid phase crystallization (SPC) is an alternating magnetic field in a temperature atmosphere of 600 ℃ to 700 ℃ using an crystallization or alternating magnetic field crystallization (AMFC) device by heat treatment in an atmosphere of 600 ℃ to 700 ℃, for example. It is preferred that it is crystallization.

Meanwhile, the impurity amorphous silicon layer located under the first inorganic insulating layer (108 in FIGS. 4A, 5A, and 6A) as well as the pure amorphous silicon layer (111 in FIGS. 4A, 5A, and 6A) by the solid phase crystallization process. (105 in Figs. 4A, 5A and 6A) is also crystallized to form the impurity polysilicon layer 106.

Next, as shown in FIGS. 4C, 5C, and 6C, the pure polysilicon layer 112 formed by crystallizing a pure amorphous silicon layer (111 of FIGS. 4A, 5A, and 6A) by the solid state crystallization (SPC) process is performed. A photoresist is applied to form a photoresist layer (not shown), and a light-transmitting region, a blocking region (not shown), and a slit form or a plurality of coating layers are formed on the photoresist layer (not shown). Further, by adjusting the amount of light passing through the light diffraction using an exposure mask (not shown) composed of a semi-transmissive area (not shown) the light transmittance is smaller than the transmission area (not shown) and larger than the blocking area (not shown) Exposure or halftone exposure is performed.

Subsequently, by developing the exposed photoresist layer (not shown), a portion of the portion where the gate electrode 107 of FIG. 4M should be formed on the pure polysilicon layer 112 corresponding to the switching region TrA (to be formed later) The first photoresist pattern 191a having a first thickness is formed to correspond to the active layer of the pure polysilicon (the portion not overlapping with 115 of FIG. 4M), and the gate electrode (107 of FIG. 4M) is formed. A second photoresist pattern 191b having a second thickness that is thicker than the first thickness is formed to correspond to a portion of the portion to be formed of the active layer of pure polysilicon (115 of FIG. 4M). Accordingly, a second photoresist pattern 191b having a second thickness is formed to correspond to a portion where the gate electrode 107 of FIG. 4M is to be overlapped with the active layer of 115 of FIG. 4M. The first photoresist pattern 191a having the first thickness is formed in an area where the active layer (115 of FIG. 4M) of pure polysilicon is not formed among the portions where the gate electrode (107 of FIG. 4M) is to be formed. All regions on the substrate 101 on which the gate electrode 107 of FIG. 4M is not formed are removed to form the pure polysilicon layer 112 by removing the photoresist layer (not shown).

In this case, the present invention is characterized in that the first photoresist pattern 191a is formed to be exposed to the outside of the second photoresist pattern 191b in the switching region TrA. The width of the first photoresist pattern 191a exposed to the outside of the photoresist pattern 191b is differently formed. The first and second photoresist patterns 191a and 191b are formed to have such a structure because a gate electrode (107 in FIG. 4M), a gate insulating film (109 in FIG. 4M) and an active layer (in FIG. 4M) thereon. 115 to prevent the undercut from occurring due to the difference in the etching rate by preventing the edge portion from forming a stairway shape, and to prevent breakage or lifting of the interlayer insulating film 122 (FIG. 4M) formed later by a high step and further formed later. To secure an area for forming a gate contact hole (142 in FIG. 4M) for contact between the gate wiring 145 in FIG. 4M and the gate electrode (107 in FIG. 4M) exposed to the outside of the active layer (115 in FIG. 4M). For sake.

Next, as shown in FIGS. 4D, 5D, and 6D, the pure polysilicon layer (112 in FIGS. 4C, 5C, and 6C) exposed to the outside of the first and second photoresist patterns 191a and 191b, and The first inorganic insulating layer (108 of FIGS. 4C, 5C, and 6C) and the impurity polysilicon layer (106 of FIGS. 4C, 5C, and 6C) positioned below are sequentially etched and removed, thereby removing islands in the switching region TrA. As a form, a gate electrode 107 made of impurity polysilicon sequentially stacked and an inorganic insulating pattern 109 and a pure polysilicon pattern 113 are formed thereon. In this case, the buffer layer 103 is exposed to regions other than the switching region TrA. At this time, the pure polysilicon layer (112 of FIGS. 4C, 5C, and 6C) exposed to the outside of the first and second photoresist patterns 191a and 191b, and the first inorganic insulating layer (FIG. 4C) 108) of 5c and 6c and the impurity polysilicon layer (106 of FIGS. 4c, 5c and 6c) are continuously affected by the dry etching even though the etching gas is changed. The gate electrode 107 which is finally patterned and sequentially stacked and remains, and the inorganic insulating pattern 109 and the pure polysilicon pattern 113 on the upper portion of the gate electrode 107 and the pure polysilicon pattern 113 do not coincide with the edge of the edge and undercut (simultaneously or consecutively) When forming a pattern of a certain shape by etching, the width of the upper pattern is smaller and the width of the lower pattern is smaller so that a blank space is formed between the end of the upper pattern and the end of the lower pattern. foot Because of the undercut form generated in the edge portion of the three patterns by the later process it is remove all does not matter.

Meanwhile, in the embodiment of the present invention, forming the gate electrode 107 with pure impurity polysilicon rather than a metal material may occur when the pure polysilicon pattern 113 formed on the gate electrode 107 is formed. This is to solve the problem. In the case of forming a thin film transistor having a bottom gate structure, a gate electrode is formed of a metal material on a substrate, and a pure amorphous silicon layer is formed on the substrate through a gate insulating film to form a semiconductor layer. The solid phase crystallization from the polysilicon layer requires a relatively high temperature of 600 ° C or higher. Therefore, in the course of the solid phase crystallization process that requires a relatively high temperature, any one of the commonly used low-resistance metal materials, such as aluminum, aluminum alloy, copper, and granular alloys, the thickness of the typical wiring and the electrode is generally 1000Å to 2000Å The gate electrode formed to have a thickness of a degree may cause a problem such as deformation or spikes that penetrate the gate insulating layer and come into contact with the crystallized pure polysilicon layer. Accordingly, in the embodiment of the present invention, in order to solve the problem that occurs during the crystallization process by forming the gate electrode of the metal material having such a low resistance characteristic, the gate electrode using impurity polysilicon that does not cause the above-mentioned problem at high temperature is used. 107 is formed. In the case of the gate electrode 107 made of impurity polysilicon, the conductivity is lower than that of the metal material. However, when the thickness of the gate electrode 107 of the impurity polysilicon is 500 kW to 1000 kW, the resistance value per unit area is 150 kW / sq (□) to It was about 230 mW / sq (□), which is similar to that of indium tin oxide (ITO) or indium zinc oxide (IZO). Therefore, even if the gate electrode is formed of impurity polysilicon, it is not a problem to perform a role as the gate electrode such as to form a channel in the active layer sufficiently.

Next, ashing is performed on the substrate 101 on which the gate electrode 107, the inorganic insulating pattern 109, and the pure polysilicon pattern 113 of the impurity polysilicon are formed, as shown in FIGS. 4E, 5E, and 6E. ) To remove the first photoresist pattern (191a in FIGS. 4D, 5D and 6D) having the first thickness, and thus the pure poly outside the second photoresist pattern 191b in the switching region TrA. One side of the silicon pattern 113 is exposed. The ashing process reduces the thickness of the second photoresist pattern 191b, but still remains on the pure polysilicon pattern 113.

 Next, as illustrated in FIGS. 4F, 5F, and 6F, the pure polysilicon pattern (113 of FIG. 4E) exposed to the outside of the second photoresist pattern (191b of FIG. 4E) and an inorganic insulating pattern disposed below the pure polysilicon pattern (FIG. 4E). A portion of the gate electrode 107 of the impurity polysilicon is exposed by etching 109 of FIG. 4E. At this time, the pure polysilicon pattern (113 of FIG. 4E), which remains unetched by the second photoresist pattern (191b of FIG. 4E), forms an active layer 115 of pure polysilicon, and patterning thereunder. The inorganic insulating pattern 109 of FIG. 4E forms the gate insulating layer 110. In this case, in the embodiment according to the present invention, the active layer 115 of the pure polysilicon and the gate insulating layer 110 disposed below the pure polysilicon have the same shape and size and overlap with each other. Accordingly, the gate electrode 107 of the impurity polysilicon is exposed on the active layer 115 of pure polysilicon, whereby the cross-sectional structure of the edge portion of the component formed in the switching region TrA is upward. It is characterized by being in the form of stairs. In addition, the width of one side of the gate electrode 107 portion of the impurity polysilicon exposed to the outside of the active layer 115 of the pure polysilicon is formed wider than the width of the other side to form a gate contact hole later It is characteristic that we are doing.

 According to the process of the present invention by the progress of the process, when the three layers are continuously etched away, undercuts caused by the difference in the etching rate is characterized in that it can also naturally prevent.

Next, as shown in FIGS. 4G, 5G, and 6G, a strip is performed to remove the second photoresist pattern (191b of FIG. 4F) remaining on the active layer 115 of the pure polysilicon. The active layer 115 of pure polysilicon is exposed.

Next, as shown in FIGS. 4H, 5H, and 6H, one or two materials of an inorganic insulating material, such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx), are disposed on the active layer 115 of the pure polysilicon. By depositing to form a second inorganic insulating layer (not shown) of a single layer or double layer structure. In this case, the second inorganic insulating layer (not shown) is formed at the edge of the gate electrode 107 and the gate insulating layer 110 and the active layer 115 of pure polysilicon formed in the upward step shape in the switch region. It can be well formed without any gaps, and even without the formation of empty spaces due to high steps. When the edges of the gate electrode 107, the gate insulating layer 110, and the active layer 115 of pure polysilicon are formed in the switching region TrA so that their ends coincide with each other without forming a step structure, the buffer layer 103 is formed. As a reference, since a total of three layers are formed up to the active layer 110 of pure amorphous silicon, the total thickness may be 5000 Å or more. In this case, the breakdown of the second inorganic insulating layer formed on the upper part may be caused by a high step. Although it may be generated or deposited in a corner portion (a portion where the side of the buffer layer 103 and the gate electrode 107 located in the bottom layer meet), an embodiment of the present invention is a gate electrode 107 of impurity amorphous silicon. In the gate insulating film 110 and the active layer 115 of pure amorphous silicon, which have the same shape and area on the upper portion thereof, the edge forms an upward step shape. It is characterized by one so that the aforementioned problem does not occur by a dual step to rock formation.

Subsequently, the second inorganic insulating layer (not shown) is subjected to a mask process including a series of unit processes such as application of photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, and the like. By patterning, the center portion of the active layer 115 of pure polysilicon covers the active layer 115 of pure polysilicon to serve as an etch stopper, and the interlayer insulating layer serves as an insulating layer to correspond to other regions. And form 122. In this case, the interlayer insulating layer 122 formed on the active layer 115 of pure polysilicon may be formed on both sides of the active layer 115 of the pure polysilicon based on the center of the active layer 115 of the pure polysilicon. The active contact hole 123 is formed to expose the gap. In addition, the interlayer insulating layer 122 may be formed to have a thickness that is thicker than the sum of the thicknesses of the gate electrode 107 and the gate insulating layer 110 of impurity amorphous silicon disposed thereunder. This is to have a sufficient thickness to form even more seamlessly in the stepped portions generated by the components located below it. That is, when the deposition is less than the thickness of the stepped portion of the lower component there is a possibility that the break occurs in the side portion of the stepped portion, to prevent this.

Next, as shown in Figs. 4i, 5i and 6i, the interlayer having an active contact hole 123 corresponding to the active layer 115 of pure polysilicon and exposing it, and acting as an etch stopper for the center portion thereof. Pure amorphous silicon is deposited on the entire surface of the insulating film 122 to further form a barrier layer (not shown) having a thickness of about 50 GPa to 100 GPa, and a second impurity amorphous having a thickness of about 100 GPa to 300 GPa by depositing impurity amorphous silicon in succession. A silicon layer (not shown) is formed.

Thereafter, a second metal layer (not shown) is deposited on the second impurity amorphous silicon layer (not shown), for example, by depositing any one of molybdenum (Mo), chromium (Cr), and molybdenum (MoTi). To form. In this case, the reason for forming a barrier layer (not shown) made of pure amorphous silicon is that the barrier layer (not shown) is interposed between the active layer 115 of the pure polysilicon and the impurity amorphous silicon layer (not shown). This is to improve the bonding force between the two layers 115 (not shown). This is because the bonding force of the pure polysilicon with the active layer 115 is superior to pure amorphous silicon rather than impurity amorphous silicon.

Next, each pixel is formed on the interlayer insulating layer 122 by patterning the second metal layer (not shown), the second impurity amorphous silicon layer (not shown), and the barrier layer (not shown) under the mask process. The data line 130 is formed at the boundary of the area P, and the data pad electrode 138 connected to one end of the data line 130 is connected to the data pad part DPA at which one end of the data line 130 is located. ). At the same time, in the switching region TrA, source and drain electrodes 133 and 136 spaced apart from each other are formed on the interlayer insulating layer 122 and impurity amorphous silicon is formed under the source and drain electrodes 133 and 136. A barrier pattern 125 of pure amorphous silicon is formed under the ohmic contact layer 127 formed below. In this case, the barrier pattern 125 of pure amorphous silicon is in contact with the active layer 115 of pure polysilicon through the active contact hole 123, respectively.

In addition, the source electrode 133 and the data line 130 formed in the switching region TrA are formed to be connected to each other. In this case, the ohmic contact layer 127 and the barrier pattern 125 formed under each of the source and drain electrodes 133 and 136 spaced apart from each other may have the same shape as that of the source and drain electrodes 133 and 136, respectively. It is characterized by having an area and being formed.

 In addition, as described above, the first dummy pattern 128 made of impurity amorphous silicon and the second dummy pattern made of pure amorphous silicon may also be formed under the data line 130 and the data pad electrode 138. 126 is formed.

In the process of forming the data line 130, the source and drain electrodes 133 and 136, the ohmic contact layer 127, and the barrier pattern 125, the active layer of pure polysilicon constituting the channel region ( Since the interlayer insulating film 122 serving as an etch stopper is formed to correspond to the central portion of the 115, the ohmic contact layer 127 and the barrier pattern 125 may be more accurately formed when the source and drain electrodes 133 and 136 are formed. During etching for patterning, for example, dry etching, the active layer 115 of pure polysilicon is not affected at all. Therefore, it can be seen that the surface damage of the active layer due to the dry etching process, which is a problem mentioned in the prior art, does not occur. That is, the data line 130 and the source and drain electrodes 133 and 136 of the polysilicon formed with the first, that is, the first patterning to form the data line 130 and the source and drain electrodes 133 and 136. ) Is made by dry etching, which is the removal of the impurity amorphous silicon layer (not shown) and the pure amorphous silicon layer beneath it, in which case the source and drain in the switching region TrA. Since the exposed interlayer insulating film 122 is formed by the electrodes 133 and 136, the active layer 115 of pure polysilicon is not affected by the snack etching. Therefore, unlike conventional array substrate fabrication, pure poly by dry etching is performed by patterning an impurity amorphous silicon layer (not shown) and a pure amorphous silicon layer (not shown) to form the ohmic contact layer 127 and the barrier pattern 125. Surface damage of the active layer 115 of silicon does not occur, and the thickness of the active layer 115 of pure polysilicon does not decrease, so that the active layer 115 of pure polysilicon is uniform in the entire switching region TrA. It is characterized by having a thickness.

At this time, the gate electrode 107 of the impurity polysilicon, the gate insulating film 110, the active layer 115 of pure polysilicon, the interlayer insulating film 122, and the like, which are sequentially stacked in the switching region TrA, The barrier pattern 125 of pure amorphous silicon, the ohmic contact layer 127 of impurity amorphous silicon, and the source and drain electrodes 133 and 136 form a thin film transistor Tr.

On the other hand, although not shown in the drawings, in the case where the above-described array substrate is used as the array substrate for the organic light emitting device, the data wiring 130 is formed on the same layer in which the data wiring 130 is formed in parallel with the data wiring 130. Power wirings (not shown) may be further formed to be spaced apart from each other, and in addition to the thin film transistor Tr connected to the data line 130 and the gate line 145 of FIG. A plurality of driving thin film transistors (not shown) having the same structure may be further formed.

Next, as illustrated in FIGS. 4J, 5J, and 6J, the data line 130, the data pad electrode 138, the source and drain electrodes 133 and 136, the ohmic contact layer 127, and the barrier pattern 127 are illustrated. The inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), on the source and drain electrodes 133 and 136, the data line 130, and the data pad electrode 138. To form a first passivation layer 140, and to mask the first passivation layer 140 and the interlayer insulating layer 122 to expose the active layer 115 outside of the pure amorphous silicon. A gate contact hole 142 exposing the gate electrode 107 of the impurity amorphous silicon is formed.

Next, as shown in FIGS. 4K, 5K, and 6K, a second metal material such as aluminum (Al) and aluminum is disposed on the exposed active layer 115 of pure polysilicon and the gate electrode 107 of impurity polysilicon. An alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo) and chromium (Cr) are deposited to form a second metal layer, and patterned by patterning the gate electrode of the exposed impurity polysilicon. A gate pad portion GPA is formed in contact with 107 and intersects the data line 130 at the boundary of each pixel region P, and at one end of the gate line 145. The gate pad electrode 147 connected to one end of the gate line 145 is formed in the gate line 145. In this case, the gate line 145 and the gate pad electrode 147 may be formed of only one metal material of the above-described second metal material to form a single layer structure, or may deposit two or more different second metal materials. By doing so, a double layer or triple layer structure may be achieved. For example, the double layer structure may be made of aluminum alloy (AlNd) / molybdenum (Mo), the triple layer may be made of molybdenum (Mo) / aluminum alloy (AlNd) / molybdenum (Mo). In the drawing, the gate wiring 145 and the gate pad electrode 147 having a single layer structure are shown.

Next, as shown in FIGS. 4L, 5L, and 6L, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate wiring 145 and the gate pad electrode 147. As a result, the second protective layer 150 is formed. Thereafter, a mask process is performed to pattern the second protective layer 150 and the first protective layer 140 below the drain contact hole exposing the drain electrode 136 in each switching region TrA. 152 and a gate pad contact hole 154 exposing the gate pad electrode 147 in the gate pad part GPA. At the same time, in the data pad part DPA, a data pad contact hole 156 exposing the data pad electrode 138 is formed.

Next, as shown in FIGS. 4M, 5M and 6M, a transparent conductive material such as indium-tin-oxide on the front surface over the second protective layer 150 having the respective contact holes 152, 154 and 156. (ITO) or indium-zinc-oxide (IZO) by depositing and patterning the same, and then masking the pixel to contact the drain electrode 136 through the drain contact hole 152 in the pixel region P An electrode 170 is formed. At the same time, in the gate pad part GPA, a gate auxiliary pad electrode 172 is formed on the second passivation layer 150 to contact the gate pad electrode 147 through the gate pad contact hole 154. Also, in the data pad part DPA, the data auxiliary pad electrode 174 may be formed on the second passivation layer 150 to contact the data pad electrode 138 through the data pad contact hole 156. The array substrate 101 according to the embodiment of the invention is completed.

Although not shown in the drawings, when a driving thin film transistor (not shown) is formed in each pixel region P, the thin film transistor Tr formed in the switching region TrA is connected to the pixel electrode 170. Instead of contacting, a drain contact hole formed by exposing the drain electrode (not shown) of the pixel electrode 170 and the driving thin film transistor (not shown) instead of the drain electrode of the driving thin film transistor (not shown). It is formed to be electrically connected by contacting through (not shown). In this case, the thin film transistor Tr formed in the switching region TrA is completely covered by the first and second protective layers 140 and 150 without forming the drain contact hole 152. In addition, the thin film transistor Tr of the switching region TrA and the driving thin film transistor (not shown) are configured to be electrically connected to each other. In the case of an array substrate in which a thin film transistor Tr connected to the gate and data lines 145 and 130 and a driving thin film transistor (not shown) are formed in the pixel region P in the switching region TrA. The array substrate is formed.

On the other hand, the manufacturing method of the array substrate as a modification other than the above-mentioned embodiment is demonstrated. In the case of the modified example of the present invention, since most of the processes are the same as the above-described embodiment, only the parts having differentiation points will be described with reference to the drawings.

7A and 7B are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate according to a modified embodiment of the present invention. Since the structure of the gate and data pad portion is the same as in the embodiment, it is omitted. In this case, the same reference numerals are assigned to the same elements as the exemplary embodiments for the convenience of description.

4F, the gate electrode 107 of impurity polysilicon and the active layer 115 of pure polysilicon are formed to have a stepped step with the gate electrode 107 of impurity polysilicon. It is shown that 107 and the active layer 115 of pure polysilicon have the same shape and area.

However, in a modified example, referring to FIG. 7A, the gate insulating layer 110 has the same area and shape as the gate electrode 107 of the impurity polysilicon, wherein the pure polysilicon on the gate insulating layer 110 is formed. The active layer 115 is formed with the gate insulating layer 110 and the gate electrode 107 of the impurity polysilicon so as to have a smaller width than the edges thereof, and thus has the same area as the gate electrode 107 of the impurity polysilicon. And a gate insulating layer 110 having a shape forming a first step portion, and the active layer 115 of pure polysilicon having a smaller width than that of the gate insulating layer 110 and completely overlapping the second insulating layer. It is characterized by being formed to achieve. Therefore, also in this case, the edges of the gate electrode 107 and the gate insulating film 110 of the impurity polysilicon and the active layer 115 of the pure polysilicon are formed in an upper step as the cross-sectional structure thereof forms an upward step. It can be seen that it is possible to prevent the break due to the high step of the insulating film 122 and to prevent the undercut.

Next, referring to FIG. 7B, in the modification as described above, the gate electrode 107 of the impurity polysilicon and the gate insulating layer 110 have the same area and shape and overlap each other. Therefore, when the gate contact hole 142 exposing the gate electrode 107 of the impurity polysilicon is formed, the impurity poly is patterned by the first protective layer 140 and the interlayer insulating layer 122 and the gate insulating layer 110. Exposing the gate electrode 107 of silicon is a difference from the embodiment. All other processes may proceed in the same manner as mentioned in the above-described embodiment, thereby completing the array substrate 101 according to the modification of the present invention.

On the other hand, in the embodiment and one modification of the present invention, the gate electrode is formed of an impurity polysilicon as an example.

In still another embodiment of the present invention, a gate electrode is formed of a metal material.

&Lt; Embodiment 2 >

In the case of the array substrate according to the second embodiment of the present invention, the structure thereof is the same as that of the first embodiment described above, and the fabrication method is performed by forming a metal layer using a sputtering apparatus for depositing a metal material after the formation of the buffer layer. Since the formed substrate is moved back to the chamber in the chemical vapor deposition apparatus, the same process is performed except that the inorganic insulating material and the pure amorphous silicon are deposited to form the inorganic insulating layer and the pure amorphous silicon layer, and thus the drawings are omitted.

When manufacturing an array substrate having a thin film transistor having a bottom gate structure, since the gate electrode is located lower than the active layer, a solid phase crystallization process having a process temperature of 600 ° C to 800 ° C is performed to improve the characteristics of the active layer. In general, the gate electrode made of a low-resistance metal material is deformed to cause defects, so that in some embodiments of the present invention and one modified example, impurity polysilicon is used as the gate electrode, but the second embodiment of the present invention The present invention provides an array substrate and a method of manufacturing the same, wherein the array substrate can be manufactured by forming a gate electrode from a metal material and not causing deformation or deformation of the substrate during the solid phase crystallization process.

In the second embodiment of the present invention, the metal material used as the gate electrode satisfies specific conditions. This particular condition is that the melting point should be higher than the solid phase crystallization temperature, and more preferably 1000 ° C or more, so that no melting, reverberation or diffusion occurs even when exposed to high temperatures of 600 ° C to 800 ° C.

In general, when the gate electrode is formed by using an aluminum alloy, which is a low-resistance metal material, which is commonly used as a gate electrode, irregular voids are generated in the gate electrode itself after the solid crystallization process. As a result, driving failure of the thin film transistor due to the difference in the resistance of each pixel region is caused, and the deterioration rate of the thin film transistor is increased due to the voids generated therein, thereby reducing the life of the thin film transistor.

On the other hand, although it is not a characteristic of the metal material itself, even if the metal material used as the gate electrode has a melting point of 1000 ° C. or higher, it should not cause deformation of the substrate itself by shrinkage expansion action when exposed to a high temperature environment, and internal resistance per unit area. Since it should be at least the same level as impurity polysilicon, the thickness of the gate electrode made of a metal material having a high melting point is preferably 100 kPa to 1000 kPa, more preferably 100 kPa to 500 kPa.

In view of the specific conditions under which such a metal material can be used as a gate electrode, in the second embodiment of the present invention, a metal material such as molybdenum (Mo) having a melting point higher than the solid phase crystallization process temperature, so as not to cause the above-mentioned problem, Molybdenum alloys such as molybdenum (MoTi), and one or more of copper (Cu) is used.

Molybdenum (Mo) and molybdenum alloys (MoTi) and copper (Cu) containing the same have higher resistance values per unit area than low-resistance metallic materials, but the degree of deformation is very small within the temperature range above the crystallization temperature and below the melting point. In the experiment, it was found that voids do not occur inside and the degree of expansion and contraction is relatively small with rapid temperature change.

Metal materials such as chromium (Cr) and titanium (Ti) also have a melting point of 1000 ° C or more, but after the solid phase crystallization process having a process temperature of 600 ° C to 800 ° C, voids occur irregularly inside or temperature change Due to the severe problems such as shrinkage expansion caused by the deformation of the substrate within the thickness range described above.

Meanwhile, even when the gate electrode is formed using any one or two of the above-described molybdenum (Mo) and molybdenum alloy (MoTi) and copper (Cu) including the same, such a metal material (molybdenum (Mo) and the same) When molybdenum alloys (MoTi) and copper (Cu)) are formed to have a thickness greater than 1000 μs on a substrate through a sputtering device, the substrate itself is formed by forming an inorganic insulating layer and a pure amorphous silicon layer thereon and proceeding to solid phase crystallization. It can be seen experimentally that the deformation of.

Therefore, in the array substrate according to the second embodiment, the gate electrode is formed using one or two or more of molybdenum (Mo), molybdenum alloy (MoTi), and copper (Cu) including the same. If the thickness is less than 100 kW, all of these factors must be increased because the resistance per unit area must be increased when the impurity polysilicon is used as the active layer in consideration of its internal resistance, and the driving voltage of the thin film transistor must be increased. In consideration of the above, when the gate electrode is formed of the above-described metal material, the thickness thereof is preferably 100 kPa to 1000 kPa.

According to the second embodiment of the present invention, any one or two of the above-described molybdenum (Mo), molybdenum alloy (MoTi), and copper (Cu) may be formed as a gate electrode to have a thickness of about 100 kV to 1000 kPa. Since the structure of the array substrate is the same as that of the first embodiment, a description of the entire structure and configuration of the array substrate according to the second embodiment is omitted.

In addition, the manufacturing method according to the second embodiment is different only in the step of forming a pure amorphous silicon layer including the buffer layer before the solid phase crystallization process with the first embodiment, but other processes go through the same process. Only points that are different from the first embodiment will be described.

In the first embodiment, the buffer layer, the impurity amorphous silicon layer, the inorganic insulating layer, and the pure amorphous silicon layer are simultaneously formed in the chamber of the chemical vapor deposition apparatus. In the second embodiment, the gate electrode is formed of a metal material. In the case of metallic materials, the deposition is not carried out through chemical vapor deposition equipment.

Therefore, after the inorganic insulating material is deposited on the substrate through the chemical vapor deposition apparatus to form a buffer layer, the substrate on which the buffer layer is deposited is moved into the chamber of the sputtering apparatus within the chamber of the chemical vapor deposition apparatus, and then the Molybdenum (Mo), molybdenum alloy (MoTi) and copper (Cu) including at least one or two or more of the sputtering device is deposited to form a gate metal layer having a single layer or multilayer structure having a thickness of about 100 kV to 1000 kV. do. Thereafter, the substrate on which the gate metal layer is formed is moved to a chamber of a chemical vapor deposition apparatus, and an inorganic insulating layer and a pure amorphous silicon layer are formed by continuously depositing an inorganic insulating material and pure amorphous silicon on the gate metal layer.

     Thereafter, the same process as that described in the first embodiment may be performed including the solid phase crystallization process to complete the array substrate according to the second embodiment having a gate electrode made of molybdenum alloy or copper including molybdenum.

Thus, when the gate electrode is formed to have a thickness of about 100 GPa to 1000 GPa as one or more of molybdenum (Mo), molybdenum alloy (MoTi), and copper (Cu) including the same, it causes deformation of a substrate during solid phase crystallization. In addition, the internal resistance value per unit area of the gate electrode itself is smaller than that of the array substrate according to the first embodiment in which the impurity polysilicon is formed as the gate electrode, and the contact resistance with the gate wiring is reduced, thereby reducing the thin film transistor. It was possible to obtain the effect of reducing the power consumption by lowering the driving voltage of.

In addition, the array substrate according to the second embodiment in which the gate electrode is formed of a metal material satisfying a specific condition includes a gate electrode made of impurity polysilicon by fundamentally preventing a problem due to photocurrent generation due to the characteristics of the semiconductor material. There is an advantage in that the on and off current characteristics of the thin film transistor compared to the array substrate according to the first embodiment is improved.

1 is a cross-sectional view of a pixel region including a thin film transistor in a conventional array substrate constituting a liquid crystal display device or an organic light emitting device.

2A through 2E are cross-sectional views illustrating a step of forming a semiconductor layer, a source and a drain electrode during a manufacturing step of a conventional array substrate;

3 is a cross-sectional view of one pixel area including the thin film transistor in an array substrate having a thin film transistor having a polysilicon semiconductor layer in the related art.

4A to 4M are cross-sectional views illustrating manufacturing steps of one pixel area including a thin film transistor of an array substrate according to a first exemplary embodiment of the present invention.

5A to 5M are cross-sectional views of manufacturing steps of a gate pad portion of an array substrate according to a first embodiment of the present invention.

6A to 6M are cross-sectional views of manufacturing steps of a data pad portion of an array substrate according to a first embodiment of the present invention.

7A and 7B are cross-sectional views illustrating manufacturing steps of one pixel region including a thin film transistor of an array substrate according to a modification of the present invention.

<Description of Symbols for Main Parts of Drawings>

101 substrate 103 buffer layer

107: gate electrode of impurity polysilicon

110 gate insulating film 115 active layer of pure polysilicon

122: interlayer insulating film 123: active contact hole

125: barrier pattern 126: second dummy pattern

127: ohmic contact layer 128: the first dummy pattern

130: data wiring 133: source electrode

136: drain electrode 140: first protective layer

142: gate contact hole 145: gate wiring

150: second protective layer 152: drain contact hole

170: pixel electrode

P: Pixel Area Tr: Thin Film Transistor

TrA: switching area

Claims (25)

Forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate insulating layer and an active layer of pure polysilicon sequentially stacked on the switching layer, exposing a gate electrode of impurity polysilicon and an edge of the gate electrode in an island form in the switching region; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on the front surface over the data line and the source and drain electrodes; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 1, Forming an active layer of sequentially stacked gate insulating layers and pure polysilicon while exposing a gate electrode of impurity polysilicon and an edge of the gate electrode in an island form over the buffer layer in an island form; Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed outside the first photoresist pattern and the inorganic insulating pattern thereunder; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. Forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate electrode and a gate insulating film of impurity polysilicon sequentially stacked in an island shape in the switching region over the buffer layer and an active layer of pure polysilicon exposing an edge of the gate insulating film over the gate insulating film; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer over the data line and the source and drain electrodes, the first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on a front surface thereof; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 3, wherein Forming a gate electrode and a gate insulating film of impurity polysilicon sequentially stacked in the island region in the switching region over the buffer layer and an active layer of pure polysilicon exposing the edge of the gate insulating film over the gate insulating film, Sequentially depositing an impurity amorphous silicon layer, a first inorganic insulating layer, and a pure amorphous silicon layer on the buffer layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer and the impurity amorphous silicon layer into a pure polysilicon layer and an impurity polysilicon layer, respectively; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate insulating layer by removing the pure polysilicon pattern exposed outside the first photoresist pattern; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method according to claim 2 or 4, The solid phase crystallization process is characterized in that the crystallization through heat treatment or alternating magnetic field crystallization using alternating magnetic field crystallization (AMFC) device. The method according to claim 1 or 3, And the barrier pattern, the ohmic contact layer, the source and the drain electrode are patterned and formed at the same time by performing the same mask process to sequentially form the same shape and the same size. The method according to claim 1 or 3, The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line. The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The forming of the pixel electrode may include forming a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole. Method of manufacturing an array substrate comprising a. The method of claim 1, The gate electrode of the impurity polysilicon has a thickness of about 500 kPa to 1000 kPa, and the active layer of the pure polysilicon is formed to have a thickness of about 400 kPa to 600 kPa. A gate electrode of impurity polysilicon formed in an island shape in the switching region on the substrate where the pixel region and the switching region are defined; A gate insulating film formed on the gate electrode; An active layer of pure polysilicon formed on the gate insulating layer to expose an edge of the gate electrode or the gate insulating layer; An interlayer insulating film formed on an entire surface of the active layer, the active contact hole exposing the active layer and spaced apart from each other;  A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing an edge portion of the gate electrode outside the active layer over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer; Array substrate comprising a. The method of claim 9, And the gate insulating layer has the same area and shape as that of the gate electrode formed below and completely overlaps with the gate insulating layer, or has the same area and shape as the active layer formed thereon and completely overlaps with each other. The method of claim 9, The gate electrode of impurity polysilicon has a thickness of 500 kPa to 1000 kPa, the active layer of the pure polysilicon has a thickness of 400 kPa to 600 kPa, and the barrier pattern has a thickness of 50 kPa to 300 kPa. The method of claim 9, A gate pad electrode connected to an end of the gate line and a data pad electrode connected to an end of the data line, The second protective layer includes a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. A gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer, and data auxiliary contacting the data pad electrode through the data pad contact hole Pad electrode Array substrate comprising a. Forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate insulating layer and an active layer of pure polysilicon sequentially stacked on the switching layer by exposing a gate electrode having a specific thickness as a specific metal material and an edge of the gate electrode in an island shape in the switching region; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on the front surface over the data line and the source and drain electrodes; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 13, Forming an active layer of pure polysilicon and a gate insulating film sequentially stacked while exposing a gate electrode having a specific thickness as a specific metal material and an edge portion of the gate electrode in an island shape in the switching region over the buffer layer, Depositing the specific metal material on the buffer layer to have the specific thickness to form a gate metal layer; Sequentially stacking a first inorganic insulating layer and a pure amorphous silicon layer on the gate metal layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The specific metal material gate is sequentially stacked on the switching region by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer and the gate metal layer thereunder. Forming an electrode, an inorganic insulating pattern, and a pure polysilicon pattern; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate electrode of the impurity polysilicon by removing the pure polysilicon pattern exposed outside the first photoresist pattern and the inorganic insulating pattern thereunder; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. Forming a buffer layer made of an inorganic insulating material on a substrate in which a pixel region and a switching region are defined; Forming a gate electrode having a specific thickness and an active layer of pure polysilicon exposing the edge portion of the gate insulating layer with a specific metal material sequentially stacked in an island form in the switching region over the buffer layer; Depositing and patterning an inorganic insulating material over the active layer to form an interlayer insulating film having active contact holes spaced apart from and exposed to the active layer;  A barrier pattern of pure amorphous silicon contacting the active layer and spaced apart from each other through the active contact hole on the interlayer insulating layer, an ohmic contact layer of impurity amorphous silicon on each of the barrier patterns, and an upper portion of the ohmic contact layer Forming a source and drain electrode spaced apart from each other, and simultaneously forming a data line on the boundary of the pixel region and connected to the source electrode on the interlayer insulating film; Forming a first passivation layer over the data line and the source and drain electrodes, the first passivation layer having a gate contact hole exposing the gate electrode outside the active layer on a front surface thereof; Forming a gate wiring on the first protective layer as a metal material to contact the gate electrode through the gate contact hole and intersect the data wiring at a boundary of the pixel region; Forming a second protective layer having a drain contact hole exposing the drain electrode on the entire surface of the substrate over the gate wiring; Forming a pixel electrode on the second protective layer in contact with the drain electrode through the drain contact hole in the pixel area Method of manufacturing an array substrate comprising a. The method of claim 15, Forming a gate electrode having a specific thickness and an active layer of pure polysilicon exposing the edge portion of the gate insulating film with a specific metal material sequentially stacked in an island form in the switching region over the buffer layer, Depositing the specific metal material on the buffer layer to have the specific thickness to form a gate metal layer; Sequentially stacking a first inorganic insulating layer and a pure amorphous silicon layer on the gate metal layer; Performing a solid phase crystallization process to crystallize the pure amorphous silicon layer into a pure polysilicon layer; The first photoresist pattern having a first thickness may be formed on the pure polysilicon layer to correspond to a portion where the active layer is formed in the switching region, and may correspond to an edge portion of the gate electrode exposed outside the active layer. Forming a second photoresist pattern having a second thickness that is thinner than the first thickness; The impurity poly is formed by sequentially removing the pure polysilicon layer exposed to the outside of the first and second photoresist patterns, the first inorganic insulating layer, and the impurity polysilicon layer below and sequentially stacked in the switching region. Forming a gate electrode, an inorganic insulating pattern, and a pure polysilicon pattern of silicon; Exposing the edge of the pure polysilicon pattern to the outside of the first photoresist pattern by removing the second photoresist pattern by ashing; Exposing an edge portion of the gate insulating layer by removing the pure polysilicon pattern exposed outside the first photoresist pattern; Removing the first photoresist pattern Method of manufacturing an array substrate comprising a. The method according to claim 14 or 16, The solid phase crystallization process is characterized in that the crystallization through heat treatment or alternating magnetic field crystallization using alternating magnetic field crystallization (AMFC) device. The method according to any one of claims 13 to 16, The specific metal material is any one or two or more of molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu), The specific thickness is a method of manufacturing an array substrate, characterized in that 100 ~ 1000Å. The method of claim 18, And the barrier pattern, the ohmic contact layer, the source and the drain electrode are patterned and formed at the same time by performing the same mask process to sequentially form the same shape and the same size. The method of claim 18, The forming of the source and drain electrodes and the data line may include forming a data pad electrode connected to one end of the data line. The forming of the gate wiring may include forming a gate pad electrode connected to one end of the gate wiring, The forming of the second passivation layer having the drain contact hole may include forming a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. The forming of the pixel electrode may include forming a gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole and a data auxiliary pad electrode contacting the data pad electrode through the data pad contact hole. Method of manufacturing an array substrate comprising a. The method of claim 18, The active layer of the pure polysilicon is a manufacturing method of the array substrate, characterized in that formed to have a thickness of about 400 ~ 600Å. A gate electrode formed of a specific metal material and having a first thickness in an island shape on the switching region on the substrate on which the pixel region and the switching region are defined; A gate insulating film formed on the gate electrode; An active layer of pure polysilicon formed on the gate insulating layer to expose an edge of the gate electrode or the gate insulating layer; An interlayer insulating film formed on an entire surface of the active layer, the active contact hole exposing the active layer and spaced apart from each other;  A barrier pattern of pure amorphous silicon formed in the switching region in contact with the active layer through the active contact hole and spaced apart from each other through the active contact hole; An ohmic contact layer of impurity amorphous silicon formed on the spaced apart barrier pattern, respectively; Source and drain electrodes spaced apart from each other on the spaced apart ohmic contact layer; A data line formed on a boundary of the pixel area over the interlayer insulating layer and connected to the source electrode; A first passivation layer having a gate contact hole exposing an edge portion of the gate electrode outside the active layer over the data line; A gate wiring formed on the boundary of the pixel area over the first passivation layer, the gate wiring being in contact with the gate electrode and crossing the data wiring; A second protective layer having a drain contact hole exposing the drain electrode over the gate line; A pixel electrode formed in the pixel region in contact with the drain electrode through the drain contact hole on the second passivation layer; Array substrate comprising a. The method of claim 22, And the gate insulating layer has the same area and shape as that of the gate electrode formed below and completely overlaps with the gate insulating layer, or has the same area and shape as the active layer formed thereon and completely overlaps with each other. The method of claim 22, The specific metal material is one or more materials of molybdenum (Mo) and molybdenum alloy (MoTi) and copper (Cu) including the same, And the first thickness is 100 mW to 1000 mW, the active layer of the pure polysilicon is 400 mW to 600 mW, and the barrier pattern has a thickness of 50 mW to 300 mW. The method of claim 22, A gate pad electrode connected to an end of the gate line and a data pad electrode connected to an end of the data line, The second protective layer includes a gate pad contact hole exposing the gate pad electrode and a data pad contact hole exposing the data pad electrode. A gate auxiliary pad electrode contacting the gate pad electrode through the gate pad contact hole with the same material forming the pixel electrode on the second passivation layer, and data auxiliary contacting the data pad electrode through the data pad contact hole Pad electrode Array substrate comprising a.

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