KR20200135911A - Thin film transistor and method of manufacturing the same and display including the same - Google Patents

Abstract

Disclosed are a method of manufacturing a thin film transistor, a thin film transistor manufactured thereby, and a display including the same. According to the present invention, the method of manufacturing a thin film transistor comprises the steps of: sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer; forming a photoresist layer having a dual structure of a first portion and a second portion having a smaller size on the first etch stop layer such that a partial region of the first etch stop layer is exposed; first-dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask; etching the channel layer from the side by wet etching, and removing a partial thickness of the photoresist layer by a photoresist ashing process; and forming the first etch stop layer so that the first etch stop layer is stepped with respect to the channel layer by removing a partial thickness of the photoresist layer using the photoresist layer as a mask, and then dry etching the exposed portion of the first etch stop layer.

Description

Thin film transistor and method of manufacturing the same, display including the same

It relates to a thin film transistor, a method of manufacturing the same, and a display including the same.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. For example, since a thin film transistor (TFT) can be manufactured on a glass substrate or a plastic substrate, it is used as a switching element or a driving element in a display field such as a liquid crystal display or an organic light emitting display. In addition, thin film transistors are used as selection switches for cross-point type memory devices.

There is an amorphous silicon thin film transistor (a-Si TFT) used as a driving element and a switching element of a display. These a-Si TFTs are currently most widely used as thin film transistors that can be uniformly formed on a large substrate of over 2m*2m at low cost. However, according to the trend of large-sized and high-definition displays, high performance is also required for thin film transistor performance, and the existing a-Si TFT, which has a mobility level of 0.5 cm ² /Vs, is expected to reach its limit.

Therefore, semiconductor materials with superior mobility characteristics compared to amorphous silicon currently used in most liquid crystal display device backplanes are required to realize next-generation ultra-large and high-resolution displays, and various kinds of oxide semiconductors as such high mobility materials Is being studied.

As such an oxide semiconductor device, it is a Zn oxide based thin film transistor that has recently been in the spotlight. Zn oxide-based semiconductor devices can be manufactured by a low-temperature process and are amorphous, so they have the advantage of easy large area. In addition, the Zn oxide-based semiconductor thin film is a material with high mobility and has very good electrical properties such as polycrystalline silicon. Currently, research is being conducted to use an oxide semiconductor material layer having high mobility, that is, a Zn oxide-based material layer in the channel region of a thin film transistor, and a ZnON channel layer containing nitrogen among the ZnO-based channel layers is moving. It is known to have a high degree.

It provides a thin film transistor having high mobility and excellent electrical properties, and a method of manufacturing the same.

It provides a display including the thin film transistor.

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer; Forming a photoresist layer having a dual structure of a first portion and a smaller second portion on the first etch stop layer so that a partial area of the first etch stop layer is exposed; First dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask; Etching the channel layer from a side surface by wet etching; Removing a partial thickness of the photoresist layer by a photoresist ashing process; Removing a partial thickness of the photoresist layer using the photoresist layer as a mask to secondarily dry-etch the exposed portion of the first etch stop layer so that the first etch stop layer is stepped with respect to the channel layer; and ; And removing the photoresist layer.

The photoresist layer having the double structure may be formed through an exposure process applying a halftone mask.

The channel layer may include a ZnON-based semiconductor material.

The layer structure of the channel layer and the first etch stop layer may be formed by continuous deposition.

The gate insulating layer may be formed such that at least a partial thickness of a portion other than the lower region of the channel layer is thinner than the thickness of the lower region of the channel layer.

The gate insulating layer, the channel layer, and the first etch stop layer may have a stepped structure.

The gate insulating layer may be formed to be stepped by etching a portion of the first etch stop layer during a secondary etching process.

The gate insulating layer may be formed of a material capable of being simultaneously etched during a secondary etching process of the first etch stop layer.

The gate insulating layer may be formed of a material capable of being simultaneously etched during a secondary etching process of the first etch stop layer.

The step of forming a second etch stop layer to cover the stepped channel layer and the first etch stop layer; may further include.

A thin film transistor according to an embodiment of the present invention includes a gate insulating layer; A channel layer formed on the gate insulating layer and including a ZnON-based semiconductor material; A first etch stop layer formed on the channel layer; And a source electrode and a drain electrode respectively contacting the channel layer, and the gate insulating layer may be formed such that at least a portion of the thickness of a portion other than the lower region of the channel layer is thinner than that of the lower region of the channel layer.

The gate insulating layer, the channel layer, and the first etch stop layer may have a stepped structure.

The gate insulating layer, the channel layer, and the first etch stop layer may be formed by continuous deposition, and may have a stepped structure through an etching process.

The gate insulating layer, the channel layer, and the first etch stop layer may be formed by continuous deposition, and may have a stepped structure through an etching process.

It may further include a second etch stop layer formed to cover the stepped gate insulating layer, the channel layer and the first etch stop layer.

A display according to an embodiment of the present invention uses the thin film transistor as at least one of a driving element and a switching element.

According to the method of manufacturing a thin film transistor according to an embodiment of the present invention as described above, by dry etching the etch stop layer twice before and after the ZnON-based channel layer wet process, a stepped structure between the channel layer and the etch stop layer is formed, The occurrence of undercut in the channel layer can be prevented. In addition, since the etch stop layer is continuously deposited following the channel layer deposition, and the etch stop layer is used as a hard mask when the channel layer is wet etched, the ZnON-based channel is similar to that of a direct photoresist process for the existing channel layer. There is no case that the upper part of the layer is deteriorated.

In addition, since a stepped structure between the channel layer and the etch stop layer is formed and undercut of the channel layer is prevented, deterioration of device characteristics due to deterioration of the channel layer exposed to the void area can be prevented, resulting in high mobility and excellent A thin film transistor having electrical characteristics can be realized.

In addition, when such a thin film transistor is applied to a pixel of a display as a driving element or a switching element, the performance of the display can be improved.

1 to 7 show a method of manufacturing a thin film transistor according to an embodiment of the present invention.
8 schematically shows the structure of a thin film transistor according to an embodiment of the present invention.
9 shows an exposure process using a half-tone mask.
10 to 13 show a method of manufacturing a thin film transistor according to another embodiment of the present invention.
14 schematically shows an example of a display including a thin film transistor according to an embodiment of the present invention.

Hereinafter, a thin film transistor according to an embodiment of the present invention, a method of manufacturing the same, and a display including the same will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals denote the same components, and the size or thickness of each component in the drawings may be exaggerated for clarity and convenience of description. In addition, what is described below as "top" or "top" may include not only those directly above by contact, but also those above non-contact.

The ZnON-based semiconductor layer shows excellent properties with high mobility, but in terms of process, it has the property of being easily etched in both weak acid and weak alkali solutions. A photo-resist (PR) coating in a photolithography process for patterning a ZnON layer may cause a case in which the top of the ZnON-based semiconductor layer is deteriorated.

According to the method of manufacturing a thin film transistor according to an embodiment of the present invention, instead of directly applying a photoresist on the ZnON-based semiconductor layer, an etch stop layer of SiO ₂ or the like is deposited on the ZnON-based semiconductor layer, and the etch stop. Since the layer is used as a kind of hard mask to perform patterning, there is no case that the top of the ZnON-based semiconductor layer is deteriorated.

Meanwhile, when patterning is performed using an etch stop layer as a kind of hard mask, an island pattern is first formed with a photoresist through a photolithography process, and then the etch stop layer is dry-etched, and the pattern of the etch stop layer formed thereby Is used as a hard mask to wet-etch the ZnON-based semiconductor layer, which is a channel layer.In this case, since the etching rate of the ZnON-based semiconductor layer is very high, undercut the ZnON-based semiconductor layer under the etch stop layer. ) Phenomenon may occur. When such an undercut structure is formed, the channel layer exposed to the void region may be deteriorated during a subsequent process, and device characteristics may be deteriorated by the deteriorated channel layer.

According to the method of manufacturing a thin film transistor according to an embodiment of the present invention, when wet etching a ZnON-based semiconductor layer, an etch stop layer is formed to prevent the occurrence of a ZnON-based semiconductor layer undercut under the etch stop layer. By dry etching the ZnON-based semiconductor layer before and after the wet etching, since the etch stop layer is formed to have a step with respect to the channel layer, the occurrence of an undercut of the ZnON-based semiconductor layer can be prevented.

1 to 7 show a method of manufacturing a thin film transistor according to an embodiment of the present invention. 8 schematically shows the structure of a thin film transistor according to an embodiment of the present invention. The thin film transistor of FIG. 8 has a bottom gate structure in which a gate electrode is provided under the channel layer 40. In FIGS. 1 through 7, the substrate 10 and the gate electrode 30 are omitted for convenience.

Referring to FIG. 1, first, a gate insulating layer 20, a channel layer 40, and an etch stop layer 50 are sequentially deposited, and a photoresist is applied thereon to form a photoresist layer 6'. ) To form.

The gate insulating layer 20 may be formed using an insulating material used in a semiconductor device. For example, the gate insulating layer 20 may be formed of silicon oxide, silicon nitride, a high dielectric material having a higher dielectric constant than silicon oxide, such as HfO _2, Al ₂ O ₃ , or a mixture thereof. The gate insulating layer 20 may be formed in a structure in which at least two or more of silicon oxide, silicon nitride, and high-k material layers are stacked.

The channel layer 40 may be formed to include, for example, a ZnON-based semiconductor material. For example, the channel layer 40 may be formed of a ZnON layer. The channel layer 40 may be deposited by a physical vapor deposition (PVD) method such as a reactive co-sputtering method.

The etch stop layer 50 may be formed to cover the channel layer 40. The etch stop layer 50 may be formed of an insulating material. The etch stop layer 50 may be formed of, for example, silicon oxide, silicon nitride, or an organic insulating material. For example, as will be described later, during the secondary etching process of the etch stop layer 50, the etch stop layer 50 may be formed of the gate insulating layer 50 so that some layers of the exposed portion of the gate insulating layer 20 can be simultaneously etched. 20) may be formed of the same material or a material having similar properties. The etch stop layer 50 serves as a hard mask during the wet etching process of the channel layer 40 and prevents the channel layer 40 from being deteriorated by a photoresist applied through a photolithography process. Can give.

The gate insulating layer 20, the channel layer 40, and the etch stop layer 50 may be sequentially stacked on the substrate 10 on which the gate electrode 30 is formed.

In this case, the layer structure of the channel layer 40 and the etch stop layer 50 may be formed by continuous deposition. That is, according to the manufacturing method according to the embodiment of the present invention, a direct photoresist process is not performed on the channel layer 40, and the etch stop layer 50 can be deposited directly on the deposited channel layer 40. have. As another example, even the gate insulating layer 20 may be formed by continuous deposition. That is, the layer structures of the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 may be formed by continuous deposition. Here, continuous deposition may mean that no other process, such as a photolithography process or an etching process, proceeds between the deposition process and the deposition process.

As described above, since the etch stop layer 50 is continuously deposited following the deposition of the channel layer 40, the top of the ZnON-based channel layer is deteriorated, as in the case of a direct photoresist process for the existing channel layer 40. There is no case.

Referring to FIG. 8, a gate electrode 30 may be formed on a substrate 10 and the gate insulating layer 20 may be formed to cover the gate electrode 30. In FIGS. 1 to 7, the substrate (10) and the illustration of the gate electrode 30 are omitted.

The substrate 10 may be a substrate used to manufacture a semiconductor device. For example, the substrate 10 may be any one of a glass substrate, a plastic substrate, and a silicon substrate. An oxide layer, for example, a silicon oxide layer formed by thermally oxidizing a silicon substrate may be further formed on the surface of the substrate 10.

The gate electrode 30 is for controlling the electrical characteristics of the channel layer 40 and may be formed of a conductive material such as a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or the like. For example, it may be formed of a metal such as Ti, Pt, Ru, Au, Ag, Mo, Al, W, or Cu, an alloy including them, or a conductive oxide such as IZO (InZnO) or AZO (AlZnO).

Referring to FIG. 2, by performing a photolithography process of exposing and patterning the photoresist layer 6 ′, forming a photoresist layer 6 having a dual structure of an island pattern on the etch stop layer 50 , The outer area of the etch stop layer 50 may be exposed. The photoresist layer 6 is formed in a dual structure of a first portion 6a and a smaller second portion 6b.

In order to form the photoresist layer 6 of the double structure, for example, as in FIG. 9, a half-tone mask 7 may be used. 9 shows an exposure process to which the half-tone mask 7 is applied. 9, in a state in which a photoresist layer 6'is formed by applying a photoresist on the stacked structure of the gate insulating layer 20, the channel layer 40, and the etch stop layer 50, the half- When the exposure process is performed using the tone mask 7, the first portion 6a formed to expose the outer area of the etch stop layer 50 and the second portion having a smaller size above the first portion 6a ( The photoresist layer 6 formed in the double structure of 6b) may be formed.

The half-tone mask 7 has a structure having a blocking portion 7a and a slit portion 7b in which a plurality of slits are formed. When exposure is performed using this half-tone mask 7, the portion corresponding to the outer region of the slit portion 7b is completely exposed because the light is not blocked at all by the normal tone portion, so the photoresist layer 6 ) Is completely removed. Compared to this normal tone portion, the portion exposed by the light passing through the slit portion 7b is a half-tone portion, and approximately half of the photoresist layer 6'is removed, so that the first portion ( A photoresist layer 6 formed in a double structure of 6a) and a second portion 6b having a smaller size above the first portion 6a is obtained. The normal tone portion is an exposed portion of the etch stop layer 50 exposed to the photoresist layer 6, and the half-tone portion is an exposed portion of the first portion 6a, and the photoresist layer 6 It has approximately half the thickness of and is located outside the second part 6b. Therefore, using such a half-tone mask 7 can form a photoresist layer 6 formed in a double structure of the first portion 6a and the second portion 6b having a smaller size above the first portion 6a. . The first portion 6a may have a size obtained by adding a half-tone portion to the second portion 6b, and the thickness may correspond to the thickness of the half-tone portion.

Here, the exposed area of the etch stop layer 50 exposed to the double-structured photoresist layer 6 is an area removed by primary dry etching using the double-structured photoresist layer 6 as a mask. May correspond to.

As described above, if, for example, the photoresist layer 6 of the double structure is formed using the half-tone mask 7 and then the dry etching process is performed, as shown in FIG. 3, the photoresist layer of the double structure ( Using 6) as a mask, the exposed area of the etch stop layer 50 is etched.

Next, when the wet etching process is performed, since the channel layer 40 uses the etch stop layer 50 as a hard mask and only the exposed side is partially etched, as shown in FIG. 4, the channel layer 40 is etched. It remains in a smaller size than the stop layer 50.

Next, when a photoresist ashing process is performed to remove a part of the thickness of the photoresist layer 6, as shown in FIG. 5, while having a thickness of the first portion 6a, approximately the second The photoresist layer 6 having a size similar to that of the portion 6b remains, and a portion of the etch stop layer 50 corresponding to the half-tone portion is exposed.

In this state, when the etch stop layer 50 is secondarily dry-etched using the photoresist layer 6 as a mask, the etch stop layer 50 is formed on the channel layer 40 as shown in FIG. It is formed in a stepped structure.

In this way, by dry etching the etch stop layer 50 twice before and after the wet process of the channel layer 40, a stepped structure between the channel layer 40 and the etch stop layer 50 is obtained, so that the channel layer 40 Can be prevented from occurring. At this time, the etch stop layer 50 is etched twice, but since primary etching, photoresist ashing, and secondary etching using the photoresist layer 6 are performed using the double-structured photoresist layer 6, the channel In order to form a stepped structure between the layer 40 and the etch stop layer 50, it is sufficient to perform the photoresist coating and exposure process only once.

Meanwhile, when the gate insulating layer 20 is formed of a material that can be etched at the same time during the etching process of the etch stop layer 50, a partial thickness of the gate insulating layer 20 may be etched to form steps. At this time, for the gate insulating layer 20, since the etch stop layer 50 acts as a mask, a portion of the gate insulating layer 20 corresponding to the outside of the etch stop layer 50 may be etched. .

In this way, the thickness of a portion of the gate insulating layer 20 is partially etched to form a step, so that, for example, the thickness of a portion other than the lower region of the channel layer 40 of the gate insulating layer 20 is the channel layer 40 ) It may be formed to be thinner than the thickness of the lower region. Therefore, a structure in which the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 are stepped can be obtained.

Finally, when the photoresist layer 6 is removed, a structure in which the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 are stepped is obtained as shown in FIG. 7.

On the other hand, according to the method of manufacturing a thin film transistor according to an embodiment of the present invention, as shown in FIG. 8, a stepped structure of the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 is obtained. , A source electrode 60 and a drain electrode 70 that contact both ends of the channel layer 40 may be formed on the gate insulating layer 20. In this case, the source electrode 60 may have a structure extending above one end of the etch stop layer 50 while contacting one end of the channel layer 40. In addition, the drain electrode 70 may have a structure extending above the other end of the etch stop layer 50 while contacting the other end of the channel layer 40.

After forming a predetermined conductive film covering the channel layer 40 and the etch stop layer 50 on the gate insulating layer 20, the conductive film is patterned to form the source electrode 60 and the drain electrode 70 can do. In this case, the etch stop layer 50 may prevent damage to the channel layer 40 due to etching during an etching process for forming the source electrode 60 and the drain electrode 70.

The source electrode 60 and the drain electrode 70 may be formed of the same material as the gate electrode 30 or may be formed of different materials. The source electrode 60 and the drain electrode 70 may be formed of a conductive material, such as a metal, an alloy, a conductive metal oxide, or a conductive metal nitride. For example, the source electrode 60 and the drain electrode 70 may be a metal such as Ti, Pt, Ru, Au, Ag, Mo, Al, W, or Cu, or an alloy including them, a transparent conductive oxide: TCO) and an alloy containing them. Transparent conductive oxides include, for example, In-Sn-O (indium tin oxide: ITO), In-Zn-O (indium zinc oxide: IZO), Al-Zn-O (aluminum zinc oxide: AZO), Ga-Zn -O (gallium zinc oxide: GZO), Zn-Sn-O (zinc tin oxide: ZTO), etc. may be used. The source electrode and the drain electrode may have a single layer or a multilayer structure.

Meanwhile, a passivation layer covering the etch stop layer 50, the source electrode 60, and the drain electrode 70 may be further formed on the gate insulating layer 20. The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, an organic insulating layer, or the like, or may be formed in a structure in which at least two or more of them are stacked.

Referring to FIG. 8, a thin film transistor according to an embodiment of the present invention includes a gate insulating layer 20, a channel layer 40 formed on the gate insulating layer 20 and including a ZnON-based semiconductor material, and the channel layer. An etch stop layer 50 formed on the 40 and a source electrode 60 and a drain electrode 70 respectively contacting the channel layer 40 are included. The gate insulating layer 20 is formed so that a thickness of a portion other than the lower region of the channel layer is substantially smaller than that of the lower region of the channel layer 40, and the gate insulating layer 20 and the channel layer 40 , The etch stop layer 50 forms a stepped structure. The stepped structure may be formed through an etching process after forming the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 by continuous deposition.

In the case of the bottom gate structure as in this embodiment, the gate electrode 30 is formed on the substrate 10, the gate insulating layer 20 is formed on the gate electrode 30, and the channel layer 40 is It may be formed on the gate insulating layer 20 so as to be positioned above the gate electrode 30 to correspond to the gate electrode 30.

A gate electrode 30 may be formed on the substrate 10, and the gate insulating layer 20 may be formed to cover the gate electrode 30.

The etch stop layer 55 may be present on a region of the channel layer 40 except for a portion for contacting the source electrode 60 and the drain electrode 70. The source electrode 60 and the drain electrode 70 may be formed to contact both ends of the channel layer 40. The source electrode 60 and the drain electrode 70 may be formed to contact both ends of the etch stop layer 50 as well. As described above, the etch stop layer 50 prevents damage to the channel layer 40 including a ZnON-based semiconductor material, and an etching process for forming the source electrode 60 and the drain electrode 70 In, the channel layer 40 may be prevented from being damaged by etching.

Meanwhile, a passivation layer may be further formed on the gate insulating layer 20 to cover the etch stop layer, the source electrode, and the drain electrode. The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, an organic insulating layer, or the like, or may be formed in a structure in which at least two or more of them are stacked.

Meanwhile, according to another embodiment of the present invention, the thin film transistor may be formed to have an etch stop layer having a two-layer structure.

10 to 13 schematically show a method of manufacturing a thin film transistor according to another embodiment of the present invention.

First, referring to FIG. 10, the gate insulating layer 20, the channel layer 40, and the etch stop layer 50 form a stepped structure.

In the stepped structure, a gate electrode 30 is formed on the substrate 10, a gate insulating layer 20 is formed to cover the gate electrode 30, and then described above with reference to FIGS. 1 to 7 As long as it can be formed according to the method of manufacturing a thin film transistor according to an embodiment of the present invention.

Next, as shown in FIG. 11, a secondary etch stop layer 80 may be further deposited on the gate insulating layer 20 to cover the channel layer 40 and the etch stop layer 50. Like the etch stop layer 50, the etch stop layer 80 may be formed of an insulating material.

The etch stop layer 80 is a portion of the channel layer 40 exposed to the etch stop layer 50 in a subsequent etching process for forming the source electrode 60 and the drain electrode 70, for example, both ends or And damage to the gate insulating layer 20 may be prevented.

Next, as shown in FIG. 12, a contact between the source electrode 60 and the drain electrode 70 and the channel layer 40 is made so that the channel layer 40 is exposed to the etch stop layers 50 and 80 of the second layer. The contact holes 91 and 95 are formed for this.

Next, referring to FIG. 13, the source electrode 60 and the drain electrode 70 are formed on the etch stop layer 80 to make contact with the channel layer 40 through the contact holes 91 and 95. When formed, a structure in which the etch stop layers 50 and 80 of a two-layer structure are formed, and the source electrode 60 and the drain electrode 70 are in contact with the channel layer 40 through the contact holes 91 and 95 A thin film transistor can be obtained.

Meanwhile, a passivation layer covering the etch stop layer 80, the source electrode 60 and the drain electrode 70 may be further formed on the gate insulating layer 20. The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, an organic insulating layer, or the like, or may be formed in a structure in which at least two or more of them are stacked.

14 schematically shows an example of a display including a thin film transistor according to an embodiment of the present invention. The display of this embodiment may be a liquid crystal display.

Referring to FIG. 13, a liquid crystal layer 150 may be provided between the first substrate 100 and the second substrate 200. The first substrate 100 is an array substrate including a thin film transistor manufactured by the manufacturing method described with reference to FIGS. 1 to 7 or the manufacturing method described with reference to FIGS. 10 to 13 as a switching element or a driving element. substrate). The first substrate 100 may include a pixel electrode connected to a thin film transistor. The second substrate 200 may include a counter electrode corresponding to the pixel electrode. According to the voltage applied between the first substrate 100 and the second substrate 200, the liquid crystal arrangement state of the liquid crystal layer 150 may vary. The configuration of the display including the thin film transistor according to the exemplary embodiment of the present invention is not limited to the structure of FIG. 13 and may be variously modified. For example, a display including a thin film transistor according to an embodiment of the present invention may be an organic light emitting display.

Although many items are specifically described in the above description, they should be construed as examples of specific embodiments rather than limiting the scope of the invention. For example, if one of ordinary skill in the art to which the present invention pertains, components and structures of thin film transistors obtained by the manufacturing method described with reference to FIGS. 1 to 7, 10 to 13 may be variously modified. You will see that you can. As a specific example, the channel layer 40 may be formed in a multilayer structure. Also, the thin film transistor may have a double gate structure.

10...substrate 20...gate insulation layer
30...gate electrode 40...channel layer
50... etch stop layer 60,70... source electrode and drain electrode

Claims (15)

Sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer;
Forming a photoresist layer having a dual structure of a first portion and a smaller second portion on the first etch stop layer so that a partial area of the first etch stop layer is exposed;
First dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask;
Etching the channel layer from a side surface by wet etching;
Removing a partial thickness of the photoresist layer by a photoresist ashing process;
Removing a partial thickness of the photoresist layer using the photoresist layer as a mask to secondarily dry-etch the exposed portion of the first etch stop layer so that the first etch stop layer is stepped with respect to the channel layer; and ;
Including; removing the photoresist layer;
A method of manufacturing a thin film transistor in which the gate insulating layer is formed to have a stepped structure by etching a portion of the first etch stop layer during a secondary etching process, so that the gate insulating layer, the channel layer, and the first etch stop layer have a stepped structure. The method of claim 1, wherein the photoresist layer having a double structure is formed through an exposure process using a halftone mask. The method of claim 1, wherein the channel layer comprises a ZnON-based semiconductor material. The method of claim 1, wherein the layer structure of the channel layer and the first etch stop layer is formed by continuous deposition. The method according to any one of claims 1 to 4, wherein the gate insulating layer has at least a partial thickness of a portion other than the lower region of the channel layer being thinner than that of the lower region of the channel layer. The method of claim 5, wherein the gate insulating layer is formed of a material that can be simultaneously etched during a secondary etching process of the first etch stop layer. The method of claim 1, wherein the gate insulating layer is formed of a material that can be simultaneously etched during a secondary etching process of the first etch stop layer. The method of claim 7, wherein the gate insulating layer is formed to be stepped by etching a portion of the first etch stop layer during a secondary etching process. The method according to any one of claims 1 to 4, further comprising forming a second etch stop layer to cover the stepped channel layer and the first etch stop layer. A gate insulating layer;
A channel layer formed on the gate insulating layer and including a ZnON-based semiconductor material;
A first etch stop layer formed on the channel layer;
And a source electrode and a drain electrode respectively contacting the channel layer,
The gate insulating layer is formed such that at least a partial thickness of a portion other than the lower region of the channel layer is thinner than the thickness of the lower region of the channel layer,
A thin film transistor manufactured by the method of any one of claims 1 to 4, wherein the channel layer is stepped from the gate insulating layer, and the first etch stop layer is stepped from the channel layer. The thin film transistor of claim 10, wherein the gate insulating layer, the channel layer, and the first etch stop layer are formed by continuous deposition, and are formed in a stepped structure through an etching process. The thin film transistor of claim 11, wherein the gate insulating layer is formed of a material that can be simultaneously etched when the first etch stop layer is etched. The thin film transistor of claim 10, further comprising a second etch stop layer formed to cover the gate insulating layer, the channel layer, and the first etch stop layer. A display using the thin film transistor manufactured by the method of any one of claims 1 to 4 as at least one of a driving element and a switching element. A display using the thin film transistor according to any one of claims 10 to 13 as at least one of a driving element and a switching element.

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