KR102335775B1 - Thin film transistor and method of manufacturing the same and display including the same - Google Patents

Abstract

Disclosed are a method for manufacturing a thin film transistor, a thin film transistor manufactured thereby, and a display including the same. According to the disclosed method for manufacturing a thin film transistor, sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer; Forming a photoresist layer having a double structure of a small size second portion, dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask, and wet etching the channel layer etching from the side, removing a partial thickness of the photoresist layer with a photoresist ashing process, and using the photoresist layer as a mask to remove a partial thickness of the photoresist layer to dry the exposed portion of the first etch stop layer a second time By etching, the first etch stop layer is formed to be stepped with respect to the channel layer.

Description

Thin film transistor and method of manufacturing the same, and display including same

It relates to a thin film transistor, a method for manufacturing the same, and a display including the same.

A transistor is widely used as a switching device or a driving device in the field of electronic devices. For example, since a thin film transistor (TFT) can be manufactured on a glass substrate or a plastic substrate, it is used as a switching element or a driving element in a display field such as a liquid crystal display or an organic light emitting display. In addition, the thin film transistor is used as a selection switch of a cross-point type memory device.

An amorphous silicon thin film transistor (a-Si TFT) is used as a driving element and a switching element of a display. The a-Si TFT is currently the most widely used as a thin film transistor that can be uniformly formed on a large substrate over 2m*2m at a low cost. However, high performance is also required for thin film transistor performance according to the trend of display enlargement and high image quality, and the existing a-Si TFT with a ^{mobility of 0.5 cm 2 /Vs is expected to reach its limit.}

Therefore, in order to realize a next-generation super-large, high-resolution display, a semiconductor material having superior mobility compared to amorphous silicon currently used in most liquid crystal display backplanes is required, and various types of oxide semiconductors are required as such high-mobility materials. is being studied

As such an oxide semiconductor device, a Zn oxide based thin film transistor has recently been spotlighted. The Zn oxide-based semiconductor device can be manufactured by a low-temperature process and has an advantage that it is easy to enlarge the area because it is an amorphous phase. In addition, the Zn oxide-based semiconductor thin film is a high-mobility material and has very good electrical properties like polycrystalline silicon. Currently, research is being conducted to use an oxide semiconductor material layer with high mobility, ie, a Zn oxide-based material layer, in the channel region of a thin film transistor, and among the ZnO-based channel layers, a ZnON channel layer containing nitrogen is moved. known to be high.

Provided are a thin film transistor having high mobility and excellent electrical properties, and a method for manufacturing the same.

A display including the thin film transistor is provided.

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer; forming a photoresist layer having a dual structure of a first portion and a smaller size of a second portion on the first etch stop layer to expose a portion of the first etch stop layer; dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask; etching the channel layer from the side by wet etching; removing a portion of the thickness of the photoresist layer with a photoresist ashing process; Using the photoresist layer as a mask to remove a portion of the thickness of the photoresist layer and dry etching the exposed portion of the first etch stop layer a second time so that the first etch stop layer has a step with respect to the channel layer; ; and removing the photoresist layer.

The photoresist layer having the double structure may be formed through an exposure process to which a halftone mask is applied.

The channel layer may include a ZnON-based semiconductor material.

The layer structure of the channel layer and the first etch stop layer may be formed by continuous deposition.

The gate insulating layer may be formed such that at least a partial thickness of a portion other than the lower region of the channel layer is thinner than a thickness of the lower region of the channel layer.

The gate insulating layer, the channel layer, and the first etch stop layer may have a stepped structure.

A portion of the gate insulating layer may be etched during the secondary etching process of the first etch stop layer to form a stepped portion.

The gate insulating layer may be formed of a material that can be simultaneously etched during the secondary etching process of the first etch stop layer.

The gate insulating layer may be formed of a material that can be simultaneously etched during the secondary etching process of the first etch stop layer.

It may further include; forming a second etch stop layer to cover the stepped channel layer and the first etch stop layer.

A thin film transistor according to an embodiment of the present invention includes a gate insulating layer; a channel layer formed on the gate insulating layer and including a ZnON-based semiconductor material; a first etch stop layer formed on the channel layer; and a source electrode and a drain electrode contacting the channel layer, respectively, and the gate insulating layer may be formed such that at least a partial thickness of a portion other than the lower region of the channel layer is thinner than a thickness of the lower region of the channel layer.

The gate insulating layer, the channel layer, and the first etch stop layer may have a stepped structure.

The gate insulating layer, the channel layer, and the first etch stop layer may be formed by continuous deposition, and may have a stepped structure through an etching process.

The gate insulating layer, the channel layer, and the first etch stop layer may be formed by continuous deposition, and may have a stepped structure through an etching process.

A second etch stop layer formed to cover the stepped gate insulating layer, the channel layer, and the first etch stop layer; may further include.

The display according to an embodiment of the present invention uses the thin film transistor as at least one of a driving element and a switching element.

According to the method for manufacturing a thin film transistor according to an embodiment of the present invention as described above, by dry etching the etch stop layer twice before and after the ZnON-based channel layer wet process, a stepped structure between the channel layer and the etch stop layer is formed, Generation of undercuts in the channel layer can be prevented. In addition, since the etch stop layer is deposited continuously to the channel layer deposition, and when the channel layer is wet etched, the etch stop layer is used as a hard mask. There is no chance that the upper part of the layer is altered.

In addition, since a stepped structure between the channel layer and the etch stop layer is formed and the occurrence of undercut of the channel layer is prevented, deterioration of device characteristics due to deterioration of the channel layer exposed to the void region can be prevented, resulting in high mobility and excellent performance. A thin film transistor having electrical characteristics can be realized.

In addition, when such a thin film transistor is applied to a pixel of a display as a driving element or a switching element, the performance of the display can be improved.

1 to 7 show a method of manufacturing a thin film transistor according to an embodiment of the present invention.
8 schematically shows the structure of a thin film transistor according to an embodiment of the present invention.
9 shows an exposure process to which a half-tone mask is applied.
10 to 13 show a method of manufacturing a thin film transistor according to another embodiment of the present invention.
14 schematically shows an example of a display including a thin film transistor according to an embodiment of the present invention.

Hereinafter, a thin film transistor, a method for manufacturing the same, and a display including the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals denote the same components, and the size or thickness of each component in the drawings may be exaggerated for clarity and convenience of explanation. In addition, what is described as "upper" or "upper" hereinafter may include not only those directly above in contact, but also those above in non-contact.

Although the ZnON-based semiconductor layer shows excellent properties of high mobility, it has the property of being easily etched in both weak acid and weak alkali solutions in terms of process. In the photolithography process for patterning the ZnON layer, the upper portion of the ZnON-based semiconductor layer may be deteriorated only by coating a photo-resist (PR).

According to the method for manufacturing a thin film transistor according to an embodiment of the present invention, instead of applying photoresist directly on the ZnON-based semiconductor layer, an etch stop layer made _{of SiO 2 is deposited on the ZnON-based semiconductor layer, and the etch stop} Since the patterning is performed using the layer as a kind of hard mask, the upper part of the ZnON-based semiconductor layer is not deteriorated.

On the other hand, when patterning is performed using the etch stop layer as a kind of hard mask, an island pattern is first formed with photoresist through a photolithography process, and then the etch stop layer is dry etched, thereby forming the pattern of the etch stop layer. is used as a hard mask to wet-etch the ZnON-based semiconductor layer, which is a channel layer. ) may occur. When such an undercut structure is formed, the channel layer exposed to the void region may be altered during a subsequent process, and device characteristics may be deteriorated due to the altered channel layer.

According to the method for manufacturing a thin film transistor according to an embodiment of the present invention, when the ZnON-based semiconductor layer is wet-etched, the etch stop layer is formed to prevent undercut of the ZnON-based semiconductor layer from occurring under the etch stop layer. By dry etching the ZnON-based semiconductor layer before and after the wet etching, the etch stop layer is formed to have a step with respect to the channel layer, so that the undercut of the ZnON-based semiconductor layer can be prevented.

1 to 7 show a method of manufacturing a thin film transistor according to an embodiment of the present invention. 8 schematically shows the structure of a thin film transistor according to an embodiment of the present invention. The thin film transistor of FIG. 8 has a bottom gate structure in which a gate electrode is provided under the channel layer 40 . 1 to 7 , the illustration of the substrate 10 and the gate electrode 30 is omitted for convenience.

Referring to FIG. 1 , first, a gate insulating layer 20 , a channel layer 40 , and an etch stop layer 50 are sequentially deposited, and a photoresist is applied thereon to a photoresist layer 6 ′. ) to form

The gate insulating layer 20 may be formed using an insulating material used in a semiconductor device. For example, the gate insulating layer 20 may be formed of silicon oxide, silicon nitride, a high-k material having a higher dielectric constant than silicon oxide, for example, HfO _{2 ,} Al ₂ O ₃ , or a mixture thereof. The gate insulating layer 20 may be formed in a structure in which at least two or more of silicon oxide, silicon nitride, and high-k material layers are stacked.

The channel layer 40 may be formed to include, for example, a ZnON-based semiconductor material. For example, the channel layer 40 may be formed of a ZnON layer. The channel layer 40 may be deposited by, for example, a physical vapor deposition (PVD) method such as a reactive co-sputtering method.

The etch stop layer 50 may be formed to cover the channel layer 40 . The etch stop layer 50 may be formed of an insulating material. The etch stop layer 50 may be formed of, for example, silicon oxide, silicon nitride, or an organic insulator. For example, as will be described later, during the secondary etching process of the etch stop layer 50 , the etch stop layer 50 is formed on the gate insulating layer ( 20) and may be formed of the same material or a material having similar properties. The etch stop layer 50 serves as a hard mask during the wet etching process of the channel layer 40 and prevents the channel layer 40 from being altered by the photoresist applied through the photolithography process. can give

The gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 may be sequentially stacked on the substrate 10 on which the gate electrode 30 is formed.

In this case, the layer structure of the channel layer 40 and the etch stop layer 50 may be formed by continuous deposition. That is, according to the manufacturing method according to the embodiment of the present invention, a direct photoresist process is not performed on the channel layer 40 , and the etch stop layer 50 can be directly deposited on the deposited channel layer 40 . have. As another example, even the gate insulating layer 20 may be formed by continuous deposition. That is, the layer structure of the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 may be formed by continuous deposition. Here, the continuous deposition may mean that another process, for example, a photolithography process or an etching process, is not performed between the deposition process and the deposition process.

As described above, since the etch stop layer 50 is deposited successively to the channel layer 40 deposition, the upper portion of the ZnON-based channel layer is altered, such as during a direct photoresist process with respect to the existing channel layer 40 . case won't happen.

Referring to FIG. 8 , the gate electrode 30 may be formed on the substrate 10 , and the gate insulating layer 20 may be formed to cover the gate electrode 30 . In FIGS. 1 to 7 , for convenience, the substrate The illustration of (10) and the gate electrode 30 is omitted.

The substrate 10 may be a substrate used for manufacturing a semiconductor device. For example, the substrate 10 may be any one of a glass substrate, a plastic substrate, and a silicon substrate. An oxide layer, for example, a silicon oxide layer formed by thermally oxidizing a silicon substrate may be further formed on the surface of the substrate 10 .

The gate electrode 30 is for controlling the electrical characteristics of the channel layer 40 and may be formed of a conductive material, for example, a metal, an alloy, a conductive metal oxide, a conductive metal nitride, or the like. For example, it may be formed of a metal such as Ti, Pt, Ru, Au, Ag, Mo, Al, W, or Cu, or an alloy including these, a conductive oxide such as IZO (InZnO) or AZO (AlZnO).

Referring to FIG. 2 , by performing a photolithography process of exposing and patterning the photoresist layer 6 ′, a photoresist layer 6 having a dual structure of an island pattern is formed on the etch stop layer 50 . , an outer region of the etch stop layer 50 may be exposed. The photoresist layer 6 is formed in a double structure of a first portion 6a and a second portion 6b having a smaller size.

In order to form the double-structured photoresist layer 6 , for example, as shown in FIG. 9 , a half-tone mask 7 may be used. 9 shows an exposure process to which the half-tone mask 7 is applied. As shown in FIG. 9 , in a state in which a photoresist layer 6 ′ is formed by coating a photoresist on the stacked structure of the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 , the half- When the exposure process is performed using the tone mask 7 , the first portion 6a formed to expose the outer region of the etch stop layer 50 and the second portion having a smaller size above the first portion 6a ( The photoresist layer 6 formed of the double structure of 6b) may be formed.

The half-tone mask 7 has a structure having a blocking portion 7a and a slit portion 7b in which a plurality of slits are formed. When exposure is performed using the half-tone mask 7, the portion corresponding to the region outside the slit portion 7b is completely exposed without blocking light as a normal tone portion, so the photoresist layer 6 ) is completely removed. Compared to the normal tone portion, the portion exposed by the light passing through the slit portion 7b is a half-tone portion and approximately half of the photoresist layer 6' is removed, so that the first portion ( 6a) and the photoresist layer 6 formed in the double structure of the second portion 6b having a smaller size on the upper side of the first portion 6a is obtained. The normal tone portion is an exposed portion of the etch stop layer 50 exposed with respect to the photoresist layer 6 , and the half-tone portion is an exposed portion of the first portion 6a, the photoresist layer 6 . It has a thickness of about half of , and is located outside the second part 6b. Therefore, using this half-tone mask 7, the photoresist layer 6 formed with the dual structure of the first portion 6a and the second portion 6b having a smaller size thereon can be formed. . The first portion 6a may have a size obtained by adding a half-tone portion to the second portion 6b, and the thickness thereof may correspond to the thickness of the half-tone portion.

Here, the exposed region of the etch stop layer 50 exposed to the double-structured photoresist layer 6 is removed by primary dry etching using the double-structured photoresist layer 6 as a mask. may correspond to

As described above, for example, when the double-structured photoresist layer 6 is formed using the half-tone mask 7 and then a dry etching process is performed, as in FIG. 3 , the double-structured photoresist layer ( 6) as a mask, the exposed region of the etch stop layer 50 is etched.

Next, when a wet etching process is performed, since the channel layer 40 uses the etch stop layer 50 as a hard mask and only the exposed side surface is partially etched, as shown in FIG. 4 , the channel layer 40 is etched. It remains in a size smaller than that of the stop layer 50 .

Next, when a photoresist ashing process is performed to remove a partial thickness of the photoresist layer 6 , as shown in FIG. 5 , the second portion approximately has a thickness of the first portion 6a and approximately A photoresist layer 6 having a size similar to that of the portion 6b remains, and a portion of the etch stop layer 50 approximately corresponding to the half-tone portion is exposed.

In this state, when the etch stop layer 50 is secondarily dry etched using the photoresist layer 6 as a mask, as shown in FIG. 6 , the etch stop layer 50 is formed on the channel layer 40 . It is formed in a stepped structure with respect to

As described above, by dry etching the etch stop layer 50 twice before and after the channel layer 40 wet process, a stepped structure between the channel layer 40 and the etch stop layer 50 is obtained, so the channel layer 40 occurrence of undercuts can be prevented. At this time, the etch stop layer 50 is etched twice, but primary etching using the photoresist layer 6 having a dual structure, photoresist ashing, and secondary etching are performed using the photoresist layer 6 , so the channel To form the stepped structure of the layer 40 and the etch stop layer 50 , it is sufficient that the photoresist application and exposure processes are performed only once, respectively.

Meanwhile, when the gate insulating layer 20 is formed of a material that can be etched at the same time during the etching process of the etch stop layer 50 , a partial thickness of the gate insulating layer 20 may also be etched to form a step difference. At this time, with respect to the gate insulating layer 20 , since the etch stop layer 50 acts as a mask, a portion of the gate insulating layer 20 corresponding to the outer side of the etch stop layer 50 may be etched. .

As described above, the thickness of a partial region of the gate insulating layer 20 is partially etched to form a step, for example, the thickness of a portion of the gate insulating layer 20 other than the lower region of the channel layer 40 is equal to that of the channel layer 40 ) may be formed to be thinner than the thickness of the lower region. Therefore, the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 may have a stepped structure.

Finally, when the photoresist layer 6 is removed, as shown in FIG. 7 , a stepped structure is obtained in which the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 are stepped.

Meanwhile, according to the method for manufacturing a thin film transistor according to an embodiment of the present invention, as shown in FIG. 8 , a stepped structure of the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 is obtained, and then , a source electrode 60 and a drain electrode 70 respectively contacting both ends of the channel layer 40 may be formed on the gate insulating layer 20 . In this case, the source electrode 60 may have a structure extending over one end of the etch stop layer 50 while contacting one end of the channel layer 40 . In addition, the drain electrode 70 may have a structure extending over the other end of the etch stop layer 50 while contacting the other end of the channel layer 40 .

After forming a predetermined conductive layer covering the channel layer 40 and the etch stop layer 50 on the gate insulating layer 20 , the conductive layer is patterned to form the source electrode 60 and the drain electrode 70 . can do. In this case, the etch stop layer 50 may serve to prevent the channel layer 40 from being damaged by etching during an etching process for forming the source electrode 60 and the drain electrode 70 .

The source electrode 60 and the drain electrode 70 may be formed of the same material as the gate electrode 30 or may be formed of a different material. The source electrode 60 and the drain electrode 70 may be formed of a conductive material, for example, a metal, an alloy, a conductive metal oxide, or a conductive metal nitride. For example, the source electrode 60 and the drain electrode 70 may be formed of a metal such as Ti, Pt, Ru, Au, Ag, Mo, Al, W or Cu, or an alloy containing them, a transparent conductive oxide: TCO) and an alloy containing them. The transparent conductive oxide is, for example, In-Sn-O (indium tin oxide: ITO), In-Zn-O (indium zinc oxide: IZO), Al-Zn-O (aluminum zinc oxide: AZO), Ga-Zn -O (gallium zinc oxide: GZO), Zn-Sn-O (zinc tin oxide: ZTO), or the like. The source electrode and the drain electrode may have a single-layer or multi-layer structure.

Meanwhile, a passivation layer may be further formed on the gate insulating layer 20 to cover the etch stop layer 50 , the source electrode 60 , and the drain electrode 70 . The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, or an organic insulating layer, or a structure in which at least two or more of them are stacked.

Referring to FIG. 8 , the thin film transistor according to the embodiment of the present invention includes a gate insulating layer 20 , a channel layer 40 formed on the gate insulating layer 20 and including a ZnON-based semiconductor material, and the channel layer An etch stop layer 50 formed on the 40 , a source electrode 60 and a drain electrode 70 respectively contacting the channel layer 40 are included. The gate insulating layer 20 is formed such that a thickness of a portion other than the lower region of the channel layer is thinner than a thickness of the lower region of the channel layer 40 , and the gate insulating layer 20 and the channel layer 40 . , the etch stop layer 50 has a stepped structure. Such a stepped structure may be formed through an etching process after the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 are formed by continuous deposition.

In the case of the bottom gate structure as in the present embodiment, the gate electrode 30 is formed on the substrate 10 , the gate insulating layer 20 is formed on the gate electrode 30 , and the channel layer 40 is It may be formed on the gate insulating layer 20 to be positioned above the gate electrode 30 to correspond to the gate electrode 30 .

A gate electrode 30 may be formed on the substrate 10 , and the gate insulating layer 20 may be formed to cover the gate electrode 30 .

An etch stop layer 55 may be present on a region of the channel layer 40 excluding a portion for contacting the source electrode 60 and the drain electrode 70 . The source electrode 60 and the drain electrode 70 may be formed to contact both ends of the channel layer 40 . The source electrode 60 and the drain electrode 70 may be formed to contact both ends of the etch stop layer 50 . As described above, the etch stop layer 50 prevents damage to the channel layer 40 including the ZnON-based semiconductor material, and an etching process for forming the source electrode 60 and the drain electrode 70 . , it may serve to prevent the channel layer 40 from being damaged by etching.

Meanwhile, a passivation layer may be further formed on the gate insulating layer 20 to cover the etch stop layer, the source electrode, and the drain electrode. The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, or an organic insulating layer, or a structure in which at least two or more of them are stacked.

Meanwhile, according to another embodiment of the present invention, the thin film transistor may be formed to have an etch stop layer having a two-layer structure.

10 to 13 schematically show a method of manufacturing a thin film transistor according to another embodiment of the present invention.

First, referring to FIG. 10 , the gate insulating layer 20 , the channel layer 40 , and the etch stop layer 50 form a stepped structure.

The stepped structure is described above with reference to FIGS. 1 to 7 and 9 after forming the gate electrode 30 on the substrate 10 and forming the gate insulating layer 20 to cover the gate electrode 30 . As long as it can be formed according to the method for manufacturing a thin film transistor according to an embodiment of the present invention.

Next, as shown in FIG. 11 , a secondary etch stop layer 80 may be further deposited on the gate insulating layer 20 to cover the channel layer 40 and the etch stop layer 50 . Like the etch stop layer 50 , the etch stop layer 80 may be formed of an insulating material.

In the subsequent etching process for forming the source electrode 60 and the drain electrode 70 , the etch stop layer 80 is a portion of the channel layer 40 exposed to the etch stop layer 50 , for example, both ends or And it is possible to prevent the gate insulating layer 20 from being damaged.

Next, as shown in FIG. 12 , the contact between the source electrode 60 and the drain electrode 70 and the channel layer 40 is formed so that the channel layer 40 is exposed to the two-layer etch stop layers 50 and 80 . Contact holes 91 and 95 are formed for

Next, referring to FIG. 13 , the source electrode 60 and the drain electrode 70 are formed on the etch stop layer 80 to be in contact with the channel layer 40 through the contact holes 91 and 95 . When formed, it has a two-layered etch stop layer 50 and 80 , and has a structure in which the source electrode 60 and the drain electrode 70 are in contact with the channel layer 40 through the contact holes 91 and 95 . of thin film transistors can be obtained.

Meanwhile, a passivation layer may be further formed on the gate insulating layer 20 to cover the etch stop layer 80 , the source electrode 60 , and the drain electrode 70 . The protective layer may be formed of, for example, a silicon oxide layer, a silicon nitride oxide layer, a silicon nitride layer, or an organic insulating layer, or a structure in which at least two or more of them are stacked.

14 schematically shows an example of a display including a thin film transistor according to an embodiment of the present invention. The display of this embodiment may be a liquid crystal display.

Referring to FIG. 13 , a liquid crystal layer 150 may be provided between the first substrate 100 and the second substrate 200 . The first substrate 100 is an array substrate including a thin film transistor manufactured by the manufacturing method described with reference to FIGS. 1 to 7 or the manufacturing method described with reference to FIGS. 10 to 13 as a switching element or a driving element. substrate). The first substrate 100 may include a pixel electrode connected to the thin film transistor. The second substrate 200 may include a counter electrode corresponding to the pixel electrode. According to the voltage applied between the first substrate 100 and the second substrate 200 , the liquid crystal arrangement state of the liquid crystal layer 150 may vary. The configuration of the display including the thin film transistor according to the embodiment of the present invention is not limited to the structure of FIG. 13 and may be variously modified. For example, the display including the thin film transistor according to the embodiment of the present invention may be an organic light emitting display.

Although many matters have been specifically described in the above description, they should be construed as examples of specific embodiments rather than limiting the scope of the invention. For example, those of ordinary skill in the art to which the present invention pertains. Components and structures of thin film transistors obtained by the manufacturing method described with reference to FIGS. 1 to 7 and 10 to 13 may be variously modified. you will see that you can As a specific example, the channel layer 40 may be formed in a multi-layered structure. In addition, the thin film transistor may have a double gate structure.

10...Substrate 20...Gate Insulation Layer
30...Gate electrode 40...Channel layer
50...Etch stop layer 60,70...Source electrode and drain electrode

Claims (15)

sequentially depositing a gate insulating layer, a channel layer, and a first etch stop layer;
forming a photoresist layer having a dual structure of a first portion and a smaller size of a second portion on the first etch stop layer to expose a portion of the first etch stop layer;
dry etching the exposed portion of the first etch stop layer using the photoresist layer as a mask;
etching the channel layer from the side by wet etching;
removing a portion of the thickness of the photoresist layer with a photoresist ashing process;
Using the photoresist layer as a mask to remove a portion of the thickness of the photoresist layer and dry etching the exposed portion of the first etch stop layer a second time so that the first etch stop layer has a step with respect to the channel layer; ;
Including; removing the photoresist layer;
A method of manufacturing a thin film transistor in which the gate insulating layer is formed to have a stepped structure by etching a portion of the gate insulating layer during the secondary etching process of the first etch stop layer, so that the gate insulating layer, the channel layer, and the first etch stop layer have a stepped structure. The method of claim 1 , wherein the photoresist layer having the double structure is formed through an exposure process to which a halftone mask is applied. The method of claim 1 , wherein the channel layer comprises a ZnON-based semiconductor material. The method of claim 1 , wherein the layer structure of the channel layer and the first etch stop layer is formed by continuous deposition. 5 . The method of claim 1 , wherein at least a portion of the gate insulating layer other than the lower region of the channel layer is thinner than a thickness of the lower region of the channel layer. The method of claim 5 , wherein the gate insulating layer is formed of a material that can be simultaneously etched during the secondary etching process of the first etch stop layer. The method of any one of claims 1 to 4, wherein the gate insulating layer is formed of a material that can be etched simultaneously during the secondary etching process of the first etch stop layer. The method of claim 7 , wherein a portion of the gate insulating layer is etched during the secondary etching process of the first etch stop layer to form a step height. The method of claim 1 , further comprising: forming a second etch stop layer to cover the stepped channel layer and the first etch stop layer. gate insulating layer;
a channel layer formed on the gate insulating layer and including a ZnON-based semiconductor material;
a first etch stop layer formed on the channel layer;
a source electrode and a drain electrode respectively contacting the channel layer; and
The gate insulating layer is formed such that at least a partial thickness of a portion other than the lower region of the channel layer is thinner than a thickness of the lower region of the channel layer;
The channel layer is stepped with respect to the gate insulating layer, and the first etch stop layer has a stepped structure with respect to the channel layer,
The thin film transistor further comprising a; second etch stop layer formed to cover the stepped gate insulating layer, the channel layer, and the first etch stop layer. The thin film transistor of claim 10 , wherein the gate insulating layer, the channel layer, and the first etch stop layer are formed by continuous deposition and are formed in a stepped structure through an etching process. The thin film transistor of claim 11 , wherein the gate insulating layer is formed of an etchable material when the first etch stop layer is etched. delete delete A display using the thin film transistor of any one of claims 10 to 12 as at least one of a driving element and a switching element.

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